DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 16 January 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 19 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 19 includes the phrase “the reset ready signal”. This phrase lacks antecedent basis in the claim. It is unclear whether claim 19 was intended to depend on claim 18 which includes “a reset ready signal” or claim 19 was intended to state “a reset ready signal” instead.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 15, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Siluvainathan et al. (US 2025/0060908) as supported by its provisional application.
References to the specification of Siluvainathan below include two citations: the first to Siluvainathan and the second to its provisional application.
In regards to claim 1, Siluvainathan as supported by its provisional application teaches a memory system (memory system 104, figure 1) comprising:
a memory device (first memory device 118, figure 1); and
a memory controller (controller 112, figure 1) configured to
execute firmware which controls the memory device (“In an example, at operation 524, the bootloader starts and loads a firmware image (e.g., a new or updated firmware image) to the subsystem manager circuit 412, and then loads a firmware image (e.g., a new or updated firmware image) to the host interface circuit 410.”, paragraph 0084, paragraph 0084),
perform, when an abnormal event of the firmware is sensed (“In an example, the first method 700 includes detecting a reset condition at a CXL device at operation 702. For example, operation 702 can include detecting a reset condition or receiving a reset trigger at the example CXL device 402. The reset condition or trigger can include or can indicate a firmware update, a detected device fault or failure, or other condition.”, paragraph 0091, paragraph 0091), data communication with a host, based on hardware in place of the firmware (“At operation 706, the first method 700 can include using the host interface circuit 410 of the example CXL device 402 to maintain a connection between the example CXL device 402 and the host device. Maintaining the connection at operation 706 can include acknowledging main-band or side-band requests or commands from the host device.”, paragraph 0094, paragraph 0093), and
reset the memory device (“At operation 708, the first method 700 can include resetting the subsystem manager circuit 412 of the example CXL device 402. Resetting the subsystem manager circuit 412 can include, for example, loading new or updated ROM code, or changing other configuration registers or commands for the example CXL device 402, and can further include rebooting and initializing the subsystem manager circuit 412. “, paragraph 0095, paragraph 0094) when access traffic of the host to the memory device is a threshold value or less (“At operation 704, the first method 700 can include quiescing transactions between the CXL device and a host device. In an example, operation 704 includes reducing to zero a number of CXL transaction credits issued by the example CXL device 402 to the host device.”, paragraph 0093, paragraph 0092).
In regards to claim 15, Siluvainathan as supported by its provisional application teaches a method of operating a memory system (memory system 104, figure 1) including a memory device (first memory device 118, figure 1), the method comprising:
sensing an abnormal event of firmware which controls the memory device (“In an example, the first method 700 includes detecting a reset condition at a CXL device at operation 702. For example, operation 702 can include detecting a reset condition or receiving a reset trigger at the example CXL device 402. The reset condition or trigger can include or can indicate a firmware update, a detected device fault or failure, or other condition.”, paragraph 0091, paragraph 0091);
performing, in response to the abnormal event of the firmware (“In an example, the first method 700 includes detecting a reset condition at a CXL device at operation 702. For example, operation 702 can include detecting a reset condition or receiving a reset trigger at the example CXL device 402. The reset condition or trigger can include or can indicate a firmware update, a detected device fault or failure, or other condition.”, paragraph 0091, paragraph 0091), data communication with a host, based on hardware in place of the firmware (“At operation 706, the first method 700 can include using the host interface circuit 410 of the example CXL device 402 to maintain a connection between the example CXL device 402 and the host device. Maintaining the connection at operation 706 can include acknowledging main-band or side-band requests or commands from the host device.”, paragraph 0094, paragraph 0093); and
resetting the memory device (“At operation 708, the first method 700 can include resetting the subsystem manager circuit 412 of the example CXL device 402. Resetting the subsystem manager circuit 412 can include, for example, loading new or updated ROM code, or changing other configuration registers or commands for the example CXL device 402, and can further include rebooting and initializing the subsystem manager circuit 412. “, paragraph 0095, paragraph 0094) when access traffic of the host to the memory device is a threshold value or less (“At operation 704, the first method 700 can include quiescing transactions between the CXL device and a host device. In an example, operation 704 includes reducing to zero a number of CXL transaction credits issued by the example CXL device 402 to the host device.”, paragraph 0093, paragraph 0092).
In regards to claim 20, Siluvainathan as supported by its provisional application further teaches that performing the data communication includes:
receiving a request including a second protocol message from the host (“the host interface circuit is configured to coordinate a device response to any one or more of a PCIe reset, a CXL reset (e.g., as notified using CXL.io to write to a memory mapped register of the CXL device)”, paragraph 0112, paragraph 0111);
analyzing the second protocol message in response to the request (“the host interface circuit is configured to coordinate a device response to any one or more of a PCIe reset, a CXL reset (e.g., as notified using CXL.io to write to a memory mapped register of the CXL device)”, paragraph 0112, paragraph 0111);
generating a response to the second protocol message, using a target interface corresponding to the analyzed message (“the host interface circuit is configured to coordinate a device response to any one or more of a PCIe reset, a CXL reset (e.g., as notified using CXL.io to write to a memory mapped register of the CXL device)”, paragraph 0112, paragraph 0111); and
providing the host with a response to the second protocol message (“the host interface circuit is configured to coordinate a device response to any one or more of a PCIe reset, a CXL reset (e.g., as notified using CXL.io to write to a memory mapped register of the CXL device)”, paragraph 0112, paragraph 0111),
wherein a second protocol message includes a CXL.io protocol message (“the host interface circuit is configured to coordinate a device response to any one or more of a PCIe reset, a CXL reset (e.g., as notified using CXL.io to write to a memory mapped register of the CXL device)”, paragraph 0112, paragraph 0111), and
wherein the target interface includes a mailbox type or a Vendor Defined Message (VDM) type (“The CXL specification provides mailbox commands to update firmware.”, paragraph 0067, paragraph 0066).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Siluvainathan et al. (US 2025/0060908) as supported by its provisional application in view of Am et al. (US 2024/0103720).
In regards to claims 2 and 16, Siluvainathan as supported by its provisional application teaches claims 1 and 16. Siluvainathan as supported by its provisional application fails to adequately teach that the memory controller is further configured to monitor the access traffic. Am teaches that the memory controller is further configured to monitor the access traffic (“In one embodiment, the RAC 230 may be configured to trigger the reset based on a specified level (e.g., less than 5%) of read/write traffic happening to the respective NVMe SSDs.”, paragraph 0066) in order to alleviate potential disk corruption (paragraph 0075). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Siluvainathan as supported by its provisional application with Am such that the memory controller is further configured to monitor the access traffic in order to alleviate potential disk corruption (id.).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Siluvainathan et al. (US 2025/0060908) as supported by its provisional application in view of Am et al. (US 2024/0103720), Nachimuthu et al. (US 2019/0243637), and Yoo et al. (US 2023/0153038).
In regards to claim 3, Siluvainathan as supported by its provisional application in view of Am teaches claim 2. Siluvainathan as supported by its provisional application in view of Am fails to teach that the memory controller includes a firmware driver configured to execute the firmware, and activate a firmware abnormal signal when the abnormal event of the firmware is sensed, and
wherein, when a dump request is generated due to a crash in a central processing unit (CPU) of the memory controller or when entrance into a sleep mode is made due to a request of the host or a policy of the memory system, the firmware driver is configured to sense the abnormal event of the firmware, suspend the execution of the firmware, and activate the firmware abnormal signal.
Nachimuthu teaches that the memory controller includes a firmware driver configured to execute the firmware (“Alternatively, the described embodiments can be implemented at least in part as executable code, or firmware, programmed or embedded into dedicated hardware such as an integrated circuit (e.g., an application specific IC or ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), or controller which can be accessed via a corresponding driver and/or operating system from an application.”, paragraph 0067), and
wherein, when a dump request is generated due to a crash in a central processing unit (CPU) of the memory controller or when entrance into a sleep mode is made due to a request of the host (“Finally, at 318, the OS requests entry into the sleep state S1/S2/S3 by writing to the SLP_TYP register. The SLP_TYP register triggers a service management interrupt SMI in the BIOS SMM logic that causes the OS to enter the sleep state 320. In one embodiment, with reference to FIG. 3B, upon entering the sleep state, a process 300B confirms that the UEFI variable 312 (set at 310) indicates that an RFA has been requested. The UEFI variable functions as a qualifier to alter the normal sleep state processes that would otherwise occur.”, paragraphs 0039-0040) or a policy of the memory system, the firmware driver is configured to sense the abnormal event of the firmware (“In one embodiment, with reference to FIG. 3B, upon entering the sleep state, a process 300B confirms that the UEFI variable 312 (set at 310) indicates that an RFA has been requested”, paragraph 0040) and suspend the execution of the firmware (“For example, if the UEFI variable 312 has been set, the process 300B continues, first to flush CPU caches 324 and then to drain write pending queues 326 (no additional memory transactions are initiated by I/O or memory while the OS is in sleep state S1). In one embodiment, the process 300B invokes asynchronous DRAM refresh to flush the memory write pending queues. Other techniques to reduce the memory bandwidth can also be employed. At 328 the process 300B loads the new firmware in the persistent memory module in place of the current firmware.”, paragraph 0040)
which “enables new firmware for a memory device to be activated without requiring an operating system reboot” (paragraph 0018).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Siluvainathan as supported by its provisional application with Am and Nachimuthu such that the memory controller includes a firmware driver configured to execute the firmware, and activate a firmware abnormal signal when the abnormal event of the firmware is sensed, and
wherein, when a dump request is generated due to a crash in a central processing unit (CPU) of the memory controller or when entrance into a sleep mode is made due to a request of the host or a policy of the memory system, the firmware driver is configured to sense the abnormal event of the firmware, suspend the execution of the firmware, and activate the firmware abnormal signal
which “enables new firmware for a memory device to be activated without requiring an operating system reboot” (id.).
Siluvainathan as supported by its provisional application in view of Am and Nachimuthu fails to teach that the firmware driver is configured to activate a firmware abnormal signal when the abnormal event of the firmware is sensed. Yoo teaches that the firmware driver is configured to activate a firmware abnormal signal (“In operation S134, the recovery logic may be changed. When it is possible to update firmware, the memory controller 311 may send a firmware update request to the host 100 through the RAID controller 200.”, paragraph 0092) when the abnormal event of the firmware is sensed (“In operation S132, the memory controller may determine the result of the verification logic operation for the non-volatile memory. If the verification log result for the non-volatile memory is a failure, operation S133 may be performed.”, paragraph 0090) in order “to correct or recover a read error” (paragraph 0093). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Siluvainathan as supported by its provisional application with Am, Nachimuthu, and Yoo such that the firmware driver is configured to activate a firmware abnormal signal when the abnormal event of the firmware is sensed in order “to correct or recover a read error” (id.).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Siluvainathan et al. (US 2025/0060908) as supported by its provisional application in view of Am et al. (US 2024/0103720) and Nachimuthu et al. (US 2019/0243637).
In regards to claim 17, Siluvainathan as supported by its provisional application in view of Am teaches claim 16. Siluvainathan as supported by its provisional application in view of Am fails to teach that sensing the abnormal event of the firmware includes sensing the abnormal event of the firmware when a dump request is generated due to a crash in a CPU of the memory system or when entrance into a sleep mode is made due to a request of the host or a policy of the memory system. Nachimuthu teaches that sensing the abnormal event of the firmware includes sensing the abnormal event of the firmware when a dump request is generated due to a crash in a CPU of the memory system or when entrance into a sleep mode is made due to a request of the host or a policy of the memory system (“Finally, at 318, the OS requests entry into the sleep state S1/S2/S3 by writing to the SLP_TYP register. The SLP_TYP register triggers a service management interrupt SMI in the BIOS SMM logic that causes the OS to enter the sleep state 320. In one embodiment, with reference to FIG. 3B, upon entering the sleep state, a process 300B confirms that the UEFI variable 312 (set at 310) indicates that an RFA has been requested. The UEFI variable functions as a qualifier to alter the normal sleep state processes that would otherwise occur.”, paragraphs 0039-0040) which “enables new firmware for a memory device to be activated without requiring an operating system reboot” (paragraph 0018). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Siluvainathan as supported by its provisional application with Am and Nachimuthu such that sensing the abnormal event of the firmware includes sensing the abnormal event of the firmware when a dump request is generated due to a crash in a CPU of the memory system or when entrance into a sleep mode is made due to a request of the host or a policy of the memory system which “enables new firmware for a memory device to be activated without requiring an operating system reboot” (id.).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Siluvainathan et al. (US 2025/0060908) as supported by its provisional application in view of Am et al. (US 2024/0103720) and Grosz et al. (KR 10-2021-0008923) as supported by its translation.
All subsequent references to Grosz are to its translation.
In regards to claim 19, Siluvainathan as supported by its provisional application in view of Am teaches claim 16. Siluvainathan as supported by its provisional application in view of Am fails to teach that the resetting of the memory device includes:
providing the host with a reset schedule notification for the memory device in response to the reset ready signal; and
outputting a reset signal to the memory device when a response to the reset schedule notification is received from the host or when a predetermined time elapses after providing the reset schedule notification to the host.
Grosz as supported by its translation teaches that the resetting of the memory device includes:
providing the host with a reset schedule notification for the memory device in response to the reset ready signal (“In some cases, when the adaptive watchdog module resets the memory device, the memory device or adaptive watchdog module notifies the host of a watchdog initiated reset to reset the host timeout timer”, page 4, paragraph 4); and
outputting a reset signal to the memory device when a response to the reset schedule notification is received from the host or when a predetermined time elapses after providing the reset schedule notification to the host (“For example, the host can associate a timer with the host timeout value for each command issued by the host to the memory device, and the command given before the host's timeout value (e.g., before the host times out) If not successfully performed by the memory device, the host can send a reset signal to the memory device.”, page 4, paragraph 3)
“to avoid deadlock or crash conditions” (page 3, paragraph 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Siluvainathan as supported by its provisional application with Am and Grosz as supported by its translation such that the resetting of the memory device includes:
providing the host with a reset schedule notification for the memory device in response to the reset ready signal; and
outputting a reset signal to the memory device when a response to the reset schedule notification is received from the host or when a predetermined time elapses after providing the reset schedule notification to the host
“to avoid deadlock or crash conditions” (id.).
Allowable Subject Matter
Claims 4-14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach that “the memory controller includes an operation manager configured to perform, in response to a firmware abnormal signal, the data communication with the host based on the hardware in place of the firmware, and reset the memory device when the access traffic is the threshold value or less” and the combination of “measuring the access traffic through a snoop transaction on a first protocol message received from the host” and “wherein the first protocol message includes a CXL.mem protocol message” in conjunction with the other claim limitations, nor would it have been obvious.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Muthiah (US 2021/0382780) teaches a hardware watchdog for storage system crash analysis.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 9 March 2026