Prosecution Insights
Last updated: September 19, 2026
Application No. 19/023,394

PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Jan 16, 2025
Priority
Jan 31, 2024 — JP 2024-012793
Examiner
JACKSON, STEPHEN W
Art Unit
Tech Center
Assignee
Ablic Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
996 granted / 1077 resolved
+32.5% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
9 currently pending
Career history
1080
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
24.5%
-15.5% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1077 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (2010/0123984A1). Lin discloses a protection circuit 200, comprising: a protection transistor 202, comprising a first end, a second end, and a control end, the first end being connected with a first end of a current path formed by a parasitic diode D1 of a semiconductor element 232 comprised in an internal circuit, and the second end being connected with a first power supply terminal Vdd; and a current limiting circuit D1,R2, connected in parallel with the protection transistor 202. With regard to claim 8, Lin discloses a semiconductor device, comprising: the protection circuit as claimed in claim 1; and a protected circuit 210, having the internal circuit. Allowable Subject Matter Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claims 2-7 recite additional features, such as the step-down circuit of claim 2, that have not been taught or been fairly suggested by the prior art of record. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN W JACKSON whose telephone number is (571)272-2051. The examiner can normally be reached M-F 6:30-3:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SWJackson August 7, 2026 /STEPHEN W JACKSON/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jan 16, 2025
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102
Sep 17, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12733144
ELECTRONIC DEVICE COMPRISING CONDUCTIVE CONNECTOR
2y 2m to grant Granted Sep 08, 2026
Patent 12726013
LEAKAGE PROTECTION CIRCUIT AND LIGHTING SYSTEM
2y 9m to grant Granted Sep 01, 2026
Patent 12724060
System and Method for Locating Remote Earth Fault Section in Power Grids
1y 2m to grant Granted Sep 01, 2026
Patent 12719262
METHODS AND SYSTEMS FOR CONFIGURING ELECTRONIC FUSES
3y 3m to grant Granted Aug 25, 2026
Patent 12719259
OVERCURRENT PROTECTION APPARATUS AND PROTECTION METHOD THEREOF
2y 7m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+7.3%)
2y 2m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1077 resolved cases by this examiner. Grant probability derived from career allowance rate.

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