DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement submitted on 16 Jan 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because:
Fig 1: the inputs to the differential amplifier are connected opposite of the specification [0018] description of the inputs to the differential amplifier: "the non-inverting input terminal of the differential amplifier circuit 30 receives the reference voltage VREF. In addition, the inverting input terminal of the differential amplifier circuit 30 receives a voltage obtained by dividing the output voltage VOUT".
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
[0018]: "the non-inverting input terminal of the differential amplifier circuit 30 receives the reference voltage VREF. In addition, the inverting input terminal of the differential amplifier circuit 30 receives a voltage obtained by dividing the output voltage VOUT". This description is the opposite of what is depicted in Fig 1.
Appropriate correction is required.
Claim Objections
Claims 1-7 are objected to because of the following informalities:
Claim 1, line 4: the limitation "output terminal" is a generic term that is used as part of the voltage regulator and differential amplifier circuit. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 2-7 depend from Claim 1 and thus have at least the same defect(s).
Claims 1-6: the limitation "gate terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 1-6: the limitation "source terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 1-6: the limitation "threshold voltage" is a generic term that is used as a property of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 2-6: the limitation "drain terminal" is a generic term that is used as part of multiple transistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 3-4 and 6: the limitation "one terminal" is a generic term that is used as part of multiple resistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claims 3-4 and 6: the limitation "other terminal" is a generic term that is used as part of multiple resistors. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lou (US 20090224737 A1).
Regarding Claim 1, Lou discloses a voltage regulator (voltage regulator 400, Fig 4) comprising: a first transistor (402, Fig 4) provided between an input terminal to which an input voltage is applied (source of 402 connected to Vin1, Fig 4) and an output terminal from which an output voltage is outputted (drain of 402 connected to Vout, Fig 4); a differential amplifier circuit (401, Fig 4) connected to provide negative feedback between a predetermined reference voltage (Vref, Fig 4) and a voltage based on the output voltage outputted from the output terminal (401 provides negative feedback/compensation of variations in the output voltage Vfb, Fig 4, [0004-5, 0019]); and an inverting amplifier connected to an output terminal of the differential amplifier circuit (403 and 404 connected to the output of 401, Fig 4), a gate terminal of the first transistor (403 and 404 connected to the gate of 402, Fig 4), and the input terminal (403 and 404 connected to Vin1, Fig 4), wherein the inverting amplifier comprises: a second transistor (403, Fig 4) comprising a gate terminal connected to the output terminal of the differential amplifier circuit (gate of 403 is connected to the output of 401, Fig 4), and a source terminal which is grounded (source of 403 is connected to ground, Fig 4); and a current adjustment circuit (404, Fig 4) capable of flowing current from the input terminal to the second transistor even with a gate voltage of the first transistor being in the vicinity of a threshold voltage ("The constant current source 405 provides a constant current Ib, and the transconductance amplifier 404a thus equivalently biases the control transistor 403 and the output transistor 402 with a DC current of ( N - 1 ) 2 Ib." Because 404a2's bias derives from 405 rather than the gate of 402 itself, it necessarily continues to source current into that node regardless of where the node sits relative to the threshold voltage, Fig 4-5, [0022]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lou (US 20090224737 A1) in view of Bedarida (US 6624683 B1).
Regarding Claim 2, Lou discloses all of the limitations of claim 1.
Lou does not disclose wherein the current adjustment circuit comprises a third transistor, the third transistor comprising a gate terminal connected to the gate terminal of the first transistor, a drain terminal connected to the gate terminal of the third transistor, and a source terminal connected to the input terminal, wherein a threshold voltage of the third transistor is smaller than the threshold voltage of the first transistor.
Bedarida teaches a conventional diode-connected transistor (see Fig 3) including wherein the current adjustment circuit comprises a third transistor (301, Fig 3), the third transistor comprising a gate terminal connected to the gate terminal of the first transistor (gates of 300 and 301 are connected together, Fig 3), a drain terminal connected to the gate terminal of the third transistor (gate 306 and drain 307 of 301 are connected together, Fig 3), and a source terminal connected to the input terminal (source terminal 305 is connected to Lou's Vin1, Fig 3), wherein a threshold voltage of the third transistor is smaller than the threshold voltage of the first transistor ("The transistor 300 has associated a threshold VT2 and the transistor 301 has associated a threshold VT1. The threshold voltage VT2, in absolute value, is greater than the threshold voltage VT1.", Fig 3, Col 3[23-5]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the diode-connected transistor in Lou, as taught by Bedarida, as it provides the advantage of obtaining a lower, more precisely controllable effective threshold voltage at low-cost (Col 1[56-63] of Bedarida).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lou (US 20090224737 A1) in view of Wang (US 20130009253 A1).
Regarding Claim 3, Lou discloses all of the limitations of claim 1.
Lou does not disclose wherein the current adjustment circuit comprises: a fourth transistor comprising a gate terminal connected to the gate terminal of the first transistor, a drain terminal connected to the gate terminal of the fourth transistor, and a source terminal connected to the input terminal, wherein a threshold voltage of the fourth transistor is substantially the same as the threshold voltage of the first transistor; and a first resistor comprising one terminal connected to the source terminal of the fourth transistor, and the other terminal connected to the drain terminal of the fourth transistor.
Wang teaches a conventional diode-connected MOSFET and gate resistor (see Fig 2) including wherein the current adjustment circuit comprises: a fourth transistor (212, Fig 2) comprising a gate terminal connected to the gate terminal of the first transistor (212's gate connected to the gate of 202, Fig 2), a drain terminal connected to the gate terminal of the fourth transistor (drain 214 connected to the gate 204, Fig 2), and a source terminal connected to the input terminal (source 216 connected to the SOURCE terminal, Fig 2); and a first resistor comprising one terminal connected to the source terminal of the fourth transistor (left side of 208 connected to source 216 of 212, Fig 2), and the other terminal connected to the drain terminal of the fourth transistor (right side of 208 connected to drain 214 of 212, Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the diode-connected transistor in Lou, as taught by Wang, as it provides the advantage of suppressing ringing at turn on/off without reducing efficiency ([0004] of Wang).
Wang does not disclose wherein a threshold voltage of the fourth transistor is substantially the same as the threshold voltage of the first transistor.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Lou, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Moreover, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPT 215 (CCPA 1980).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Lou to include wherein a threshold voltage of the fourth transistor is substantially the same as the threshold voltage of the first transistor by matching a diode-connected auxiliary transistor's threshold voltage to the driven pass transistor's threshold voltage (e.g. by common process/sizing) to achieve predictable, process- and temperature-tracking current adjustment behavior relative to the first transistor's own turn-on threshold.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lou (US 20090224737 A1) in view of Yasukochi (JP 2010086013 A).
Regarding Claim 7, Lou discloses all of the limitations of claim 1.
Lou does not disclose semiconductor device comprising the voltage regulator according to claim 1.
Yasukochi teaches a conventional semiconductor device (see Fig 1) including a semiconductor device comprising the voltage regulator according to claim 1 ("A semiconductor device characterized by being equipped with a linear regulator circuit according to any one of claims 1 to 3", Claim 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the semiconductor device in Lou, as taught by Yasukochi, as it provides the advantage of integrated implementation suited for mobile electronic systems ([0005] of Lou).
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and all limitations of any intervening claims, which would comprise a particular combination of elements that is neither taught nor suggested by the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 9/14/2026
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