DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 31 July 2026 have been entered. Claims 1-10 remain pending in the application. The Applicant’s amendments to the claims overcome some of the objections and 112(b) rejections previously set forth in the Non-Final Rejection dated 03 June 2026, and the amendments also overcome the 103 rejections as previously written.
Response to Arguments
Applicant's arguments filed 31 July 2026 have been fully considered but they are not persuasive.
On pages 11-12, the Applicant argues that the combination of, specifically, Allen and Swanson fails to teach: (1) symmetric spiral fine-tuning delay lines arranged on both reference optical path and sample optical path (however, Allen clearly teaches a spiral delay line (40) and Swanson clearly teaches variable delays provided in both the reference and sample arms (¶21); (2) a reference-path-only cascaded delay link with exponentially increasing foxed delay segments (however, Allen very clearly teaches this cascade link structure in figure 5 and the associated ¶¶64-75, and it should be noted that, according to the claim language, the spiral delay structure and cascaded delay link need not exist simultaneously due to the “or” statement); and (3) coarse fixed delays coordinated with symmetric fine spiral delays to achieve continuous optical path different tuning starting from zero delay offset (however, the only part of the above statement that is claimed is the fixed delay and/or symmetric spirals, and Allen teaches both the fixed delay and the spiral structures. Regarding that symmetrical nature of the spiral delays, without showing criticality of the symmetrical nature, it would have been obvious, through routine experimentation, to position the delay structures in order to produce the best result for variable delay as well as device packaging).
Additionally, on pages 12-14, the Applicant argues that a PHOSITA would lack any motivation to combine Allen and Swanson since no technical problem with Allen has been mentioned in Allen, however, the Examiner disagrees. Swanson clearly states that, in order to accomplish matching of the path lengths and variability of the reference and sample arms of an OCT system, the variable delay may be placed in the sample arm, the reference arm, or both the sample arm and the reference arm. Therefore the variable delay in the sample arm, the reference arm, or both the sample arm and the reference arm are merely obvious variants that, through routine experimentation, a user could choose between in order to produce the best path length matching.
Additionally, on page 13, the Applicant argues that “the integrated course+fine zero-start continuous optical delay solution delivers an unexpected technical advantage: full, uninterrupted (gap-free) depth scanning across the entire detection range without imaging gaps or axial resolution degradation” However, this is not claimed. The claims merely state that an optical delay line exists in both the sample arm and the reference arm, and that the delay line can be spiral or a cascaded optical delay link. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims… Various limitations on which appellant relied were not stated in the claims; the specification did not provide evidence indicating these limitations must be read into the claims to give meaning to the disputed terms (MPEP 2145 VI). Additionally, The fact that appellant has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious (MPEP 2145 II).
For the reasons set forth above, Allen and Swanson (in addition to Aggarwal and Yu) still teach the limitations of claim 1.
Claim Objections
Claims 1-2, 4-5, and 10 are objected to because of the following informalities:
Claim 1: “the first continuously adjustable optical delay line” in line 37 should be “the first optical delay line”; “the second continuously adjustable optical delay line” in lines 37-38 should be “the second optical delay line”; “the first spiral continuously adjustable optical delay line” in lines 43-44 and 47-48 respectively should be “the first optical delay line”; and “the second spiral continuously adjustable optical delay line” in lines 45-46 and 48-49 respectively should be “the second optical delay line” for further clarity and continuity.
Claim 2: “the N-level cascaded fixed optical delay line” in line 2 should be “the N-level cascaded optical delay line”; “the first spiral continuously adjustable optical delay line” in lines 6-7 should be “the first optical delay line”; and “the second spiral continuously adjustable optical delay line” in line 7 should be “the second optical delay line” for further clarity and continuity in the claim language.
Claim 4: “the N+1-level cascaded optical switches” in line 2 should be “the N+1-level cascaded 2×2 adiabatic directional coupler or multimode interferometer optical switches” for further clarity and continuity in the claim language.
Claim 5: “the first spiral continuously adjustable optical delay line” in lines 3-4 should be “the first optical delay line”; “the second spiral continuously adjustable optical delay line” in lines 4-5 should be “the second optical delay line”; “the N+1-level cascaded optical switches” in line 5 should be “the N+1-level cascaded 2×2 adiabatic directional coupler or multimode interferometer optical switches”; and “sample path” in line 12 should be “the sample path” for further clarity and continuity in the claim language.
Claim 10: “transmits” in line 19 should be “transmitting” for further clarity in the claim language. Additionally, “the two paths” in lines 43-44 should be “the reference path and the sample path” for further clarity and continuity in the claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, “an analog-to-digital acquisition circuitry” in line 4 is not supported by the Applicant’s specification. There is no mention analog signals, digital signals, or any conversion between the analog and digital signals. Additionally, “image calculation hardware” in line 4 is not supported by the Applicant’s specification. There is mention of a data processing module with no associated hardware. Additionally, “the analog-to-digital acquisition circuitry receives the electrical signal output by the photoelectric detection assembly, and transmits digitized signal data to the image calculation hardware” in lines 20-22 is not supported by the Applicant’s specification. Again, there is no mention analog signals, digital signals, or any conversion between the analog and digital signals and there is no hardware associated with the processing modules in the specification. Additionally, “the image calculation hardware processes the digitized signal data to reconstruct a tomographic image of the sample to be scanned” in lines 23-25 in not supported by the specification for the same reasons mentioned above and in addition, there is no mention of image reconstruction.
Claims 2-9 are rejected for their dependency on claim 1.
Regarding claim 5, “wherein the control module includes a thermo-optic driving circuit and an optical switch driving circuit” in lines 2-3 is not supported by the Applicant’s specification. While the selection of an output path being controlled by a thermos-optic effect of a silicon nitride waveguide is mentioned in paragraph 52, there is no mention of driving circuitry for either switches or the thermos-optic effects.
Regarding claim 7, “the analog-to-digital acquisition circuitry” in lines 2-3 and 12-13 respectively are not supported by the Applicant’s specification. There is no mention analog signals, digital signals, or any conversion between the analog and digital signals.
Regarding claim 10, “receiving the electrical signal by a sample acquisition module an analog-to-digital acquisition circuitry including a timing synchronization analog-to-digital circuit and transmitting transmits the electrical signal to a data processing module an image calculation hardware including an FPGA and an image reconstruction host; processing the electrical signal to obtain an image of the sample to be scanned by the data processing module image calculation hardware” in lines 17-22 is not supported by the Applicant’s specification. There is no mention analog signals, digital signals, or any conversion between the analog and digital signals. Additionally, there is mention of a data processing module with no associated hardware. Additionally, there is no mention of an FPGA or image reconstruction in the specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, “a reference path” in line 27 is unclear as this limitation has been mentioned previously in line 5 of the same claim. Is this limitation referring to the same reference path mentioned previously or a different reference path? In light of the specification, the Examiner is interpreting this limitation to be referring to the same reference path mentioned previously. Additionally, “a sample path” in line 27 is unclear as this limitation has been mentioned previously in line 6 of the same claim. Is this limitation referring to the same sample path mentioned previously or a different sample path? In light of the specification, the Examiner is interpreting this limitation to be referring to the same sample path mentioned previously. Additionally, “a first optical delay line” in line 29 is unclear as an optical delay line arranged on both the reference path and the sample path respectively has already been mentioned previously in lines 5-6 of the same claim. Is this limitation referring to the optical delay lines mentioned previously or a different optical delay line? In light of the specification, the Examiner is interpreting this limitation to be referring to the same optical delay line mentioned previously. Additionally, “a second optical delay line in lines 29-30 is unclear as an optical delay line arranged on both the reference path and the sample path respectively has already been mentioned previously in lines 5-6 of the same claim. Is this limitation referring to the optical delay lines mentioned previously or a different optical delay line? In light of the specification, the Examiner is interpreting this limitation to be referring to the same optical delay line mentioned previously. Additionally, “each of the first continuously adjustable optical delay line and the second continuously adjustable optical delay line is of a spiral structure; and/or the reference path of the optical chip has a cascaded delay” is followed by limitations treating the above limitation as an “and” statement as opposed to a possible “or” statement; this is unclear. If the Applicant intends to have the above limitation treated as an “and/or” statement, then the claim must be amended to reflect that, otherwise the limitation should be amended to merely an “and” statement.
Claims 2-9 are rejected for their dependency on claim 1.
Regarding claim 2, “the fixed delay amount” in lines 4-5 lacks proper antecedent basis and is therefore unclear.
Regarding claim 4, “a 2×2 type adiabatic coupler” in line 2 is unclear as this limitation has been mentioned previously in claim 1, on which claim 4 is dependent. Is this limitation referring to the same 2×2 type adiabatic coupler mentioned previously or a different 2×2 type adiabatic coupler? In light of the specification, the Examiner is interpreting this limitation to be referring to the same 2×2 type adiabatic coupler mentioned previously. Additionally, “a multimode interferometer” in lines 2-3 is unclear as this limitation has been mentioned previously in claim 1, on which claim 4 is dependent. Is this limitation referring to the same multimode interferometer mentioned previously or a different multimode interferometer? In light of the specification, the Examiner is interpreting this limitation to be referring to the same multimode interferometer mentioned previously.
Regarding claim 5, “a target delay amount” in line 9 is unclear as a target value has been mentioned previously in claim 1, on which claim 5 is dependent. Is this limitation referring to the same target value mentioned previously or a different target delay amount? In light of the specification, the Examiner is interpreting this limitation to be referring to the same target value mentioned previously. Additionally, “a plurality of optical switches” in lines 9-10 is unclear as the N+1-level cascaded 2×2 adiabatic directional coupler or multimode interferometer optical switch has been mentioned previously in claim 1, on which claim 5 is dependent. Is this limitation referring to the same N+1-level cascaded 2×2 adiabatic directional coupler or multimode interferometer optical switches mentioned previously or a different plurality of switches? In light of the specification, the Examiner is interpreting this limitation to be referring to the same N+1-level cascaded 2×2 adiabatic directional coupler or multimode interferometer optical switches mentioned previously. Additionally, “the delay amount of the first optical delay line” in lines 10-11 and “the delay amount of the second optical delay line” in line 11 both lack proper antecedent basis and are therefore both unclear. Additionally, “a relative delay amount” in line 12 is unclear as this limitation has been mentioned previously in claim 1, on which claim 5 is dependent. Is this limitation referring to the same relative delay amount mentioned previously or a different relative delay amount? In light of the specification, the Examiner is interpreting this limitation to be referring to the same relative delay amount mentioned previously.
Regarding claim 7, “an interference” in line 9 is unclear as this limitation has been mentioned previously in claim 1, on which claim 7 is dependent. Is this limitation referring to the same interference mentioned previously or a different interference? In light of the specification, the Examiner is interpreting this limitation to be referring to the same interference mentioned previously.
Regarding claim 10, “a detection light” in line 4 is unclear as this limitation has been mentioned previously in line 3 of the same claim. Is this limitation referring to the same detection light mentioned previously or a different detection light? In light of the specification, the Examiner is interpreting this limitation to be referring to the same detection light mentioned previously. Additionally, “a first optical delay line” in line 25 is unclear as a first spiral continuously adjustable optical delay line has been mentioned previously in lines 5-6 of the same claim. Is this limitation referring to the first spiral continuously adjustable optical delay line mentioned previously or a different first optical delay line? In light of the specification, the Examiner is interpreting this limitation to be referring to the first spiral continuously adjustable optical delay line mentioned previously. Additionally, “a second optical delay line” in line 25 is unclear as a second spiral continuously adjustable optical delay line has been mentioned previously in lines 6-7 of the same claim. Is this limitation referring to the second spiral continuously adjustable optical delay line mentioned previously or a different second optical delay line? In light of the specification, the Examiner is interpreting this limitation to be referring to the second spiral continuously adjustable optical delay line mentioned previously. Additionally, “the optical delay line” in line 33 is unclear as there have been two optical delay lines mentioned previously (at least under the Examiner’s interpretation). To which optical delay line is this limitation referring? In light of the specification, the Examiner is interpreting this limitation to be referring to both the first and second optical delay lines mentioned previously. Additionally, “the optical delay line is of a spiral nature; and/or the reference path of the optical chip further has a cascaded delay link” is preceded and followed by limitations treating the above limitation as an “and” statement as opposed to a possible “or” statement; this is unclear. If the Applicant intends to have the above limitation treated as an “and/or” statement, then the claim must be amended to reflect that, otherwise the limitation should be amended to merely an “and” statement. Additionally, “the optical delay line” in line 36 is unclear as a first optical delay line, a second optical delay line, and an N-level cascaded optical delay line have been mentioned previously in the same claim (at least under the Examiner’s interpretation). To which optical delay line is this limitation referring? In light of the specification, the Examiner is interpreting this limitation to be referring to the N-level cascaded optical delay line mentioned previously.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-6, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Allen et al. (USPGPub 20230414103 A1) in view of Swanson (USPGPub 20210356249 A1), Aggarwal et al. (USPGPub 20250216632 A1) and Yu et al. (USPGPub 20250362533 A1).
Regarding claim 1, Allen teaches a time domain coherence tomography system based on a photonic integrated chip (11) (abstract, An apparatus for optical coherence tomography (OCT) scanning is described; and ¶1, The invention seeks to implement an OCT scanner using photonic integrated circuit technology), comprising a light source (10), an optical chip (11), an interferometer (20), a photoelectric detection assembly, and an image calculation hardware (21), wherein the light source (10) is connected to the interferometer (20) by the optical chip (11) (see figure 2, broadband light source 10, photonic integrated circuit 11, spectrometer 20 (i.e. interferometer), and processor 21 (i.e. image calculation hardware)), and an optical delay line (18), wherein the optical delay line is continuously adjustable (see figure 2, variable delay 18; ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively; and see ¶¶45-48 for further details); the light source (10) is configured to emit a detection light (¶39, the broadband light source 10 provides a photonic input signal to the module 11); the optical chip (11) is configured to divide the detection light into a reference path signal light and a sample path signal light, and transmit the reference path signal light by the continuously adjustable optical delay line (18) and the sample path signal light to the interferometer (20) (¶39, The module 11 has a 2×2 coupler 17 which splits the initial input signal into two signals; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); the interferometer (20) is configured to transmit the reference path signal light to generate a reference signal, and transmit the reference signal to the photoelectric detection assembly; and configured to transmit the sample path signal light to a sample to be scanned to generate a reflection signal, and transmit the reflection signal to the photoelectric detection assembly (¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively; and ¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20); the photoelectric detection assembly receives the reference signal and the reflection signal, and generates an electrical signal after an interference between the reference signal and the reflection signal (¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20. The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum); and transmits signal data to the image calculation hardware (21) (¶40, The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum… The spectral content is delivered to output image processor 21); the image calculation hardware (21) processes the signal data to reconstruct a tomographic image of the sample to be scanned (¶40, The spectral content is delivered to output image processor 21 to produce an image, which can be displayed on a display of the image processor 21 or can be analysed by that processor or can be stored and sent for remote viewing. The processor 21 builds up the image, because it “knows” the position of the x and y mirrors of the imaging optics. I.e. it has control of the scanning of the target and receives back the complete spectral results for each point/pixel/line of the scan, so it is able to build the image from the results for each spatial position it selects); the optical chip includes an optical input port (14), a light splitter (17), a reference path, a sample path, a first output port, and a second output port (see figure 2, optical port 14 (i.e. optical input port) having coupler 17 (i.e. splitter), two unlabeled output paths that include both a reference and sample path, the paths being arranged respectively and symmetrically, two output ports via waveguides 15 and 23); after having been input by the optical input port (14), the detection light is divided into the reference path signal light and the sample path signal light by the light splitter (17), while the reference path signal light is output by the first output port, and the sample path signal light is output by the second output port (see figure 2; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); the optical delay line (18) is of a spiral structure (see figure 4; and ¶75, In some embodiments, a combined version of the binary delay 50 and the tunable spiral waveguide with at least one phase shifter configurations could also be implemented in the variable delay 18); and/or the reference path of the optical chip further has a cascaded delay link arranged, the cascaded delay link is formed by an N+1-level cascaded 2x2 adiabatic directional coupler or multimode interferometer optical switch and an N-level cascaded optical delay line, while an optical delay amount of each level of the N-level cascaded optical delay line is fixed but different; wherein N is a positive integer (see figure 5; ¶64, a binary delay 50 with several integrated tunable switches 511, 512, 513, 514, and 515 where ‘L’ stands for a pre-defined unit delay. The upper ‘rail’ on the binary delay 50 have fibre optic, free space, or integrated photonic delay lines 52, 53, 54, and 55 of lengths L, 2L, 4L, and 8L respectively between each tunable switch 511, 512, 513, 514, and 515 that may have an order of magnitude of 2.sup.n which correspond to delays of 2.sup.n unit delays, where n is a positive integer; and see figures 3a-3c, different types of switches that can be used, including direction coupler, multimode interferometer, and Mach-Zehnder interferometer); the reference path signal light passes through the first spiral continuously adjustable optical delay line and passes through the cascaded delay link, and being output by the first output port (¶64, The combination of the two rails results in a reprogrammable path length, wherein a desired delay to the reference signal can be implemented; and ¶75, In some embodiments, a combined version of the binary delay 50 and the tunable spiral waveguide with at least one phase shifter configurations could also be implemented in the variable delay 18); the sample path signal light being output by the second output port directly (see figure 2; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); after determining a delay matching most with a desired delay amount, through the first spiral continuously adjustable optical delay line and the sample path at a front end, a relative delay amount of the two paths is accurately locked to a target value (¶65, In operation, the multiple of L is calculated for a desired delay, and the tunable switches are configured so that the signal travels a path length matching the desired delay). However, Allen fails to explicitly teach an analog-to-digital acquisition circuitry; and wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively; wherein the analog-to-digital acquisition circuitry receives the electrical signal output by the photoelectric detection assembly, and outputs a digitized signal; wherein the input and output ports are formed by respective edge couplers; wherein a first optical delay line which is continuously adjustable and a second optical delay line which is continuously adjustable are arranged respectively and symmetrically; and wherein the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Swanson teaches an analog-to-digital acquisition circuitry (¶32, Light from the swept laser 102 is directed to the sample 105 and light reflected from the sample 105 is directed back to the receiver section containing components, such as one or more polarization beam splitters 109, 180-degree optical hybrids 110, photodetectors 111, transimpedance amplifiers 112, and analog to digital converters 113); and wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively (¶21, This type of variable delay may be placed in the sample arm, the reference arm, or both the sample arm and the reference arm); wherein the analog-to-digital acquisition circuitry receives the electrical signal output by the photoelectric detection assembly, and outputs a digitized signal (see figure 2B, ADCs 263 direct signals to the control and processing module 251).
It would have been obvious to one of ordinary skill n the art before the effective filing date of the claimed invention to modify Allen to incorporate the teachings of Swanson to further include an ADC as these transform analog signals (like light) into digital data that computers, microcontrollers, and processors can process, store, and/or transmit, as well as decreasing signal degradation that could lead to noise. Additionally, it would have been obvious to include a variable delay line in both the reference and sample paths as this is a common configuration in the technology (according to the prior art) and because [t]his VDL provides the variable delay between the two arms of the interferometer that is necessary to match their path lengths as required by the system (Swanson, ¶21). However, the combination fails to explicitly teach wherein the input and output ports are formed by respective edge couplers; wherein a first optical delay line which is continuously adjustable and a second optical delay line which is continuously adjustable are arranged respectively and symmetrically; and wherein the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Aggarwal teaches wherein the input and output ports are formed by respective edge couplers (¶105, the photonic ports, e.g., input and output photonic ports, for the active photonic component can be optically coupled to a fiber array unit (FAU)… the FAU can also be coupled to the photonic port through an edge coupler).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen and Swanson to incorporate the teachings of Aggarwal to further include an edge coupler in order to efficiently couple light from an external source into a photonic chip and vice versa. However, the combination fails to explicitly teach wherein a first optical delay line which is continuously adjustable and a second optical delay line which is continuously adjustable are arranged respectively and symmetrically; and wherein the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Yu teaches wherein the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode (¶29, one or more silicon photonic circuits 150 are provided on a layer of buried oxide (BOX) 203 disposed over a manufacturing substrate 201. Manufacturing substrate 201 can be a silicon wafer; ¶22, Silicon photonic circuit 150 can further include one or more optical structures, such as first and second waveguides 115a and 115b… First and second waveguides 115a and 115b can include elongated sections of a suitable material, such as silicon or silicon nitride; and ¶23, Silicon photonic circuit 150 may further include at least one electrode… one or more electrodes 117a-117d include stacked layers of conducting (such as metal), semi-conducting, and insulating materials).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, and Aggarwal to incorporate the teachings of Yu to include a silicon on insulator device as these devices are common in photonics. However, the combination fails to explicitly teach wherein a first optical delay line which is continuously adjustable and a second optical delay line which is continuously adjustable are arranged respectively and symmetrically.
However, without showing criticality of the symmetrical nature, it would have been obvious, through routine experimentation, to position the delay structures in order to produce the best result for variable delay as well as device packaging (see MPEP 2144.05 II A).
Regarding claim 2, Allen as modified by Swanson, Aggarwal, and Yu teaches the system according to claim 1, wherein a length of each level of the N-level cascaded fixed optical delay line grows exponentially, while a delay amount of a next-level fixed optical delay line is greater than a delay amount of a previous-level fixed optical delay line; and/or the fixed delay amount of a first-level fixed optical delay line is less than or equal to a maximum adjustable delay amount of each of the first spiral continuously adjustable optical delay line and the second spiral continuously adjustable optical delay line (Allen, ¶64, a binary delay 50 with several integrated tunable switches 511, 512, 513, 514, and 515 where ‘L’ stands for a pre-defined unit delay. The upper ‘rail’ on the binary delay 50 have fibre optic, free space, or integrated photonic delay lines 52, 53, 54, and 55 of lengths L, 2L, 4L, and 8L respectively between each tunable switch 511, 512, 513, 514, and 515 that may have an order of magnitude of 2.sup.n which correspond to delays of 2.sup.n unit delays, where n is a positive integer).
Regarding claim 4, Allen as modified by Swanson, Aggarwal, and Yu teaches the system according to claim 1, wherein each optical switch of the N+1-level cascaded optical switches is a 2x2 type adiabatic directional coupler or a multimode interferometer (Allen, ¶70, The tunable switches 511, 512, 513, 514, and 515 are like individual two-way switches. Each MZI allows switching (selection, via the phase shift) to the bottom or top output of the MZI; ¶73, There may be a need to switch from one to many different outputs/delay lengths (a multiplexer). Multiplexers can be many cascaded MZIs that ‘fan-out’ to many optical paths or more complex N×N MZI structures (rather than a simple 2×2). Each of these (2×2 MZIs and N×N MZIs) will be controlled by a phase shift as described above; and see figures 3a-3c, different types of switches that can be used, including direction coupler, multimode interferometer, and Mach-Zehnder interferometer).
Regarding claim 5, Allen as modified by Swanson, Aggarwal, and Yu teaches the system according to claim 1, further comprising a control module, wherein the control module includes a thermo-optic driving circuit and an optical switch driving circuit, the control module adjusts a delay amount of the first spiral continuously adjustable optical delay line and the second spiral continuously adjustable optical delay line, and controls each of the N+1-level cascaded optical switches to adjust a total optical delay amount (Allen, ¶61, The temperature of the waveguide can be adjusted by an on-chip heater to lengthen or shorten the path length of the spiral waveguide 40, thereby increasing or decreasing the additional delay applied; and ¶70, The tunable switches 511, 512, 513, 514, and 515 are like individual two-way switches. Each MZI allows switching (selection, via the phase shift) to the bottom or top output of the MZI. By tuning the phase shift it is possible to switch from 100:0 or 0:100 (i.e. switch between the two outputs). They operate by heating the switches 511, 512, 513, 514, and 515 to change the signal path from the lower rail to the upper rail, wherein the default setting of the switches 511, 512, 513, 514, and 515 (i.e. when no heat is applied) is to transmit the signal along the lower rail, or vice versa. Alternatively, the tunable switches may also be operated by heating switches 511, 512, 513, 514, or 515 to change the signal path from its current rail to the other); after determining a target delay amount and selecting a plurality of optical switches to generate a delay most matching the target delay amount, together with the delay amount of the first optical delay line and the delay amount of the second optical delay line, a relative delay amount between the reference path and sample path is locked accurately to the target delay amount (Allen, ¶61, Switches 302 can connect to a controller 308 that can direct the switch state of each switch to select the desired path with its associated desired delay).
Regarding claim 6, Allen as modified by Swanson, Aggarwal, and Yu teaches the system according to claim 1, wherein the light source (Allen 10) is coupled to the optical chip (Allen 11) through an optical fiber via an edge coupler or a lens coupling mode (Allen, ¶34, FIG. 1 shows a broadband light source 10 that provides a photonic input signal to a photonic integrated circuit (PIC) module 11 via an optical port 14; and Aggarwal, ¶105, the photonic ports, e.g., input and output photonic ports, for the active photonic component can be optically coupled to a fiber array unit (FAU)… the FAU can also be coupled to the photonic port through an edge coupler).
Regarding claim 8, Allen as modified by Swanson, Aggarwal, and Yu teaches the system according to claim 1, further comprising a scanning element (Allen 12), wherein the scanning element (Allen 12) includes a two-dimensional rotating mirror (Allen, ¶34, The imaging optics 12 comprise a scanning unit containing two independent mirrors rotatable about perpendicular axes); the scanning element (Allen 12) guides the sample path signal light emitted from the optical chip (Allen 11) and transmitted through the interferometer (Allen 20) to the sample to be scanned by the two-dimensional rotating mirror, so as to generate a plurality of reflection signals at a plurality of different positions of the sample to be scanned, and completing extracting an information on a specific depth level of the sample to be scanned (Allen, see ¶¶35-36; and see ¶¶2-8 regarding scanning for depth).
Regarding claim 9, Allen as modified by Swanson, Aggarwal, and Yu teaches the system according to claim 1, wherein the light source (Allen 10) is a low coherence broadband light source; and/or the interferometer is a Michelson interferometer (Allen, ¶2, Optical coherence tomography (OCT) scanning is an imaging technique using low-coherent light to capture two- and three-dimensional images from within a media; and ¶15, The means for providing the first signal is preferably a broadband light source).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Allen et al. (USPGPub 20230414103 A1) in view of Swanson (USPGPub 20210356249 A1), Aggarwal et al. (USPGPub 20250216632 A1) and Yu et al. (USPGPub 20250362533 A1) as applied to claim 1 above, and further in view of Nakamura (USPGPub 20210018312 A1).
Regarding claim 3, Allen as modified by Swanson, Aggarwal, and Yu teaches the first output port and the second output port of the optical chip (Allen, see figure 2, optical port 14 (i.e. optical input port) having coupler 17 (i.e. splitter), two unlabeled output paths that include both a reference and sample path, the paths being arranged respectively and symmetrically, two output ports via waveguides 15 and 23). However, the combination fails to explicitly teach wherein the output ports of the optical chip are coupled through a bi-channel optical fiber array, and the sample path signal light output from the second output port is collimated by an optical fiber collimator.
However, Nakamura teaches wherein the output ports of the optical chip are coupled through a bi-channel optical fiber array, and the sample path signal light output from the second output port is collimated by an optical fiber collimator (¶36, connection lines between blocks in the drawings include both bidirectional and unidirectional. The one-way arrow schematically shows the flow of a main signal (data), and it does not exclude bidirectionality; and ¶44, The object light passes through a fiber collimator 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Aggarwal, and Yu to incorporate the teachings of Nakamura to further include bi-channel optical fibers as they allow data to be transmitted and received in both directions simultaneously over a single fiber, thereby decreasing the hardware needs. Additionally, it would have been obvious to further include a collimator in the sample path in order to prevent the scattering of measurement light in all directions, thereby allowing for a strong signal to be reflected from the sample and transmitted to the detector.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Allen et al. (USPGPub 20230414103 A1) in view of Swanson (USPGPub 20210356249 A1), Flanders (USPGPub 20120170046 A1), Nakamura (USPGPub 20210018312 A1), Everett et al. (USPGPub 20240081638 A1), Aggarwal et al. (USPGPub 20250216632 A1), and Yu et al. (USPGPub 20250362533 A1).
Regarding claim 10, Allen teaches a time domain coherence tomography method based on a photonic integrated chip (11) (abstract, An apparatus for optical coherence tomography (OCT) scanning is described; and ¶1, The invention seeks to implement an OCT scanner using photonic integrated circuit technology), comprising: emitting a detection light by a low-coherence broadband light source (10) (¶2, Optical coherence tomography (OCT) scanning is an imaging technique using low-coherent light to capture two- and three-dimensional images from within a media; and ¶39, the broadband light source 10 provides a photonic input signal to the module 11); dividing a detection light into a reference path signal light and a sample path signal light by an optical chip (11) (¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively), and transmitting the reference path signal light through a first spiral continuously adjustable optical delay line (18) and the sample path signal to an interferometer (20) respectively (¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively; see figure 2, broadband light source 10, photonic integrated circuit 11, spectrometer 20 (i.e. interferometer), processor 21, and variable delay 18; see figure 4; ¶75, In some embodiments, a combined version of the binary delay 50 and the tunable spiral waveguide with at least one phase shifter configurations could also be implemented in the variable delay 18; and see ¶¶45-48 for further details); transmitting the reference path signal light to generate a reference signal by the interferometer (20), then transmitting the reference signal to a photoelectric detection assembly; and transmitting the sample path signal light to a sample to be scanned to generate a reflection signal, then transmitting the reflection signal to the photoelectric detection assembly (¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20; and see ¶39 for further details); receiving the reference signal and the reflection signal by the photoelectric detection assembly, and generating an electrical signal after an interference between the reference signal and the reflection signal (¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20. The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum); receiving the electrical signal and transmits the electrical signal to an image calculation hardware (21) (¶40, The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum… The spectral content is delivered to output image processor 21); processing the electrical signal to obtain an image of the sample to be scanned by the image calculation hardware (¶40, The spectral content is delivered to output image processor 21 to produce an image, which can be displayed on a display of the image processor 21 or can be analysed by that processor or can be stored and sent for remote viewing); wherein the optical chip includes an optical input port (14), a light splitter (17), a reference path, a sample path, a first output port, and a second output port (see figure 2, optical port 14 (i.e. optical input port) having coupler 17 (i.e. splitter), two unlabeled output paths that include both a reference and sample path, the paths being arranged respectively and symmetrically, two output ports via waveguides 15 and 23); after having been input by the optical input port (14), the detection light is divided into the reference path signal light and the sample path signal light by the light splitter (17), while the first output port outputs the reference path signal light, and the second output port outputs the sample path signal light (see figure 2; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); the optical delay line (18) is of a spiral structure (see figure 4; and ¶75, In some embodiments, a combined version of the binary delay 50 and the tunable spiral waveguide with at least one phase shifter configurations could also be implemented in the variable delay 18); and/or the reference path of the optical chip further has a cascaded delay link arranged, the cascaded delay link is formed by an N+1-level cascaded optical switch and an N-level cascaded optical delay line, while an optical delay amount of each level of the optical delay line is fixed but different; wherein N is a positive integer (see figure 5; and ¶64, a binary delay 50 with several integrated tunable switches 511, 512, 513, 514, and 515 where ‘L’ stands for a pre-defined unit delay. The upper ‘rail’ on the binary delay 50 have fibre optic, free space, or integrated photonic delay lines 52, 53, 54, and 55 of lengths L, 2L, 4L, and 8L respectively between each tunable switch 511, 512, 513, 514, and 515 that may have an order of magnitude of 2.sup.n which correspond to delays of 2.sup.n unit delays, where n is a positive integer); the reference path signal light passes through the first optical delay line and passes through the cascaded delay link, and being output by the first output port (¶64, The combination of the two rails results in a reprogrammable path length, wherein a desired delay to the reference signal can be implemented; and ¶75, In some embodiments, a combined version of the binary delay 50 and the tunable spiral waveguide with at least one phase shifter configurations could also be implemented in the variable delay 18); the sample path signal light being output by the second output port directly (¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); after determining a delay matching most with a desired delay amount, through the first optical delay line and sample path at a front end, a relative delay amount of the two paths is accurately locked to a target value (¶65, In operation, the multiple of L is calculated for a desired delay, and the tunable switches are configured so that the signal travels a path length matching the desired delay). However, Allen fails to explicitly teach wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively; the photoelectric detection assembly including a photoelectric detector and a transimpedance amplifier; an analog-to-digital acquisition circuitry including a timing synchronization analog-to-digital circuit; the image calculation hardware including an FPGA and an image reconstruction host; wherein the input and output ports are formed by respective edge couplers; wherein a first optical delay line continuously adjustable and a second optical delay line continuously adjustable are arranged respectively and symmetrically; and the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Swanson teaches wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively (¶21, This type of variable delay may be placed in the sample arm, the reference arm, or both the sample arm and the reference arm); and an analog-to-digital acquisition circuitry including a timing synchronization analog-to-digital circuit (¶32, Light from the swept laser 102 is directed to the sample 105 and light reflected from the sample 105 is directed back to the receiver section containing components, such as one or more polarization beam splitters 109, 180-degree optical hybrids 110, photodetectors 111, transimpedance amplifiers 112, and analog to digital converters 113; and ¶34, SS-OCT imaging system 100 can include a k-clock module 115 to help ensure that the sample from an analog to digital converter (ADC) 113 approximately equals frequency increments and/or repeatable frequencies as is known in the prior art).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Allen to incorporate the teachings of Swanson to further include an ADC as these transform analog signals (like light) into digital data that computers, microcontrollers, and processors can process, store, and/or transmit, as well as decreasing signal degradation that could lead to noise. Additionally, it would have been obvious to include a variable delay line in both the reference and sample paths as this is a common configuration in the technology (according to the prior art) and because [t]his VDL provides the variable delay between the two arms of the interferometer that is necessary to match their path lengths as required by the system (Swanson, ¶21). However, the combination fails to explicitly teach the photoelectric detection assembly including a photoelectric detector and a transimpedance amplifier; the image calculation hardware including an FPGA and an image reconstruction host; wherein the input and output ports are formed by respective edge couplers; wherein a first optical delay line continuously adjustable and a second optical delay line continuously adjustable are arranged respectively and symmetrically; and the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Flanders teaches the photoelectric detection assembly including a detector (348) and a transimpedance amplifier (350) (¶39, The two detectors 348 along with the transimpedance amplifier 350 are integrated together on a common optical bench 110 . This bench 110 is further installed within an optoelectronic package 200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen and Swanson to incorporate the teachings of Flanders to further include a detector with a transimpedance amplifier because [t]he integration of the detectors 348 on a common optical bench 110 along with the transimpedance amplifier 350 improves the electronic performance of the system (Flanders, ¶40). However, the combination fails to explicitly teach wherein the detector comprises a photoelectric detector; the image calculation hardware including an FPGA and an image reconstruction host; wherein the input and output ports are formed by respective edge couplers; wherein a first optical delay line continuously adjustable and a second optical delay line continuously adjustable are arranged respectively and symmetrically; and the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Nakamura teaches wherein the detector comprises a photoelectric detector (abstract, The photoelectric conversion measuring means obtains interference light intensity measurement values by causing object light scattered from the object to be measured and the reference light to interfere with each other and to be guided to a light receiver).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, and Flanders to incorporate the teachings of Nakamura to have the detectors be photoelectric detectors as these are very common in the art. However, the combination fails to explicitly teach the image calculation hardware including an FPGA and an image reconstruction host; wherein the input and output ports are formed by respective edge couplers; wherein a first optical delay line continuously adjustable and a second optical delay line continuously adjustable are arranged respectively and symmetrically; and the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Everett teaches the image calculation hardware including an FPGA and an image reconstruction host (¶58, The processor (computing device) Cmp1 may include, for example, a field-programmable gate array (FPGA), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a graphics processing unit (GPU), a system on chip (SoC), a central processing unit (CPU), a general purpose graphics processing unit (GPGPU), or a combination thereof, that may performs some, or the entire, processing steps in a serial and/or parallelized fashion with one or more host processors and/or one or more external computing devices; and ¶133, Such a system can then include not only passive and active optical components, but also electronic integrated circuits for driving light sources, signal conditioning, analog to digital conversion, signal processing (e.g. image reconstruction), data transfer and data storage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, and Nakamura to incorporate the teachings of Everett for the image processor to include an FPGA as they are a common type of integrated circuit that can perform parallel processing, minimal response delays, and is reconfigurable. Additionally, it would have been obvious to reconstruct the image for the received data in order to have a functioning imaging device. However, the combination fails to explicitly teach wherein the input and output ports are formed by respective edge couplers; wherein a first optical delay line continuously adjustable and a second optical delay line continuously adjustable are arranged respectively and symmetrically; and the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Aggarwal teaches wherein the input and output ports are formed by respective edge couplers (¶105, the photonic ports, e.g., input and output photonic ports, for the active photonic component can be optically coupled to a fiber array unit (FAU)… the FAU can also be coupled to the photonic port through an edge coupler).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, Nakamura, and Everett to incorporate the teachings of Aggarwal to further include an edge coupler in order to efficiently couple light from an external source into a photonic chip and vice versa. However, the combination fails to explicitly teach wherein a first optical delay line continuously adjustable and a second optical delay line continuously adjustable are arranged respectively and symmetrically; and the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Yu teaches the optical chip includes a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode (¶29, one or more silicon photonic circuits 150 are provided on a layer of buried oxide (BOX) 203 disposed over a manufacturing substrate 201. Manufacturing substrate 201 can be a silicon wafer; ¶22, Silicon photonic circuit 150 can further include one or more optical structures, such as first and second waveguides 115a and 115b… First and second waveguides 115a and 115b can include elongated sections of a suitable material, such as silicon or silicon nitride; and ¶23, Silicon photonic circuit 150 may further include at least one electrode… one or more electrodes 117a-117d include stacked layers of conducting (such as metal), semi-conducting, and insulating materials).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, Nakamura, Everett, and Aggarwal to incorporate the teachings of Yu to include a silicon on insulator device as these devices are common in photonics. However, the combination fails to explicitly teach wherein a first optical delay line continuously adjustable and a second optical delay line continuously adjustable are arranged respectively and symmetrically.
However, without showing criticality of the symmetrical nature, it would have been obvious, through routine experimentation, to position the delay structures in order to produce the best result for variable delay as well as device packaging (see MPEP 2144.05 II A).
Allowable Subject Matter
Claim 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art of record individually or combined fails to teach the system according to claim 1 as claimed, wherein the photoelectric detection assembly is arranged between the interferometer and the analog-to-digital acquisition circuitry; the photoelectric detection assembly includes a photoelectric detector and a transimpedance amplifier; the photoelectric detector receives a signal of the reference path signal light having been transmitted through the interferometer as the reference signal, and receives an echo signal generated by the sample to be scanned as the reflection signal; and more specifically in combination with generates a current signal after an interference between the reference signal and the reflection signal, and transmits the current signal to the transimpedance amplifier; the transimpedance amplifier generates a voltage signal correspondingly according to the current signal, and transmits the voltage signal to the analog-to-digital acquisition circuitry.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIN R GARBER whose telephone number is (571)272-4663. The examiner can normally be reached M-F 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Y Epps can be reached at (571) 272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIN R GARBER/Examiner, Art Unit 2878
