DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 02/14/2025 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 02/14/2025 & 09/30/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6 & 11-12 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Fang et al (US20110032766).
Regarding claim 1, Fang discloses a method for operating a memory apparatus(FIG 5 & 9G; [0045] ), comprising: providing a semiconductor device(FIG 5 & 9; 300), wherein the semiconductor device comprises a substrate(966/301), a deep N-well region disposed in the substrate(931/304), a P-well region disposed in the deep N-well region(922/302), and a plurality of transistor structures disposed in the P-well region(966s on PW/ 320 and 310 in 302); wherein each of the plurality of transistor structures comprises a gate(965 and 966/ 307 and 306), as well as a source and a drain disposed on two sides of the gate respectively(FIG 5 & 9; [0065] disclose s/d not shown in figure / 322 314 and 312 311); and applying a first voltage to a port of the gate(FIG 5-7 & 9; [0045-0047] discloses applying voltage e.g., 320/gate 433 e.g.,. when it is not selected) , applying a second voltage to a port of the deep N-well region (FIG 5-6; [0048] discloses applying a second voltage to DNW 931/454), and applying a third voltage to a port of the P-well region(voltage on 310/966); wherein when a first operation is performed, the first voltage is equal to 0(When 320/966 is not selected 0V), the second voltage is a positive voltage(DNW 454/931 ground potential during normal operations), and the third voltage is a negative voltage(FIG 5-7; [0045] discloses 310/966 threshold voltage is negative when the tunneling transistor decoupled from bit line); when a second operation is performed, the first voltage is a positive voltage(When 320/966 is selected e.g., on), the second voltage is a positive voltage(DNW 931/454 grounded), and the third voltage is a positive voltage(310 is selected/ 432 CG1/ 966).
Regarding claim 6, Fang discloses a memory apparatus FIG 5 & 9G; [0045] ), comprising: a semiconductor device; wherein the semiconductor device comprises a substrate(966/301), a deep N-well region disposed in the substrate(931/304), a P-well region disposed in the deep N-well region(922/302), and a plurality of transistor structures disposed in the P-well region(966s on PW/ 320 and 310 in 302); wherein each of the plurality of transistor structures comprises a gate(965 and 966/ 307 and 306), as well as a source and a drain disposed on two sides of the gate respectively(FIG 5 & 9; [0065] disclose s/d not shown in figure / 322 314 and 312 311); and a voltage module(BL, WL, COM, CG, DNW and PW, configured to apply a first voltage to a port of the gate e(FIG 5-7 & 9; [0045-0047] discloses applying voltage e.g., 320/gate 433 e.g,. when it is not selected), apply a second voltage to a port of the deep N-well region (FIG 5-6; [0048] discloses applying a second voltage to DNW 931/454), and apply a third voltage to a port of the P-well region(voltage on 310/966); wherein when a first operation is performed, the first voltage is equal to 0(When 320/966 is not selected) 0V), the second voltage is a positive voltage(DNW 454/931 ground potential during normal operations), and the third voltage is a negative voltage(FIG 5-7; [0045] discloses 310/966 threshold voltage is negative when the tunneling transistor decoupled from bit line); when a second operation is performed, the first voltage is a positive voltage(When 320/966 is selected e.g., on), the second voltage is a positive voltage(DNW 931/454 grounded), and the third voltage is a positive voltage(310 is selected/ 432 CG1/ 966).
Regarding claim 11, Fang discloses an electronic device (FIG 5; 300) comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor. to cause the at least one processor to execute the method according to claim 1 (FIG 5; 300 [0066] processor).
Regarding claim 12, Fang discloses a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are executed by a computer to cause the computer to perform the method according to claim 1 ((FIG 5; 300 [0066] computer system).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5, 7-8 & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang et al.
Regarding claim 2, Fang discloses further comprising: when a third operation is performed, the first voltage is equal to 0(FIG 5, 7 & 9; When 320/966 is not selected 0V), the second voltage is a positive voltage (DNW 454/931 ground potential during normal operations).
However, Fang does not teach the third voltage is a positive voltage. However, it is obvious to one ordinary skill in the art to establish, and understand that Fang teaches a range voltages levels from positive to negative, and was held to be an obvious matter of choice of range.
Regarding claim 3, Fang discloses further comprising wherein the second operation is a forming operation (FIG 5-7 & 9; [0064] discloses forming operation), and the third operation is a reset operation (FIG 5-7; erase operation e.g., reset).
Regarding claim 5, Fang discloses wherein when the first operation is performed, the third voltage is greater than or equal to -1 V and less than 0 V(FIG 5-7; [0045] discloses 310/966 threshold voltage is negative when the tunneling transistor decoupled from bit line); and when the second operation or the third operation is performed, the third voltage is greater than 0 V and less than or equal to 1 V (FIG 7; voltage ranges so that it is obvious to one ordinary skill in the art to establish, and understand that Fang teaches a range voltages levels from positive to negative, and was held to be an obvious matter of choice of range).
Regarding claim 7, Fang discloses wherein when a third operation is performed, the first voltage is equal to 0(FIG 5, 7 & 9; When 320/966 is not selected 0V), the second voltage is a positive voltage (DNW 454/931 ground potential during normal operations).
However, Fang does not teach the third voltage is a positive voltage. However, it is obvious to one ordinary skill in the art to establish, and understand that Fang teaches a range voltages levels from positive to negative, and was held to be an obvious matter of choice of range.
Regarding claim 8, Fang discloses wherein the second operation is a forming operation (FIG 5-7 & 9; [0064] discloses forming operation), and the third operation is a reset operation (FIG 5-7; erase operation e.g., reset).
Regarding claim 10, Fang discloses wherein when the first operation is performed, the third voltage is greater than or equal to -1 V and less than 0 V(FIG 5-7; [0045] discloses 310/966 threshold voltage is negative when the tunneling transistor decoupled from bit line); and when the second operation or the third operation is performed, the third voltage is greater than 0 V and less than or equal to 1 V (FIG 7; voltage ranges so that it is obvious to one ordinary skill in the art to establish, and understand that Fang teaches a range voltages levels from positive to negative, and was held to be an obvious matter of choice of range).
Claim(s) 4 & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang et al in view of Chang et al (US20220336018).
Regarding claim 4, Fang discloses wherein the semiconductor device further comprises; the step of applying the first voltage to the port of the gate comprises (FIG 5-7 & 9): applying the first voltage to the port of the gate through the word line( WL1 programming voltage e.g.,0V); the method further comprises: applying a fourth voltage to the drain through the bit line(FIG 7; BL1 during reading); wherein the fourth voltage is a positive voltage(BL during reading is positive); and grounding the source through the source line (COM signal during reading 0V).
However, Fang does not disclose a resistive unit, a first end of the resistive unit being connected to the drain through a first connecting layer; a bit line connected to a second end of the resistive unit; a source line connected to the source through a second connecting layer; and a word line connected to the gate
in the same field of endeavor, Chang discloses a resistive unit (FIG 6; [0017 & 0061] discloses MCN 610 resistive unit), a first end of the resistive unit being connected to the drain through a first connecting layer (612); a bit line connected to a second end of the resistive unit (618 Vss); a source line connected to the source through a second connecting layer (614); and a word line connected to the gate (616).
Fang and Chang are analogous art because they are all directed to a semiconductor device with deep n-well substrate, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Fang to include Chang because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Chang in the teachings of Fang for the benefits reducing a leakage in the deep n-well and respective drain port. ([0016] Chang)
Regarding claim 9, Fang discloses wherein the semiconductor device further comprises; the step of applying the first voltage to the port of the gate comprises (FIG 5-7 & 9): applying the first voltage to the port of the gate through the word line( WL1 programming voltage e.g.,0V); the method further comprises: applying a fourth voltage to the drain through the bit line(FIG 7; BL1 during reading); wherein the fourth voltage is a positive voltage(BL during reading is positive); and grounding the source through the source line (COM signal during reading 0V).
However, Fang does not disclose a resistive unit, a first end of the resistive unit being connected to the drain through a first connecting layer; a bit line connected to a second end of the resistive unit; a source line connected to the source through a second connecting layer; and a word line connected to the gate
in the same field of endeavor, Chang discloses a resistive unit (FIG 6; [0017 & 0061] discloses MCN 610 resistive unit), a first end of the resistive unit being connected to the drain through a first connecting layer (612); a bit line connected to a second end of the resistive unit (618 Vss); a source line connected to the source through a second connecting layer (614); and a word line connected to the gate (616).
Fang and Chang are analogous art because they are all directed to a semiconductor device with deep n-well substrate, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Fang to include Chang because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Chang in the teachings of Fang for the benefits reducing a leakage in the deep n-well and respective drain port. ([0016] Chang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Liu et al (US20110233673 FIG 3; discloses memory device having p-type substrate 12, two gate structures 40 disposed on 12, n-well 20 on 12, source and drains and isolation region in 20 e.g., 16).
Cai et al (US20120099381 FIG 7-8; discloses memory device applying negative to positive voltages into the memory device).
Roizin et al (US20080135904 FIG 1; discloses controller 160, applying voltages on gate, deep well, source and bit lines of memory device 100).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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