DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 7, 12, and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-11, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee at al. (KR 20180003971A, with reference made to provided machine translation, Lee).
As per claim 1, Lee teaches (in figures 6-7) an array substrate, comprising a plurality of gate lines (GL) and a plurality of data lines (DL) disposed on a base substrate (410), wherein the plurality of gate lines are extended along a first direction (x direction, horizontal direction in figures) and are sequentially arranged in a second direction (y direction vertical direction in figures), the plurality of data lines are extended along the second direction and are sequentially arranged in the first direction, the plurality of gate lines and the plurality of data lines are intersected to define a plurality of sub- pixels, and at least one sub-pixel of the plurality of sub-pixels at least comprises a thin film transistor (t formed of gate electrode GE, drain electrode D and source electrode SE), a pixel electrode (450) and a common electrode (440), the first direction is intersected with the second direction; the common electrode in at least one sub-pixel is connected with the common electrode in an adjacent sub-pixel in the second direction through a common connection portion (portion of 440 shown as R1 in the annotated figure below), the at least one sub-pixel further comprises a common shielding portion (portion of 440 shown as R2 in the annotated figure below) disposed between the sub-pixel and an adjacent sub-pixel in the first direction, the common connection portion comprises a protrusion portion (portion of 440 shown as R1 in the annotated figure below) towards the pixel electrode, the protrusion portion comprises a second edge (edge of 440 shown as R3 in the annotated figure below) towards the pixel electrode, a joint of the common shielding portion and the protrusion portion comprises a third edge (edge of 440 shown as R4 in the annotated figure below) close to the pixel electrode, the pixel electrode comprises a fourth edge (edge of 450 shown as R5 in the annotated figure below) close to the protrusion portion and a fifth edge (edge of 450 shown as R6 in the annotated figure below) close to the common shielding portion, the second edge and the fourth edge are parallel, and the third edge and the fifth edge are parallel (see figure 6).
As per claim 2, Lee teaches (in figures 6-7) an angle between the second edge (edge of 440 shown as R3 in the annotated figure above) and the third edge (edge of 440 shown as R4 in the annotated figure above) is an obtuse angle (see figure 6).
As per claim 3, Lee teaches (in figures 6-7) a common electrode line (plate portions of 431 which are formed below contact holes CNT3 and CNT2 and portions 431a and 431b) extending along the first direction, and the common electrode is connected with the common electrode line through a second via hole (CNT2).
As per claim 4, Lee teaches (in figures 6-7) an orthographic projection of the second via hole (CNT2) on the base substrate (410) overlaps with an orthographic projection of the protrusion portion (portion of 440 shown as R1 in the annotated figure above) on the base substrate.
As per claim 5, Lee teaches (in figures 6-7) a first via hole (CNT3), the pixel electrode (450) comprises a pixel connection portion (portion of 450 surrounding CNT3), the pixel connection portion is connected with a drain electrode (DE) of the thin film transistor through the first via hole, an orthographic projection of a connecting line (dashed line labeled as R7 in the annotated figures above and below) between two adjacent second via holes on the base substrate does not overlap with an orthographic projection of a center of the first via hole on the base substrate (see annotated figure below).
As per claim 6, Lee teaches (in figures 6-7) that orthographic projections of the first via hole (CNT3) and the second via hole (CNT2) on the base substrate (410) both overlap with an orthographic projection of the common electrode line (plate portions of 431 which are formed below contact holes CNT3 and CNT2 and portions 431a and 431b) on the base substrate (see figure 6).
As per claim 8, Lee teaches (in figures 6-7) that the common shielding portion (portion of 440 shown as R2 in the annotated figure above) of the at least one sub-pixel is connected with common base portions (portions of 440 shown as R8 in the annotated figure above) in a next row of sub-pixels through the common connection portion (portion of 440 shown as R1 in the annotated figure above connected to the portions of 440 shown as R8 in the annotated figure above through via hole CNT2 and second connection pattern 431c).
As per claim 9, Lee teaches (in figures 6-7) that an orthographic projection of the common shielding portion (portion of 440 shown as R2 in the annotated figure above) on the base substrate (410) at least partially overlaps with an orthographic projection of the plurality of data lines (DL) on the base substrate (see figure 6).
As per claim 10, Lee teaches (in figures 6-7) that at least one sub-pixel further comprises at least one shielding line (portion of 431 extending parallel to data lines DL), and a first end of the shielding line is connected with the common electrode line (plate portions of 431 which are formed below contact holes CNT3 and CNT2 and portions 431a and 431b), and a second end of the shielding line is extended in a direction away from the common electrode line.
As per claim 11, Lee teaches (in figures 6-7) that the shielding lines (portion of 431 extending parallel to data lines DL) of the plurality of sub-pixels, the plurality of gate lines (GL), and the common electrode lines (plate portions of 431 which are formed below contact holes CNT3 and CNT2 and portions 431a and 431b) of the plurality of sub-pixels are arranged in a same layer (pixel electrode and TFT layer of the first substrate).
As per claim 20, Lee teaches (in figures 2-7, see paragraph 65) a display apparatus, comprising a first substrate (410) and a second substrate (180) oppositely arranged, wherein the first substrate comprises the array substrate according to claim 1 (see rejection above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee at al. (KR 20180003971A, with reference made to provided machine translation, Lee).
As per claim 13, Lee teaches (in figures 6-7) all the limitations of claim 5 (as shown in the rejection above) and further teaches a first distance between an edge of the pixel connection portion (portion of 450 surrounding CNT3) at a side close to the common connection portion (portion of 440 shown as R1 in the annotated figure above connected to the portions of 440 shown as R8 in the annotated figure above through via hole CNT2 and second connection pattern 431c) and an edge of the common connection portion (portion of 440 shown as R1 in the annotated figure above connected to the portions of 440 shown as R8 in the annotated figure above through via hole CNT2 and second connection pattern 431c) at a side close to the pixel connection portion (portion of 450 surrounding CNT3), and the first distance is a dimension in the first direction.
Lee does not specifically teach that the first distance is between 20 µm and 50 µm.
However, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). The first distance is a result-effective variable (MPEP 2144.05(III)(C)) in that if the distance is too small, short circuiting is more likely to occur.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the first distance such that it is between 20µm and 50 µm in order to prevent short circuiting.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER P GROSS whose telephone number is (571)272-5660. The examiner can normally be reached Monday-Friday 9am-6pm EST.
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/ALEXANDER P GROSS/Primary Examiner, Art Unit 2871
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