DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claim filed on 05/12/2026. Claim 13 has been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202411797625.5, filed on 12/06/2024.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully and carefully considered, with the Examiner’s response set for the below.
(1)In view of the amendments, claim objections directed to claim 13 have been withdrawn.
(2) Applicant contends that, regarding claim 1, “there is no shown disclosure or suggestion in Liao of ‘determine, based on the read window, and erase/program (E/P) cycle status of the one or more memory pages’. Particularly, “First, Liao is silent with respect to ‘determining E/P cycle status’ ‘based on the read window’, as recited in claim 1. FIG. 3 of Liao merely suggests that ‘as time passes and the number of PEC increases, each die behaves differently, and the RWB index may reflect the degradation in the respective dies.’ (See Liao, [0047]) While there is generally a relation between program-erase cycle (PEC) and RWB index, Liao does not use RWB index to determine PEC. In fact, Liao discloses ‘a counter (e.g., a PEC counter), which may be incremented every time a program-erase operation is performed’. (See Liao, [0038]) In other words, Liao keeps track of PEC using a counter. Therefore there is no need in Liao to determine PEC based on other metrics (e.g., RWB index)”. The Examiner respectfully disagrees.
Lien disclose that the invention is directed to “adapting the bitline voltage and sensing time for read operations using an estimation of the degradation of a portion of memory” ([0012]). Lien further teaches that “One estimation of the level of degradation over the lifetime of a memory device can be measured in program erase cycles” ([0012]). In addition, Lien teaches a look-up table that maps RWB, sense time, and program erase cycle values for each wordline ([0036]) and states that “In some embodiments, adaptive bitline voltage component 113 updates the look-up table based on estimated or actual RWB degradation” ([0039]), which indicates that program erase cycle values can be updated based on actual RWB values.
A person of ordinary skill in the art would have recognized that program erase cycle values and RWB exhibit an inversely proportional relationship as illustrated in Figure 3 of Liao. Accordingly, a function can be derived from the plot/relationship shown in Figure 3, enabling determination of a program erase cycle value from an RWB value, or vice versa. Lien provides the motivation and need to determine program erase cycle values from RWB while Liao discloses a technique that can be used to achieve that objective. Therefore, it would have been obvious to use Liao’s direct mapping between program erase cycle values and RWB in the system of Lien to determine program erase cycle values based on RWB for purposes of adapting bitline voltage and sensing time.
(3) Applicant contends, that regarding claim 1, “Second, the RWB index of Liao is "updated when a program-erase cycle (PEC) is performed". That is, PEC is a trigger to update RWB index. RWB index is used in Liao as a basis to "dynamically modifies one or more device parameters of the memory device 130. For example, the memory access management component 113 may reduce a voltage for performing the memory access operation (e.g., a program operation or an erase operation) on one or more memory dies, thereby slowing degradation of the dies." (See Liao, [0038]) In contrast, the "read window" of claim 1 is used as a basis to determine erase/program cycle status”. The Examiner respectfully disagrees.
As set forth above, Lien teaches a look-up table that maps RWB, sense time, and program erase cycle values for each wordline ([0036]) and states that “In some embodiments, adaptive bitline voltage component 113 updates the look-up table based on estimated or actual RWB degradation” [0039]), which indicates that program erase cycle values can be updated based on actual RWB values. Liao disclose a technique in Figure 3 that enables a person of ordinary skill in the art to determine a program erase cycle value from an RWB value, or vice versa. Therefore, it would have been obvious to use Liao’s direct mapping between program erase cycle values and RWB in the system of Lien to determine program erase cycle values based on RWB for purposes of adapting bitline voltage and sensing time.
(4) Applicant contends, that regarding claim 1, “Third, Liao is silent with respect to "determining E/P cycle status of the one or more memory pages" as recited in claim 1. In fact, Liao discloses "monitoring the health index of a memory device at a die-level", where "the memory sub-system monitors a read window budget (RWB) index reflecting a RWB of every die in the memory device, and updates the individual RWB index when a program-erase cycle (PEC) is performed on the individual dies." (See Liao, [0017].) As further disclosed in Liao, "a non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. Planes can be grouped into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. A "block" herein shall refer to a set of contiguous or non- contiguous memory pages." (See Liao, [0012]) In other words, Liao manages RWB index and PEC on a die-level, which is a much coarser level of control compared to memory page-level management. In comparison, claim 1 recites "obtaining a read window corresponding to the one or more memory pages; and determining, based on the read window, an erase/program (E/P) cycle status of the one or more memory pages", which is not disclosed in Liao or other cited references”. The Examiner respectfully disagrees.
Lien teaches “the read operation sensing time is an amount of time threshold voltages are applied during a read operation in order for the memory subsystem to determine the value stored in one or more memory cells along a wordline”, ([0034]). The “one or more memory cells alone a wordline” are considered page(s). In SLC mode, a wordline corresponds to a page as the wordline is the physical entity, while the page is the logical abstraction of that physical storage location. Furthermore, Lien discloses a look-up table that maps each wordline to sensing time, bitline voltage values, and program erase cycle counts ([0036]). Accordingly, Lien teaches tracking and determining these metric values at the page level.
Therefore, Lien in view of Liao teaches each and every limitation recited in claim1. Similar arguments apply to claims 9 and 17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al (US2024/0053901), hereinafter Lien in view of Liao et al. (US2024/0347127), hereinafter Liao.
Regarding claims 1 and 17, taking claim 1 as exemplary Lien teaches a memory system, comprising:
a memory device (Lien, [0020], non-volatile memory devices (e.g., memory device 130) include negative-and (NAND) type flash memory; Fig.1, memory device 130) comprising one or more memory pages (Note – pages are storage units in a flash memory); and
a memory controller (Lien, Fig.1, memory subsystem controller 115) coupled to the memory device, wherein the memory controller is configured to perform operations comprising:
obtaining a read window corresponding to the one or more memory pages (Lien, [0011], read window bandwidth (RWB); [0039], Adaptive bitline voltage component 113 estimates RWB for each of the wordlines); and
determining, based on the read window, an erase/program (E/P) cycle status of the one or more memory pages (Lien, [0034]; [0036], the look-up table maps wordlines with lower RWB to higher sensing times. In such an embodiment, for each of the wordlines in the look-up table, a larger number of program erase cycles is mapped to a smaller bitline voltage value; [0037], the look-up table maps wordlines with lower RWB to smaller bitline voltages. In such an embodiment, for each of the wordlines in the look-up table, a larger number of program erase cycles is mapped to a smaller bitline voltage value).
Lien teaches determining erase/program cycle of one or more memory pages, nevertheless, Lien does not explicitly teach determining, based on the read window, an erase/program (E/P) cycle status of the one or more memory pages, as claimed.
However, Lien in view of Liao teaches a memory device (Lien, [0013], one or more non-volatile memory devices (e.g., memory device 130)) comprising one or more memory pages (Liao, [0012], For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. A “block” herein shall refer to a set of contiguous or non-contiguous memory pages);
determining, based on the read window, an erase/program (E/P) cycle status of the one or more memory pages (Liao, [0017], read window budget (RWB) index; Fig.3, see PEC may be determined based on RWB index).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lien to incorporate teachings of Liao to determine program/erase count based on read window value. As such, accurate sensing times and voltages can be determined for word lines and/or bitlines. A person of ordinary skill in the art would have been motived to combine the teachings Lien with Liao because it improves efficiency of the storage system disclosed in Lien by providing a mapping between read window and program/erase count for quick look-up.
Claim 17 has similar limitations as claim 1 and is rejected for the similar reasons.
Regarding claims 3 and 19, taking claim 3 as exemplary, the combination of Lien teaches all the features with respect to claim 1 as outlined above. The combination of Lien further teaches the memory system of claim 1, wherein the E/P cycle status is determined based on a pre-determined relation between an E/P cycle and the read window, wherein the read window decreases with an increase of the E/P cycle (Lien, [0036], a larger number of program erase cycles is mapped to a smaller bitline voltage value; [0037], the look-up table maps wordlines with lower RWB to smaller bitline voltages; Note – a larger number of P/E cycle therefore maps lower RWB; Liao, Fig.3, see large PEC maps to small RWB index).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lien to incorporate teachings of Liao to determine program/erase count based on read window value. As such, accurate sensing times and voltages can be determined for word lines and/or bitlines. A person of ordinary skill in the art would have been motived to combine the teachings Lien with Liao because it improves efficiency of the storage system disclosed in Lien by providing a mapping between read window and program/erase count for quick look-up.
Claim 19 has similar limitations as claim 3 and is rejected for the similar reasons.
Claim(s) 2 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien and Liao as applied to claims 1 and 17 respectively above, and further in view of Zhu et al. (US2025/0284402), hereinafter Zhu.
Regarding claims 2 and 18, taking claim 2 as exemplary, the combination of Lien teaches all the features with respect to claim 1 as outlined above. The combination of Lien does not explicitly teach the memory system of claim 1, wherein obtaining the read window comprises: sending one or more commands to obtain the read window to the memory device, wherein the one or more commands comprise an address of the one or more memory pages; and obtaining the read window based on one or more responses to the one or more commands from the memory device, as claimed.
However, the combination of Lien in view of Zhu teaches the memory system of claim 1, wherein obtaining the read window comprises: sending one or more commands to obtain the read window to the memory device (Zhu, Abstract, A memory system may receive a command from a host system requesting an RWB for an edge of a distribution of a logic level of a set of logic levels), wherein the one or more commands comprise an address of the one or more memory pages (Zhu, [0059], the host system 205 may issue commands indicating one or more LBAs and the memory system controller 215 may identify one or more physical block addresses indicated by the LBAs; [0065], the host system controller 406 of the host system 405 may be operable to transmit multiple commands to the memory system 410 (e.g., to the memory system controller 415) each requesting the memory system 410 to calculate or measure RWBs (e.g., read budgets) corresponding to edges of logic levels for the memory system 410); and obtaining the read window based on one or more responses to the one or more commands from the memory device (Zhu, [0060], [0065]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Zhu to include a command for requesting a read window budget for one or more memory pages. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Zhu because it improves communication of the storage system disclosed in the combination of Lien by allowing host to request RMB when needed.
Claim 18 has similar limitations as claim 2 and is rejected for the similar reasons.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien and Liao as applied to claim 3 above, and further in view of Kim et al. (US 2025/0199680), hereinafter Kim.
Regarding claim 4, the combination of Lien teaches all the features with respect to claim 3 as outlined above. The combination of Lien does not explicitly teach the memory system of claim 3, wherein the pre-determined relation is stored in a buffer of the memory controller, as claimed.
However, the combination of Lien in view of Kim teaches the memory system of claim 3, wherein the pre-determined relation is stored in a buffer of the memory controller (Kim, [0112], the controller 120 may load a mapping table stored in a memory 110 into a buffer memory 122 included in the controller 120; Lien, [0022], The memory subsystem controller 115 can include hardware … and/or discrete components, a buffer memory).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Kim to store management information such as mapping tables in a buffer included in a controller. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Kim because it improve performance of the storage system disclosed in the combination of Lien by storing frequently accessed mapping tables in a high performance storage medium.
Claim(s) 5 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien and Liao as applied to claims 3 and 17 respectively above, and further in view of You (US 2025/0364064, KR10-2024-0067895), hereinafter You and Kang et al. (US 2023/0081557), hereinafter Kang.
Regarding claims 5 and 20, taking claim 5 as exemplary, the combination of Lien teaches all the features with respect to claim 1 as outlined above. The combination of Lien does not explicitly teach the memory system of claim 1, wherein the E/P cycle status comprises a ratio of a quantity of undergone E/P cycles of a first memory block to an expected maximum quantity of E/P cycles of the first memory block, wherein the first memory block comprises the one or more memory pages, as claimed.
However, the combination of Lien in view of You and Kang teaches the memory system of claim 1, wherein the E/P cycle status comprises a ratio of a quantity of undergone E/P cycles of a first memory block to an expected maximum quantity of E/P cycles of the first memory block, wherein the first memory block comprises the one or more memory pages (You, [0095], a remaining read count (or remaining lifespan) of the memory block, which will be described later, may be predicted according to a degree to which the current threshold voltage distribution is influenced by the disturbance; Kang, [0064], the remaining lifetime code RLC stored in the mode register 130a may have … value (e.g., ‘0001’ through ‘1110’) between the first value and the second value representing a ratio (e.g., about 5% through about 90%) of the remaining lifetime to the maximum lifetime).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of You and Kang to use a ratio of a quantity of utilized P/E count of a memory block to a maximum P/E count to represent endurance/program erase cycle status of a memory block. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with You and Kang because it improves efficiency of the storage system disclosed in the combination of Lien by allowing different ways to represent endurance of memory blocks in a nonvolatile memory storage.
Claim 20 has similar limitations as claim 5 and is rejected for the similar reasons.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien, Liao, You, and Kang as applied to claim 5 above, and further in view of Kao et al. (US 2010/0100663), hereinafter Kao.
Regarding claim 6, the combination of Lien teaches all the features with respect to claim 5 as outlined above. The combination of Lien does not explicitly teach the memory system of claim 5, wherein the operations further comprise: in response to determining that the ratio is larger than a threshold, moving data from the first memory block to a second memory block, as claimed.
However, the combination of Lien in view of Kao teaches the memory system of claim 5, wherein the operations further comprise: in response to determining that the ratio is larger than a threshold, moving data from the first memory block to a second memory block (Kao, [0018]; claim 1, determining a stage according to a highest erase count; determining a wear leveling limit corresponding to the stage; and performing wear leveling according to the wear leveling limit; claim 4, The method of claim 3, wherein calculating the stage from the highest erase count according to the algorithm comprises calculating the stage according to a ratio of the highest erase count and a predetermined maximum erase count).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Kao to relocate data from a memory block whose ratio of P/E cycle count and a predetermined maximum count exceeds a threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Kao because it improves efficiency and reliability of the storage system disclosed in the combination of Lien by moving data to reliable memory blocks to avoid data loss.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien and Liao as applied to claim 1 above, and further in view of Petti et al. (US2026/0004846), hereinafter Petti.
Regarding claim 7, the combination of Lien teaches all the features with respect to claim 1 as outlined above. The combination of Lien does not explicitly teach the memory system of claim 1, wherein the memory controller is configured to perform the operations in response to detecting a failure in the memory device, as claimed.
However, the combination of Lien in view of Petti teaches the memory system of claim 1, wherein the memory controller is configured to perform the operations in response to detecting a failure in the memory device (Petti, [0095], A required read reliability set by a read bit error rate (BER) specification determines the read window margin requirements for a memory array of Threshold Selector Memory Cells 222a.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Petti to determine/adjust a read window margin based on bit error rate. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Petti because it improves efficiency and reliability of the storage system disclosed in the combination of Lien by determining appropriate voltage distribution in response to a bit error rate of a memory block exceeds a threshold.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien and Liao as applied to claim 1 above, and further in view of Xie et al. (US 2023/0063498), hereinafter Xie and Petti et al. (US2026/0004846), hereinafter Petti.
Regarding claim 8, the combination of Lien teaches all the features with respect to claim 1 as outlined above. The combination of Lien does not explicitly teach the memory system of claim 1, wherein the memory controller is configured to perform the operations in response to receiving, from a host, a request to obtain health information of the memory device, and wherein the operations further comprise sending the health information comprising the E/P cycle status to the host, as claimed.
However, the combination of Lien in view of Xie and Petti teaches the memory system of claim 1, wherein the memory controller is configured to perform the operations in response to receiving, from a host, a request to obtain health information of the memory device (Xie, [0061], the processing logic provides the amount of remaining device life to a host system. The processing logic can provide the amount of remaining drive life to the host system in response to a request for an indication of the amount of remaining device life; [0014], The operational lifetime of a memory sub-system system (or other unit of storage, such as a memory unit, storage device, or drive) can refer to a predicted number of program/erase cycles after which the memory sub-system does not provide a specified degree of storage reliability. Storage reliability can be specified in terms of an amount of time for which the memory sub-system can store data while maintaining an unrecoverable bit error rate below a threshold; [0043]; Petti, [0095]), and
wherein the operations further comprise sending the health information comprising the E/P cycle status to the host (Xie, [0014], The used device life can be represented as a percentage of the lifetime that has been used, and the remaining device life be represented as a percentage of the lifetime that has not been used.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Xie and Petti to request indication of device life, by a host, and determine/adjust read window margin when bit error rate is less than a threshold level. In response to the request from the host, used device life /remaining device life is provided to the host. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Xie and Petti because it improves efficiency and reliability of the storage system disclosed in the combination of Lien by determining appropriate voltage distribution in response to the bit error rate of a memory block exceeds a threshold.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al (US2024/0053901), hereinafter Lien in view of Liao et al. (US2024/0347127), hereinafter Liao, and further in view of Zhu et al. (US 2025/0284402), hereinafter Zhu.
Regarding claim 9, the claim has similar limitations as claim 1 and is rejected for the similar reasons. However, the combination of Lien does not explicitly teach send, through the interface to a memory device coupled to the memory controller, one or more commands to obtain a read window, as claimed.
However, the combination of Lien in view of Zhu teaches send, through the interface to a memory device coupled to the memory controller, one or more commands to obtain a read window (Zhu, Abstract, A memory system may receive a command from a host system requesting an RWB for an edge of a distribution of a logic level of a set of logic levels).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Zhu to include a command for requesting a read window budget for one or more memory pages. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Zhu because it improves communication of the storage system disclosed in the combination of Lien by allowing host to request RMB when needed.
Regarding claim 10, the claims has similar limitations as claim 2 and is rejected for the similar reasons.
Regarding claim 11, the claims has similar limitations as claim 3 and is rejected for the similar reasons.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien, Liao, and Zhu as applied to claim 4 above, and further in view of Kim et al. (US 2025/0199680), hereinafter Kim.
Regarding claim 12, the claims has similar limitations as claim 4 and is rejected for the similar reasons.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien, Liao, and Zhu as applied to claim 9 above, and further in view of You (US 2025/0364064, KR10-2024-0067895), hereinafter You and Kang et al. (US 2023/0081557), hereinafter Kang.
Regarding claim 13, the claims has similar limitations as claim 5 and is rejected for the similar reasons.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien, Liao, Zhu, You, and Kang as applied to claim 13 above, and further in view of Kao et al. (US 2010/0100663), hereinafter Kao.
Regarding claim 14, the claims has similar limitations as claim 6 and is rejected for the similar reasons.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien, Liao, and Zhu as applied to claim 9 above, and further in view of Petti et al. (US2026/0004846), hereinafter Petti.
Regarding claim 15, the combination of Lien teaches all the features with respect to claim 9 as outlined above. The combination of Lien does not explicitly teach the memory controller of claim 9, wherein the memory controller is configured to determine the E/P cycle status in response to detecting a failure in the memory device, as claimed.
However, the combination of Lien in view of Petti teaches the memory controller of claim 9, wherein the memory controller is configured to determine the E/P cycle status in response to detecting a failure in the memory device (Petti, [0095], A required read reliability set by a read bit error rate (BER) specification determines the read window margin requirements for a memory array of Threshold Selector Memory Cells 222a; Lien, [0034]-[0037]; Liao, Fig.3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Petti to determine/adjust read window margin based on bit error rate. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Petti because it improves efficiency and reliability of the storage system disclosed in the combination of Lien by determining appropriate voltage distribution in response to the bit error rate of a memory block exceeds a threshold.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lien, Liao, and Zhu as applied to claim 9 above, and further in view of Xie et al. (US 2023/0063498), hereinafter Xie and Petti et al. (US2026/0004846), hereinafter Petti.
Regarding claim 16, the combination of Lien teaches all the features with respect to claim 9 as outlined above. The combination of Lien does not explicitly teach the memory controller of claim 9, wherein the memory controller is configured to: determine the E/P cycle status in response to receiving, from a host, a request to obtain health information of the memory device; and send the health information comprising the E/P cycle status to the host, as claimed.
The combination of Lien in view of Xie and Petti teaches the memory controller of claim 9, wherein the memory controller is configured to: determine the E/P cycle status in response to receiving, from a host, a request to obtain health information of the memory device (Xie, [0061], the processing logic provides the amount of remaining device life to a host system. The processing logic can provide the amount of remaining drive life to the host system in response to a request for an indication of the amount of remaining device life; [0014], [0014], The operational lifetime of a memory sub-system system (or other unit of storage, such as a memory unit, storage device, or drive) can refer to a predicted number of program/erase cycles after which the memory sub-system does not provide a specified degree of storage reliability. Storage reliability can be specified in terms of an amount of time for which the memory sub-system can store data while maintaining an unrecoverable bit error rate below a threshold; [0043]; Petti, [0095]; Lien, [0034]-[0037]; Liao, Fig.3); and
send the health information comprising the E/P cycle status to the host (Xie, [0014], The used device life can be represented as a percentage of the lifetime that has been used, and the remaining device life be represented as a percentage of the lifetime that has not been used.)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lien to incorporate teachings of Xie and Petti to request indication of device life, by a host, and determine/adjust read window margin when bit error rate is less than a threshold level. In response to the request from the host, used device life/remaining device life is provided to the host. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Lien with Xie and Petti because it improves efficiency and reliability of the storage system disclosed in the combination of Lien by determining appropriate voltage distribution in response to the bit error rate of a memory block exceeds a threshold.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Patel (US 2025/0225071) teaches that a host obtains health information from a storage device, which includes device life information.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/ Primary Examiner, Art Unit 2137
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