Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 19 May 2026 for application number 19/023,759.
Claims 1 – 20 are presented for examination.
Response to Amendment
Applicant’s amendment filed 19 May 2026 is sufficient to overcome the rejection of claims 1 – 20 based upon the arguments.
Response to Arguments
Applicant’s arguments, filed 19 May 2026, with respect to the rejection(s) of claim(s) 1 – 20 under 35 USC § 103 have been fully considered and are persuasive based upon the arguments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Cariello, US Pub. No. 2023/0395117 A1.
Cariello, in combination with the prior art of record, reads on the claim limitation based on the current claim language. Please see the new grounds of rejection below.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05 June 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 9 – 11, 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. [hereafter as Jang], US Pub. No. 2023/0384957 A1 in view of Cariello [hereafter as Cariello], US Pub. No. 2023/0395117 A1.
As per claim 1, Jang discloses a memory system, comprising:
a memory device comprising a plurality of memory blocks [“a plurality of memory blocks,”] [para. 0005]; and
a memory controller coupled to the memory device [“The storage controller is configured to control data input and data output of the at least one nonvolatile memory device”] [Abstract], wherein the memory controller is configured to:
identify a first memory block of the plurality of memory blocks, wherein the first memory block comprises specific data that is invalid [“a normal purge operation may refer to physically erasing all invalid data stored in the storage device”] [para. 0026];
a priority of the first memory block among the plurality of memory blocks [“The storage controller 1210 may limit the number of RPMBs by managing garbage collection and log block allocation priorities for the RPMBs.”] [para. 0031]; and
perform garbage collection on the memory device of the plurality of memory blocks [“perform garbage collection for managing the number of RPMBs”] [para. 0038].
However, Jang does not explicitly disclose increase a priority level; and
perform garbage collection based on priority levels.
Cariello teaches increase a priority level [“For instance, the host system 105 may provide ranking information associated with garbage collection operations so that the memory system 110 can prioritize zones for other operations. To illustrate, if the ranking information from the host system 105 indicates that a zone has a high urgency for garbage collection, the memory system 110 may deprioritize that zone for refresh to avoid a superfluous refresh operation on the zone. Additionally or alternatively, the memory system 110 may provide ranking information associated with refresh operations so that the host system 105 can prioritize zones for garbage collection operations. To illustrate, if the ranking information from the memory system 110 indicates that a zone has a high urgency for refresh, the host system 105 may prioritize that zone for garbage collection to avoid a superfluous refresh operation on the zone.”] [para. 0045] [“… a validity information table 220 may be arranged so that the zones are ranked in order of garbage collection urgency based on the validity information (VI) tracked by that table. For instance, if a validity information table 220 is tracking the quantity of invalid data per zone, the validity information table 220 may list the zones in descending order of quantity of invalid data (e.g., zones associated with higher quantities of invalid data may be ranked higher than zones associated with lower quantities of invalid data).”] [para. 0055] [“…the garbage collection ranking table 225 may indicate zones in descending order of garbage collection urgency, where zones with higher garbage collection urgency are ranked higher than zones with lower garbage collection urgency … garbage collection ranking may be based on the quantity of invalid data ...”] [para. 0056]; and
perform garbage collection based on priority levels [“… a validity information table 220 may be arranged so that the zones are ranked in order of garbage collection urgency based on the validity information (VI) tracked by that table. For instance, if a validity information table 220 is tracking the quantity of invalid data per zone, the validity information table 220 may list the zones in descending order of quantity of invalid data (e.g., zones associated with higher quantities of invalid data may be ranked higher than zones associated with lower quantities of invalid data).”] [para. 0055] [“…the garbage collection ranking table 225 may indicate zones in descending order of garbage collection urgency, where zones with higher garbage collection urgency are ranked higher than zones with lower garbage collection urgency … garbage collection ranking may be based on the quantity of invalid data ...”] [para. 0056].
Jang and Cariello are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jang with Cariello in order to modify Jang for “increase a priority level; and
perform garbage collection based on priority levels” as taught by Cariello. One of ordinary skill in the art would be motivated to combine Jang with Cariello before the effective filing date of the claimed invention to improve a system by providing the ability to “improve maintenance operation management and avoid superfluous maintenance operations, among other advantages..” [Cariello, para. 061].
As per claim 2, Jang in view of Cariello discloses the memory system of claim 1, Jang discloses wherein the specific data comprises replay-protected-memory-block (RPMB) data [“The storage controller 1210 may limit the number of RPMBs by managing garbage collection and log block allocation priorities for the RPMBs.”] [para. 0031].
Claim 16 is rejected with like reasoning.
As per claim 3, Jang in view of Cariello discloses the memory system of claim 1, Jang discloses wherein the specific data becomes invalid when new data is written to a same logical address as the specific data [“Furthermore, the host 1100 may provide a purge command (hereinafter, for example, RPMB purge) for RPMB data invalidated through overwriting to the storage device 1200.”] [para. 0028] [“invalid RPMB data is logically erased”] [para. 0030].
Claim 17 is rejected with like reasoning.
As per claim 9, Jang in view of Cariello discloses the memory system of claim 1, Jang discloses wherein the memory controller is configured to:
perform a first garage collection operation on the first memory block by sending one or more commands to migrate valid data from the first memory block to a target memory block of the memory device [“In operation S240, the RPMB purge manager 1214 may perform garbage collection using the RPMB free block as a destination block for writing the collected valid RPMB data. When all valid RPMB data is moved to the destination block by garbage collection, the RPMB in which only invalid RPMB data remains is designated as the free block.”] [para. 0081].
Cariello teaches garage collection operation on the first memory block erase the first memory block [“To avoid waiting for all of the pages 175 in the block 170 to have invalid data in order to erase and reuse the block 170, an algorithm referred to as “garbage collection” may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations.”] [para. 0036].
Claim 19 is rejected with like reasoning.
Claim 10 is rejected with like reasoning as claims 1 and 9 above, except for the following remaining claim limitations:
a processor; and
a first interface configured to be coupled to a memory device,
wherein the first interface is configured to:
send one or more read commands to read valid data from a first memory block of the plurality of memory blocks.
Jang discloses a processor [“The processing unit 1211 may include a central processing unit or a micro-processor.”] [para. 0045]; and
a first interface configured to be coupled to a memory device [“Referring to FIG. 3, the storage controller 1210 of the present disclosure may include a processing unit 1211, a working memory 1213, a host interface 1215,”] [para. 0044],
wherein the first interface is configured to:
send one or more read commands to read valid data from a first memory block of the plurality of memory blocks [“the storage controller 1210 may write data to or read data stored in the nonvolatile memory device 1220 according to a request from the host 1100 (FIG. 1). In order to access the nonvolatile memory device 1220, the storage controller 1210 may provide a command, an address, data, and/or a control signal to the nonvolatile memory device 1220.”] [para. 0034] [para. 0050].
Claim 11 is rejected with like reasoning as claim 1 above.
Claim 20 is rejected with like reasoning as claim 1 above.
Claims 4, 8, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. [hereafter as Jang], US Pub. No. 2023/0384957 A1 in view of Cariello [hereafter as Cariello], US Pub. No. 2023/0395117 A1 as applied to claims 1 and 10, and further in view of Shatsky et al. [hereafter as Shatsky], US Pub. No. 2022/0414102 A1.
As per claim 4, Jang in view of Cariello discloses the memory system of claim 1, However, Jang and Cariello do not explicitly disclose wherein the memory controller is configured to:
identify the first memory block by checking an indication bit corresponding to the first memory block,
wherein the indication bit indicates whether the first memory block comprises the specific data that is invalid.
Shatsky teaches wherein the memory controller [“The storage control system …”] [Abstract] is configured to:
identify the first memory block by checking an indication bit corresponding to the first memory block [“The storage control system receives data items and assigns a respective unique data ID to each data item, … starting from the first data ID…”] [Abstract],
wherein the indication bit indicates whether the first memory block comprises the specific data that is invalid [“… a respective bit whose value indicates whether the data item associated with the data ID is valid or invalid.”] [Abstract].
Jang, Cariello, and Shatsky are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jang and Cariello with Shatsky in order to modify Jang and Cariello “wherein the memory controller is configured to:
identify the first memory block by checking an indication bit corresponding to the first memory block,
wherein the indication bit indicates whether the first memory block comprises the specific data that is invalid” as taught by Shatsky. One of ordinary skill in the art would be motivated to combine Jang and Cariello with Shatsky before the effective filing date of the claimed invention to improve a system by providing for “an efficient method for tracking data block utilization.” [Shatsky, para. 0035].
Claim 18 is rejected with like reasoning.
As per claim 8, Jang in view of Cariello discloses the memory system of claim 1, However, Jang and Cariello do not explicitly disclose wherein the memory controller is configured to:
perform the garbage collection on the memory device while the memory device is idle.
Shatsky teaches wherein the memory controller is configured to:
perform the garbage collection on the memory device while the memory device is idle [“a garbage collection process can be performed asynchronously, in the background (e.g., during periods of idle time between I/O requests sent to the storage system)”] [para. 0066].
Jang, Cariello, and Shatsky are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jang and Cariello with Shatsky in order to modify Jang and Cariello “wherein the memory controller is configured to:
perform the garbage collection on the memory device while the memory device is idle” as taught by Shatsky. One of ordinary skill in the art would be motivated to combine Jang and Cariello with Shatsky before the effective filing date of the claimed invention to improve a system by providing for “an efficient method for tracking data block utilization.” [Shatsky, para. 0035].
Claim 15 is rejected with like reasoning.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. [hereafter as Jang], US Pub. No. 2023/0384957 A1 in view of Cariello [hereafter as Cariello], US Pub. No. 2023/0395117 A1 as applied to claims 1 and 11, and further in view of Lai et al. [hereafter as Lai], US Pub. No. 2020/0326874 A1.
As per claim 5, Jang in view of Cariello discloses the memory system of claim 1, However, Jang and Cariello do not explicitly disclose wherein the memory controller is configured to:
increase the priority level of the first memory block by decreasing a first valid page count (VPC) of the first memory block; and
perform a first garbage collection operation on the first memory block before a second memory block having a second VPC that is greater than the first VPC.
Lai teaches wherein the memory controller is configured to:
increase the priority level of the first memory block by decreasing a first valid page count (VPC) of the first memory block [“… the storage device controller 100 applies priorities … the corresponding valid page count is lower, the higher priority is applied.”] [para. 0065]; and
perform a first garbage collection operation on the first memory block before a second memory block having a second VPC that is greater than the first VPC [“In the case of the queue 510 related to GC, the storage device controller 100 applies priorities to the internal data movement requests according to the invalid page counts (IPCs) of the memory regions corresponding to the internal data movement requests. For example, as the corresponding IPC is higher or the corresponding valid page count is lower, the higher priority is applied.”] [para. 0065].
Jang, Cariello, and Lai are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jang and Cariello with Lai in order to modify Jang and Cariello “wherein the memory controller is configured to:
increase the priority level of the first memory block by decreasing a first valid page count (VPC) of the first memory block; and
perform a first garbage collection operation on the first memory block before a second memory block having a second VPC that is greater than the first VPC” as taught by Lai. One of ordinary skill in the art would be motivated to combine Jang and Cariello with Lai before the effective filing date of the claimed invention to improve a system by providing for “relatively few or no internal data movement requests to be processed by the storage device controller …, the write performance is improved… to stabilize the write efficiency of the host data”. [Lai, para. 0043].
Claim 12 is rejected with like reasoning.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. [hereafter as Jang], US Pub. No. 2023/0384957 A1 in view of Cariello [hereafter as Cariello], US Pub. No. 2023/0395117 A1 as applied to claims 1 and 10, and further in view of Klein [hereafter as Klein], US Pub. No. 2020/0218465 A1.
As per claim 6, Jang in view of Cariello discloses the memory system of claim 1, However, Jang and Cariello do not explicitly disclose wherein the memory controller is configured to:
receive a purge command to erase invalid specific data in the memory device; and
send a response indicating that the invalid specific data in the memory device have been erased.
Klein teaches wherein the memory controller is configured to:
receive a purge command to erase invalid specific data in the memory device [“in response to receiving the selective erase command, erasing, by the controller, blocks in which one or more pages mapped by the logical address are located based on a mapping table that maps the logical address to the one or more pages, wherein … invalid data, … are physically stored in the one or more pages.”] [claim 1]; and
send a response indicating that the invalid specific data in the memory device have been erased [“sending a selective erase command response to the host in response to execution of all of the erase commands”] [claim 9].
Jang, Cariello, and Klein are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jang and Cariello with Klein in order to modify Jang and Cariello “wherein the memory controller is configured to:
receive a purge command to erase invalid specific data in the memory device; and
send a response indicating that the invalid specific data in the memory device have been erased” as taught by Klein. One of ordinary skill in the art would be motivated to combine Jang and Cariello with Klein before the effective filing date of the claimed invention to improve a system “data security or privacy … perform selective erasure of data”. [Klein, para. 0006].
Claim 13 is rejected with like reasoning.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. [hereafter as Jang], US Pub. No. 2023/0384957 A1 in view of Cariello [hereafter as Cariello], US Pub. No. 2023/0395117 A1 and further in view of Klein [hereafter as Klein], US Pub. No. 2020/0218465 A1 as applied to claims 6 and 13, and further in view of Yun [hereafter as Yun], US Pub. No. 2014/0325168 A1.
As per claim 7, Jang in view of Cariello discloses the memory system of claim 6, However, Jang and Cariello do not explicitly disclose wherein the memory controller is configured to:
erase the invalid specific data in a corresponding memory block during the garbage collection before receiving the purge command.
Yun teaches wherein the memory controller is configured to:
erase the invalid specific data in a corresponding memory block during the garbage collection before receiving the purge command [“memory controller 210 may automatically erase invalid data among data DATA1 to DATAk in user storage region USR of storage region 235 without an additional erase command from host 100. Moreover, memory controller 210 may automatically erase the invalid data during performance of a garbage collection operation.”] [para. 0059].
Jang, Cariello, and Yun are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jang and Cariello with Yun in order to modify Jang and Cariello “wherein the memory controller is configured to:
erase the invalid specific data in a corresponding memory block during the garbage collection before receiving the purge command” as taught by Yun. One of ordinary skill in the art would be motivated to combine Jang and Cariello with Yun before the effective filing date of the claimed invention to “improve performance of a memory system by reducing data management overhead of a host and increasing the size of a programmable free storage region of the data storage device through automatic processing of invalid data.” [Yun, para. 0009].
Claim 14 is rejected with like reasoning.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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