FINAL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's arguments filed 6/18/2026 have been fully considered but they are not persuasive. While the ideas discussed during the interview conducted on 6/11/2026 would overcome the current prior art rejection, the amended claim language does not narrow the scope sufficiently. Compatible parity data only requires that there is parity that exists for more than one possible storage mode, or shared between data that can be in different modes. It does not require the parity to be generated only once for both storage modes the user data is written to.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7, 9, 11, 16, 18 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo (US 20220050612).
Regarding claim 1, Luo teaches A memory system, comprising: a memory device comprising memory blocks programmable in a first storage mode or a second storage mode, wherein the first storage mode has a lower storage density than the second storage mode(“In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells …. pages can be grouped to form blocks” ¶31);); and a memory controller coupled to the memory device, wherein the memory controller is configured to perform operations comprising: generating parity data corresponding to user data (“A memory sub-system can employ techniques to perform data recovery in the event of a memory defect associated with the programming of user data” ¶13); , wherein the parity data is compatible with the second storage mode; (“As described in more detail, herein, the shared parity stripe can include redundant array of independent NAND (RAIN) recovery data. In some embodiments, the shared parity stripe can be coded such that, in contrast to approaches in which the same sub-blocks or pages are placed in different planes within a same RAIN stripe, different sub-blocks or pages are placed in different planes within a same RAIN stripe” ¶19); writing, in the first storage mode, the user data and the parity data to a first set of memory blocks (“If each memory block sub-set includes 3 pages, then 48 KB of parity data can be generated and stored for each memory block sub-set across N planes.” ¶17) and writing, in the second storage mode, the user data and the parity data that are read from the first set of memory blocks to a second set of memory blocks (“The memory stripe coding management component 313 can cause a second page of data (e.g., the page of data P_1 338-2) corresponding to a data recovery operation to be written to a different plane 334-2 of the memory device 330.” ¶49).
Regarding claim 6, Luo teaches The memory system of claim 1, wherein data in the first set of memory blocks is associated with a first set of pages numbered in sequence, and data in the second set of memory blocks is associated with a second set of pages numbered in sequence (“A number of blocks (or sub-blocks), which can be referred to as pages 238-1 to 238-M (e.g., the PAGE _0 to the PAGE_M), can be included in each of the planes 234-1 to 234-P. That is, as shown in FIG. 2, a number of physical blocks (or sub-blocks) or pages 238-1 to 238-P can be included in a plane 234-1 to 234-P, and a number of planes 234-1 to 234-P can be included on a memory die 232-1 to 232-N.” ¶43); wherein writing the user data and the parity data that are read from the first set of memory blocks to the second set of memory blocks comprises: reading data associated with one or more first pages of the first set of pages; and writing the data to one or more second pages of the second set of pages (“The term “RAIN,” as used herein, is an umbrella term for computer information (e.g., data) storage schemes that divide and/or replicate (e.g., mirror) information among multiple pages of a memory sub-system, for instance, in order to help protect the data stored in the memory sub-system” ¶21); wherein page numbers of the one or more first pages and page numbers of the one or more second pages are identical (“For instance, in some embodiments, each row 236-1 to 236-R can include multiple physical pages 238-1 to 238-M of memory cells (e.g., one or more even pages of memory cells coupled to even-numbered word lines and/or bit lines, and one or more odd pages of memory cells coupled to odd numbered word lines and/or bit lines)” ¶44).
Regarding claim 7, Luo teaches wherein a first position of the parity data relative to the user data in the first set of memory blocks is identical to a second position of the parity data relative to the user data in the second set of memory blocks (“Each of the memory planes can include one or more sub-sets of memory blocks (e.g., the pages 238-1 to 238-M illustrated in FIG. 2, herein) that are physically arranged such that a first sub-set of memory blocks within a first memory plane is located in a same physical position within the first memory plane as a first sub-set of memory blocks with a second memory plane” ¶54).
received from an external host,” ¶6).
Regarding claim 9, Luo teaches where the operations comprise: in response to detecting a write failure when writing the user data and the parity data to the second set of memory blocks (“The memory stripe coding management component 313 can cause performance of the data recovery operation responsive to a determination that that a failure involving host data written to the memory device 330 has occurred.” ¶53); reading the user data and the parity data from the first set of memory blocks again.(“ In a non-limiting example, the memory stripe coding management component 313 can cause a first page of data (e.g., the page of data P_0 338-1) corresponding to a data recovery operation to be written to a plane 334-1 of a memory device 330. The memory stripe coding management component 313 can cause a second page of data (e.g., the page of data P_1 338-2) corresponding to a data recovery operation to be written to a different plane” ¶49).
Regarding claim 11, Luo teaches A memory controller, comprising: a processor and an interface, wherein the processor is configured to perform operations comprising: generating parity data (“If each memory block sub-set includes 3 pages, then 48 KB of parity data can be generated and stored for each memory block sub-set across N planes.” ¶17); corresponding to user data (“A memory sub-system can employ techniques to perform data recovery in the event of a memory defect associated with the programming of user data” ¶13); wherein the parity data is compatible with a second storage mode; (“As described in more detail, herein, the shared parity stripe can include redundant array of independent NAND (RAIN) recovery data. In some embodiments, the shared parity stripe can be coded such that, in contrast to approaches in which the same sub-blocks or pages are placed in different planes within a same RAIN stripe, different sub-blocks or pages are placed in different planes within a same RAIN stripe” ¶19); that has a higher storage density than a first storage mode (“In some embodiments, a particular memory device can include an SLC portion, and an MLC portion” ¶31); sending, through the interface, one or more first write commands to write the user data and the parity data to a first set of memory blocks in the first storage mode (“In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and/or the memory device 140.” ¶36); sending, through the interface, one or more read commands to read the user data and the parity data from the first set of memory blocks and sending, through the interface, one or more second write commands to write the user data and the parity data to a second set of memory blocks in the second storage mode.; (“The memory stripe coding management component 313 can cause a second page of data (e.g., the page of data P_1 338-2) corresponding to a data recovery operation to be written to a different plane 334-2 of the memory device 330.” ¶49).
Regarding claim 16, Luo teaches where the operations comprise: in response to detecting a write failure when writing the user data and the parity data to the second set of memory blocks (“The memory stripe coding management component 313 can cause performance of the data recovery operation responsive to a determination that that a failure involving host data written to the memory device 330 has occurred.” ¶53); reading the user data and the parity data from the first set of memory blocks again.(“ In a non-limiting example, the memory stripe coding management component 313 can cause a first page of data (e.g., the page of data P_0 338-1) corresponding to a data recovery operation to be written to a plane 334-1 of a memory device 330. The memory stripe coding management component 313 can cause a second page of data (e.g., the page of data P_1 338-2) corresponding to a data recovery operation to be written to a different plane” ¶49).
Regarding claim 18,Luo teaches A method of operating a memory system, comprising: generating parity data corresponding to user data (“If each memory block sub-set includes 3 pages, then 48 KB of parity data can be generated and stored for each memory block sub-set across N planes.” ¶17); wherein the parity data is compatible with a second storage mode; (“As described in more detail, herein, the shared parity stripe can include redundant array of independent NAND (RAIN) recovery data. In some embodiments, the shared parity stripe can be coded such that, in contrast to approaches in which the same sub-blocks or pages are placed in different planes within a same RAIN stripe, different sub-blocks or pages are placed in different planes within a same RAIN stripe” ¶19); that has a higher storage density than a first storage mode(“In some embodiments, a particular memory device can include an SLC portion, and an MLC portion” ¶31); writing the user data and the parity data to a first set of memory blocks in the first storage mode; and writing the user data and the parity data that are read from the first set of memory blocks to a second set of memory blocks in the second storage mode (“(“The memory stripe coding management component 313 can cause a second page of data (e.g., the page of data P_1 338-2) corresponding to a data recovery operation to be written to a different plane 334-2 of the memory device 330.” ¶49).
Regarding claim 19 Luo teaches where the operations comprise: in response to detecting a write failure when writing the user data and the parity data to the second set of memory blocks (“The memory stripe coding management component 313 can cause performance of the data recovery operation responsive to a determination that that a failure involving host data written to the memory device 330 has occurred.” ¶53); reading the user data and the parity data from the first set of memory blocks again.(“ In a non-limiting example, the memory stripe coding management component 313 can cause a first page of data (e.g., the page of data P_0 338-1) corresponding to a data recovery operation to be written to a plane 334-1 of a memory device 330. The memory stripe coding management component 313 can cause a second page of data (e.g., the page of data P_1 338-2) corresponding to a data recovery operation to be written to a different plane” ¶49).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 5, 8, 10, 13, 17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Ma (US 20230153019).
Regarding claim 2, Luo teaches wherein the first storage mode is a single-level cell (SLC) mode, wherein a memory cell in the first set of memory blocks stores one bit of data, wherein the second storage mode is a multi-level cell (MLC) mode, wherein a memory cell in the second set of memory blocks stores two or more bits of data, (“Each of the memory devices 130, 140 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs),” ¶31). Luo does not teach and wherein the parity data comprises redundant array of independent disks (RAID) parity data
Ma teaches and wherein the parity data comprises redundant array of independent disks (RAID) parity data (“As described above, the storage device 100 according to some example embodiments of the present disclosure may apply or use the RAID to or for data for which higher reliability is desired.” ¶59). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the use of different flash cell operating modes with the use of RAID. Luo teaches generating parity data for RAIN data protection, and RAID would also be a way for improved reliability (Ma ¶59).
Regarding claim 5, Ma teaches wherein a Redundant Array of Independent Disks (RAID) encoder of the memory controller is disabled when writing the user data and the parity data to the second set of memory blocks. (“the second write request including the second stream identifier and the second data, and receiving an RAID disable request from the external host, the RAID disable request including the first stream identifier and a RAID disable indication” ¶6).
Regarding claim 8, Ma teaches wherein the memory controller is configured to perform the operations in response to receiving, from a host, a write command to write the user data. (“the RAID enable request and the first write request being received from an external host” ¶6).
Regarding claim 10, Ma teaches wherein the operations comprise: in response to detecting a read failure when reading the user data from the second set of memory blocks, (“In operation S330, the storage device 100 may determine whether a read error is detected. For example, the storage controller 110 may detect an error of the read data provided from the nonvolatile memory device 120. When an error is detected from the read data, the storage controller 110 performs operation S340; when an error is not detected from the read data, the storage controller 110 performs operation S370.” ¶129); recovering the user data using the parity data from the second set of memory blocks (“The RAID engine 119 of the storage controller 110 may recover the data D17 by performing the recovery operation based on the remaining unit data D11 to D16 and the parity data “P”.” ¶138).
Regarding claim 13, Regarding claim 2, Luo teaches wherein the first storage mode is a single-level cell (SLC) mode, wherein a memory cell in the first set of memory blocks stores one bit of data, wherein the second storage mode is a multi-level cell (MLC) mode, wherein a memory cell in the second set of memory blocks stores two or more bits of data, (“Each of the memory devices 130, 140 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs),” ¶31). Luo does not teach and wherein the parity data comprises redundant array of independent disks (RAID) parity data
Ma teaches and wherein the parity data comprises redundant array of independent disks (RAID) parity data (“As described above, the storage device 100 according to some example embodiments of the present disclosure may apply or use the RAID to or for data for which higher reliability is desired.” ¶59).
Regarding claim 17, Regarding claim 10, Ma teaches wherein the operations comprise: in response to detecting a read failure when reading the user data from the second set of memory blocks, (“In operation S330, the storage device 100 may determine whether a read error is detected. For example, the storage controller 110 may detect an error of the read data provided from the nonvolatile memory device 120. When an error is detected from the read data, the storage controller 110 performs operation S340; when an error is not detected from the read data, the storage controller 110 performs operation S370.” ¶129); recovering the user data using the parity data from the second set of memory blocks (“The RAID engine 119 of the storage controller 110 may recover the data D17 by performing the recovery operation based on the remaining unit data D11 to D16 and the parity data “P”.” ¶138).
Regarding claim 20, Regarding claim 10, Ma teaches wherein the operations comprise: in response to detecting a read failure when reading the user data from the second set of memory blocks, (“In operation S330, the storage device 100 may determine whether a read error is detected. For example, the storage controller 110 may detect an error of the read data provided from the nonvolatile memory device 120. When an error is detected from the read data, the storage controller 110 performs operation S340; when an error is not detected from the read data, the storage controller 110 performs operation S370.” ¶129); recovering the user data using the parity data from the second set of memory blocks (“The RAID engine 119 of the storage controller 110 may recover the data D17 by performing the recovery operation based on the remaining unit data D11 to D16 and the parity data “P”.” ¶138).
Allowable Subject Matter
Claims 3, 4, 14 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yang US 20240403207, D’Abreu US 9244767, and Tam US 20140075259. These references were found through consultation with examiner Nathan Sadler (art unit 2139) regarding the word line spacing of parity data.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/SEAN KEVIN MCNAMARA/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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