Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a continuation application of U.S. Pat. App. Ser. No. 18/482,644 filed Oct 6, 2023, which is a continuation application of U.S. Pat. App. Ser. No. 17/685,250 filed Mar 2, 2022 and issued as U.S. Pat. No. 11,782,841 on Oct 10, 2023, which is a continuation application of U.S. Pat. App. Ser. No. 16/883,826 filed May 26, 2020 and issued as U.S. Pat. No. 11,294,820 on Apr 5, 2022, which claims priority to Prov. U.S. Pat. App. Ser. No. 62/868,060 filed Jun 28, 2019, claims 1-20 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/6/2025; 6/16/2025 and 11/24/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/482,644. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences between claims 1-20 of instant application and claims 1-20 of copending Application 18/482,644 are not sufficient to render the claim patentably distinct (claim 1 of the instant application and copending application 18/482,644 both claimed the core limitations: a device, comprising: an interface configured to communicate with a host system; a plurality of media units; and a logic circuit configured to manage programming of pages in the media units to accommodate a predetermined characteristics of data. However, the limitations of the instant application are anticipated by the U.S. copending Application 18/482,644.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
The following table only compares claim 1 of instant application to claim 1 of the U.S. copending Application 18/482,644.
Instant application 19/024060
Copending Application 18/482,644
A device, comprising:
A device, comprising:
an interface configured to communicate with a host system;
an interface configured to communicate with a host system;
a plurality of media units; and
a plurality of media units; and
a logic circuit configured to manage programming of pages in the media units to accommodate a predetermined characteristics of data
a logic circuit configured to manage programming of pages in the media units to accommodate a predetermined characteristics of data transfer through the interface,
wherein the logic circuit is configured to perform multi-pass programming of pages in the media units,
wherein the multi-pass programming includes a first atomic programming of a single data page of a predetermined size in the media units
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-14 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Canepa et al., US 9,905,294 B1.
Regarding claims 1, 9 and 17, Canepa teaches a device (a data storage device 100 in Fig.1 or an SSD data storage device 200 in Fig.5), comprising:
an interface (Fig.5; host I/F 206) configured to communicate with a host system (a host system is taught as a host device in abstract; col.3, lines 5-8; a non-volatile cache memory, such as an SLC flash cache, is configured to store a plurality of sequentially received pages of data from a host device; col.6, lines 17-18; A host interface (I/F) 206 provides communication paths with an external host device); a plurality of media units (Fig.4-6; N-level flash array; The array includes a plural number m of dies 214, each constituting a physically separate portion of the semiconductor integrated circuit(s) that make up the array 212); and a logic circuit (Fig.4 and 1; an SSD controller 160 (corresponding to the controller 102 in FIG. 1) ) configured to manage programming of pages in the media units (claim 1 of Canepa; a control circuit configured to direct a writing of first and second pages from the sequence of pages to a selected set of the n-level cells coupled to a common word line on a selected integrated circuit die; the second page separated from the first page in the sequence of pages by a logical offset comprising a plurality of intervening pages in the sequence of pages, the logical offset selected responsive to the m number of integrated circuit dies and a delay time associated with the transfer circuits) to accommodate a predetermined characteristics of data (claim 10; a host interface (I/F) circuit coupled to the host device, and the logical offset between the first page and the second page in the sequence of pages is further selected responsive to a host data transfer rate associated with the host I/F). for claim 17, Canepa further teaches a constant rate of data transfer (col.5, lines 29-39).
Regarding claims 2 and 10, Canepa teaches the predetermined characteristics is associated with a rate of data transfer between the device and host system over the interface (claim 10; a host interface (I/F) circuit coupled to the host device, and the logical offset between the first page and the second page in the sequence of pages is further selected responsive to a host data transfer rate associated with the host I/F).
Regarding claims 3 and 11, Canepa teaches the logic circuit is configured to manage the programming of the pages in the media units to accommodate the rate to be constant (col.5, lines 29-39; the data are written sequentially as received from the host device to a single flash device over a single flash bus; if each page 162 is 32 KB in length, the transfer rate Tr is 50 μs (e.g., the specified flash array read delay time to service a read command), the flash bus has a transfer rate of 400 MT/s (maximum rate at which data can be read from the array 164) and the host interface transfer rate is 1 GB/s).
Regarding claims 4 and 12, Canepa teaches the logic circuit is configured to perform multi-pass programming of pages in the media units (according to specification section 0108 and 0111; perform multi-pass programming of pages is taught as three pages X, Y and Z are written to different dies of the array 164, so that different read/write circuitry can access each of the separate die locations. As before, the data may be written sequentially as received from the host device, but this time to multiple dies across multiple lanes; col.5, lines 46-50).
Regarding claims 5 and 13, Canepa teaches the multi-pass programming includes a plurality of atomic programming operations; and the logic circuit is configured to manage transitions between modes of programming a memory cell in the atomic programming operations (col.2, lines 44-50; Each page of data is stored to the memory cells connected to the same word line, with a single bit of the page stored to a different cell along the word line. Memory cells that store multiple bits are often arranged to initially store a first page of data as SLCs. A second page of data written to the same cells transitions the cells to MLCs, a third page written to the same cells transitions the cells to TLCs, etc.).
Regarding claims 6 and 14, Canepa teaches the multi-pass programming includes: a first atomic programming of a single data page of a predetermined size in the media units; and a second atomic programming of two data pages each having the predetermined size in the media units (col.6, lines 23-26; An SLC cache memory 210 initially stores data received from the host. It is contemplated that the SLC cache memory 210 is formed from a set of non-volatile flash memory cells configured and operated as SLCs; col. 6, lines 28-33; Data accumulated in the cache memory 210 are subsequently transferred, under the direction of the SSD controller 202, to an n-level flash array 212. It is contemplated for purposes of the present example that the NAND flash memory cells of the n-level flash array are configured as TLCs; col.10; lines 2-5; The data are stored in any suitable fashion in the SLC cache. To simplify processing, it is contemplated that both the cache memory 210 and the main memory 212 will share a common page size (e.g., 32 KB)).
Regarding claim 18, Canepa teaches the device configured to perform multi-pass programming of pages in the media units via a plurality of atomic programming operations (col.2, lines 44-50; Each page of data is stored to the memory cells connected to the same word line, with a single bit of the page stored to a different cell along the word line. Memory cells that store multiple bits are often arranged to initially store a first page of data as SLCs. A second page of data written to the same cells transitions the cells to MLCs, a third page written to the same cells transitions the cells to TLCs, etc.), including a first atomic programming of a single data page of a predetermined size in the media units and a second atomic programming of two data pages each having the predetermined size in the media units; and wherein the device is further configured to manage transitions between modes of programming a memory cell in the atomic programming operations (col.6, lines 23-26; An SLC cache memory 210 initially stores data received from the host. It is contemplated that the SLC cache memory 210 is formed from a set of non-volatile flash memory cells configured and operated as SLCs; col. 6, lines 28-33; Data accumulated in the cache memory 210 are subsequently transferred, under the direction of the SSD controller 202, to an n-level flash array 212. It is contemplated for purposes of the present example that the NAND flash memory cells of the n-level flash array are configured as TLCs; col.10; lines 2-5; The data are stored in any suitable fashion in the SLC cache. To simplify processing, it is contemplated that both the cache memory 210 and the main memory 212 will share a common page size (e.g., 32 KB)).
Allowable Subject Matter
Claims 7-8, 15-16 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include the logic circuit is configured to determine a count of first transitions in modes of programming a memory cell in the first atomic programming and manage, based on the count, second transitions in modes of programming a memory cell in the second atomic programming in combination with the other claimed limitations as described in the claims 7,15 and 19 (claims 8, 16 and 20 are depended on claims 7, 15 and 19 respectively).
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133