The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (19/024,084) filed on January 16, 2025.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on January 16, 2025 have been considered and accepted.
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 14 and 20 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “critical flash translation layer” claim 7, claims are rejected under 35 U.S.C 112(b) as it is a relative term that was not defined.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 13-15 and 20 are rejected under 35 U.S.C. 103(a) as being disclosed by Kientz et al. (US PGPUB 2023/0195379 hereinafter referred to as Kientz), and further in view of Agarwal et al. (US 11,379,128 hereinafter referred to as Agarwal).
As per independent claim 1, Kientz discloses a system, comprising: a memory device; and a controller, coupled to the memory device, wherein the controller is configured to: receive a write command; select, based on a type of the write command, one of: a first set of trim values corresponding to a first type of the write command or a second set of trim values corresponding to a second type of the write command [(Paragraphs 0045-0049; FIG. 1 and 2A-B and related text) wherein McWilliams teaches where the programming voltages and/or other trims can be shifted based on the average number of PECs for a memory sub-system 110 as a whole, for a memory device 130 within the memory sub-system 110, or for a group of blocks within a memory device 130. For example, memory sub-system 110 can use a striping scheme to distribute data throughout a subset of dies of a memory device 130. A set of blocks distributed across a set of dies of a memory device using a striping scheme can be referred to as a “superblock.” Hence, the trim management component 113 can determine an average number of PECs for each superblock of a memory device. The first writing trim set “1” illustrated in column 214 can be applied when the average number of PECs is less than 30. For example, if the trim management component 113 determines that the average number of PECs is 25, the trim management component 113 can apply a value of -40 DACs for a write operation directed to base level 1 of a memory cell. To continue the example, at an average PEC of 25, the trim management component 113 can apply a value of -25 DACs to a write operation directed to a base level 7 of a memory cell. The trim management component 113 can indicate in a second data structure (e.g., data structure 230 illustrated in FIG. 2B) which writing trim set was used in executing the write operations directed to the block. That is, the trim management component 113 can indicate that writing trim set “1” was used to execute a write operation on the block. The second writing trim set “2” illustrated in column 216 can be applied when the average PEC of the memory device is greater than or equal to 30 and less than 1,000. For example, if the trim management component 113 determines that average PEC is 500, the trim management component 113 can apply a value of -20 DACs to a write operation directed to base level 3 of a memory cell. The trim management component 113 can update the indicator in data structure 230 to indicate that writing trim set “2” was used to write data to the block to correspond to the claimed limitation]; and executing the write command with the selected set of trim values [(Paragraphs 0041-0042) wherein Kientz teaches where the set of values can further include erase trims, and other trim values used when executing write operations to the memory sub-system. When the memory sub-system 110 receives a write request directed to a memory device (e.g., memory device 130), the trim management component 113 can execute the write request using the set of values associated with the average number of PECs. The trim management component 113 can update a second data structure to mark the set of values used when executing the write request. An example such second data structure is described with regard to FIG. 2B. The second data structure can list the blocks, groups of blocks, and/or sets of blocks. When the trim management component 113 executes a write request directed to a particular block (or group of blocks or set of blocks), the trim management component 113 can update the second data structure to indicate the set of program voltage and/or trim values used in the write request execution. The set of values can reference the first data structure, which lists the values for each set to correspond to the claimed limitation].
Kientz does not appear to explicitly disclose wherein the second set of trim values corresponds to a higher endurance characteristic of the memory device than the first set of trim values.
However, Agarwal discloses wherein the second set of trim values corresponds to a higher endurance characteristic of the memory device than the first set of trim values [(Column 3, lines 14-30 and Column 17, lines 20-53; FIGs. 1 and 6) where Agarwal teaches storing a first application set of configuration settings, where the first application set of configuration settings includes a first trim parameter setting for electrical signals used to write data units to a storage medium; storing a second application set of configuration settings, where the second application set of configuration settings includes a second trim parameter setting for electrical signals used to write data units to the storage medium and the first trim parameter setting is different from the second trim parameter setting; receiving, at a storage device, a storage command for a target data unit; selecting, based on an application type for the storage command, a set of configuration settings selected from the first application set of configuration settings and the second application set of configuration settings; and executing, using the selected set of configuration settings, the storage command to a storage medium of the storage device; FIG. 6 shows write profiles 600 for four consecutive bits according to two configurations 610, 620. In write signals, there is an inverse correlation between performance and reliability. By writing slowly, the read performance and reliability are increased, but the performance (in terms of number of operations per unit time) are decreased. By changing the trim settings for the write signal, the storage device can vary and adjust this tradeoff for different applications. For example, configuration settings for writing slowly (for applications that do not need fast write performance) may allow cells to be programmed as fast as needed for the application, while increasing reliability. Write profile 612 in configuration 610 includes four bits 612.1-612.4 programmed in non-volatile memory cells. Write profile 612 may include a profile width based on trim parameters that determine the write speed and/or signal timing for write profile 612. For example, profile widths 614.1-614.4 in configuration 610 may result in high write performance, low read performance, and a higher bit error rate. Configuration 610 may correlate to a first reliability value for the configuration set of storage device configuration settings that generate write profile 612. Write profile 622 in configuration 620 includes four bits 622.1-622.4 programmed in non-volatile memory cells. Write profile 622 may include a narrower profile width based on trim parameters that determine the write speed and/or signal timing for write profile 622. For example, profile widths 624.1-624.4 in configuration 620 may result in lower write performance, higher read performance, and a lower bit error rate compared to configuration 610. Configuration 620 may correlate to a second reliability value for a different configuration set of storage device configuration settings that generate write profile 622 to correspond to the claimed limitation].
Kientz and Agarwal are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kientz and Agarwal before him or her, to modify the method of Kientz to include the preset poll rule of controllers of Agarwal because it will enhance efficiency.
The motivation for doing so would be [“profile widths 624.1-624.4 in configuration 620 may result in lower write performance, higher read performance, and a lower bit error rate compared to configuration 610. Configuration 620 may correlate to a second reliability value for a different configuration set of storage device configuration settings that generate write profile 622” (Column 17, lines 45-55 by Agarwal)].
Therefore, it would have been obvious to combine Kientz and Agarwal to obtain the invention as specified in the instant claim.
As per dependent claim 6, Agarwal discloses wherein a first write command of the first type is generated by a host device coupled to the controller and a second write command of the second type is generated by the controller [(Column 2, lines 27-42 and Column 18, lines 41-67) where Agarwal teaches the device controller may be further configured to: send the first application set of configuration settings to a host system; and receive the second application set of configuration settings from the host system, where the first application set of configuration settings are a default set of configuration settings. The device controller may be further configured to: configure a first set of storage blocks in the storage medium with the first application set of configuration settings; and configure a second set of storage blocks in the storage medium with the second application set of configuration settings, where selecting the selected set of configuration settings uses a storage location in the storage command and the storage location is selected from the first set of storage blocks and the second set of storage blocks; At block 912, a storage command may be received. For example, the device controller may receive a storage command from a host system indicating that the storage command should be processed according to a corresponding application set of configuration settings to correspond to the claimed limitation].
As per dependent claim 7, Agarwal discloses wherein the first type of write command is one of a critical flash translation layer (FTL) journal write, a media management operation, or an error handling operation [(Column 6, lines 37-55 and Column 13, lines 35-55; FIGs. 1 and 7) where Agarwal teaches application settings 110.1 may include a plurality of application sets of storage device configuration settings, where each application set corresponds to a selected application or application type in applications 102. For example, application settings 110 may include an application set of storage device configuration settings for financial or transactional applications and another application set of storage device configurations for video or media applications. In some embodiments, application settings 110 may include a graphical user interface for configuring and storing application sets of storage device configuration settings and providing those sets of storage device configuration settings to storage devices 140. In some embodiments, an application identifier and/or application type may be associated with each set of storage device configuration settings and the application identifier or application type may be included in storage commands from hosts 106 to storage devices 140 and indicate the set of storage device configuration settings to be used for executing the storage command; a plurality of configuration setting types may be managed in configuration settings 530. For example, configuration setting types may include write settings 532, error correction settings 534, redundancy settings 536. In some embodiments, each configuration setting type may itself include a plurality of configuration setting parameters corresponding to different parameters that drive reliability and performance for that particular configuration setting type. For example, write settings 532 may include a plurality of parameters related to the electrical signals used to write a bit, line, or page to the cells in memory dies 550. In some embodiments, one or more trim parameters, such as write signal timing, pulse counts, pulse widths, applied voltage levels, etc. may be among write settings 532 to correspond to the claimed limitation].
As for independent claims 8 and 15, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 13, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
As for dependent claims 14 and 20, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claims 2, 9 and 16 is rejected under 35 U.S.C. 103(a) as being disclosed by Kientz and Agarwal, as applied to claims 1, 8 and 15, and further in view of Wieduwilt et al. (US PGPUB 2021/0263848 hereinafter referred to as Wieduwilt).
As per dependent claim 2, Kientz/Agarwal discloses the system of claim 1.
Kientz/Agarwal does not appear to explicitly disclose wherein the first set of trim values is stored by a plurality of fuses within the memory device, and executing the write command with the second set of trim values comprises enabling a latch coupled to at least one of the plurality of fuses.
However, Wieduwilt discloses wherein the first set of trim values is stored by a plurality of fuses within the memory device, and executing the write command with the second set of trim values comprises enabling a latch coupled to at least one of the plurality of fuses [(Paragraphs 0070-0074) wherein First global trimming latch 360-a may be configured to store a bit of first global trimming information that is used to adjust a first set of operating parameters at memory bank 300-a. In some examples, first global trimming latch 360-a may store a bit of a first global trim parameter. In some cases, first global trimming latch 360-a is a D flip flop. In some examples, a bit of data (e.g., a bit of a first global trim parameter) may be applied to the input of first global trimming latch 360-a, and a voltage corresponding to the bit of data may be output by first global trimming latch 360-a after receiving a clocking signal from first logic gate 340-a. In some cases, first global trimming latch 360-a is coupled with and receives first global trimming information from a first fuse set. In some cases, option circuitry 305-a includes multiple first global trimming latches—e.g., the number of first global trimming latches may correspond to the number of bits used to convey a first global trim parameter. In some cases, the multiple first global trimming latches are coupled with and receive first global trimming information from a single fuse set. In some cases, the multiple first global trimming latches are coupled with and receive first global trimming information from multiple fuse sets that each store a single bit of the first global trimming information. And in other cases, the multiple first global trimming latches are coupled with and receive first global trimming information from multiple fuse sets that each store multiple bits of the first global trimming information. Second global trimming latch 365-a may be similarly configured as first global trimming latch 360-a. In some examples, second global trimming latch 365-a may store a bit of second global trimming information that is used to adjust a second set of operating parameters at memory bank 300-a. In some examples, second global trimming latch 365-a may store a bit of a second global trim parameter. In some examples, second global trimming latch 365-a is coupled with and receives the second global trimming information from a second fuse set that is different than a first fuse set that stores first global trimming information. In some examples, second global trimming latch 365-a may receive the second global trimming information from a first fuse set that stores first global trimming information. In some examples, option circuitry 305-a includes multiple second global trimming latches—e.g., the number of second global trimming latches may correspond to the number of bits used to convey a second global trim parameter to correspond to the claimed limitation].
Kientz/Agarwal and Wieduwilt are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kientz/Agarwal and Wieduwilt before him or her, to modify the method of Kientz/Agarwal to include the memory operations of Wieduwilt because it will enhance system performance.
The motivation for doing so would be [“ improving a performance of the memory system” (Paragraph 0011 by Wieduwilt)].
Therefore, it would have been obvious to combine Kientz/Agarwal and Wieduwilt to obtain the invention as specified in the instant claim.
As for dependent claims 9 and 16, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Claims 3, 4, 10, 11, 17 and 18 is rejected under 35 U.S.C. 103(a) as being disclosed by Kientz and Agarwal, as applied to claims 1, 8 and 15, and further in view of Sicard et al. (US PGPUB 2023/0304872 hereinafter referred to as Sicard).
As per dependent claim 3, Kientz/Agarwal discloses the system of claim 1.
Kientz/Agarwal does not appear to explicitly disclose wherein the first set of trim values comprises a first start voltage which is higher than a second start voltage of the second set of trim values.
However, Sicard discloses wherein the first set of trim values comprises a first start voltage which is higher than a second start voltage of the second set of trim values [(Paragraphs 0100-0102; Figs.4 and 5 and their related text) wherein FIG. 4 shows a graph of the PTAT voltage 400 from terminal 102 received at the dynamic calibration module 111 on the y-axis 401 versus temperature on the x-axis. As expected, the PTAT voltage 400 is substantially linear with temperature. The set of ranges 403 illustrate the contiguous set of voltage ranges and correspond to the ranges 310-317 shown along the x-axis of FIG. 3, although not all of them are shown in FIG. 4. Each voltage range, taking the range 404 as an example, is defined by a lower limit voltage 406 and an upper limit voltage 407. When the PTAT voltage 400 is in a voltage range 404, that is between the lower limit voltage 406 and the upper limit voltage 407, the dynamic calibration module 111 is configured to add or subtract a predetermined number of bits from the predetermined calibration value to generate the trim value to correspond to the claimed limitation].
Kientz/Agarwal and Sicard are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kientz/Agarwal and Sicard before him or her, to modify the method of Kientz/Agarwal to include the trim circuit of Sicard because it will enhance system performance.
The motivation for doing so would be [“provide the greatest accuracy” (Paragraphs 0098-0100 by Sicard)].
Therefore, it would have been obvious to combine Kientz/Agarwal and Sicard to obtain the invention as specified in the instant claim.
As per dependent claim 4, Sicard discloses wherein the first set of trim values comprises a first step voltage which is higher than a second step voltage of the second set of trim values [(Paragraphs 0127-0129; FIGs. 1 and 5) where Agarwal teaches at time 520, the line 504 shows the lower limit voltage being set to that of the lowest “candidate” range of the set of voltage ranges. In this “candidate” voltage range, the trim value is set to “111” as shown at 521. The signals 510 and 511 are both low, which in this example indicates that the PTAT voltage 503 is not in the “candidate” voltage range between 504 and 505 at time 520. At time 522, the logic module 243 has provided an initialization signal (a spike) that causes the dynamic calibration module 111 to step to the next “candidate” voltage range. Accordingly, at time 522, the lower limit voltage 504 increases to that of the next “candidate” voltage range and the upper limit voltage 505 increases to that of the same, next “candidate” voltage range. In this next “candidate” voltage range, the trim value is set to “110” as shown at 523. The signals 510 and 511 are both low, which in this example indicates that the PTAT voltage 503 is not in the next “candidate” voltage range either between 504 and 505 at time 522. At time 524, the logic module 243 has provided an initialization signal (a spike) that causes the dynamic calibration module 111 to step to the second next “candidate” voltage range. Accordingly, at time 524, the lower limit voltage 504 increases to that of the second next “candidate” voltage range and the upper limit voltage 505 increases to that of the same, second next “candidate” voltage range. In this second next “candidate” voltage range, the trim value is set to “101” as shown at 525. The signal 510 has gone high and the signal 511 is low, which in this example indicates that the PTAT voltage 503 is within the second next “candidate” voltage range at time 524. Thus, the current voltage range has been found. The dynamic calibration module 111 may now operate as described above by detecting subsequent changes in the PTAT voltage 503 relative to the upper and lower limit voltages 504, 505 and changing the trim value accordingly. Thus, at time 526, the signal 510 has provided an indication (i.e. the downward spike just before time 526) that the PTAT voltage 503 has exceeded the upper limit voltage 505 set for time 524. Thus, the current voltage range changes and trim value is changed accordingly to “100” in this example. Further, the upper limit voltage 505 and the lower limit voltage 504 are also updated for the changed current voltage range to correspond to the claimed limitation].
As for dependent claims 10 and 17, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claims 11 and 18, the applicant is directed to the rejections to claim 4 set forth above, as they are rejected based on the same rationale.
Claims 5, 12 and 19 is rejected under 35 U.S.C. 103(a) as being disclosed by Kientz and Agarwal, as applied to claims 1, 8 and 15, and further in view of Ferrario et al. (US 8,963,589 hereinafter referred to as Ferrario).
As per dependent claim 5, Kientz/Agarwal discloses the system of claim 1.
Kientz/Agarwal does not appear to explicitly disclose wherein the first set of trim values comprises a first ramp up time of a voltage pulse which is shorter than a second ramp up time of a voltage pulse of the second set of trim values.
However, Ferrario discloses wherein the first set of trim values comprises a first ramp up time of a voltage pulse which is shorter than a second ramp up time of a voltage pulse of the second set of trim values [(Column 10, lines 17-42) wherein a trim value of 7.3 would return a measured ramp equal to the target. Any greater trim value leads to a shorter measured time. In a first iteration of the algorithm, if the test TRIM_VALUE=7 and the signal > pulses high, this indicates that the ramp is slow and the ideal trim value is somewhere between 7 and 15. In a second iteration of the algorithm, the test TRIM_VALUE=11 because the signal > was high and 1/4 of the full range (i.e., 16/4=4) was added to the previously tested value. In this case, the < signal pulses high indicating that the ramp is fast and the ideal trim value is somewhere between 7 and 11. In a third iteration of the algorithm, the test TRIM_VALUE=9 because the signal < was high and 1/8 of the full range (i.e., 16/8=2) was subtracted from the previously tested value. In this case, the < signal pulses high indicating that the ramp is still too fast and the ideal trim value is somewhere between 7 and 9. In a fourth iteration of the algorithm, the test TRIM_VALUE=8 because the signal < was high and 1/16 of the full range (i.e., 16/16=1) was subtracted from the previously tested value. In this case, the < signal pulses high indicating that the ramp is still too fast and the ideal trim value is somewhere between 7 and 8. Having reduced the difference to one, the binary search algorithm terminates. The modulation value will now start with a base trim value of 7 and modulation at 50%. This will produce a slope at 7.5. The tracking portion of the process will then drive the slope value to the target at 7.3 to correspond to the claimed limitation].
Kientz/Agarwal and Ferrario are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kientz/Agarwal and Ferrario before him or her, to modify the method of Kientz/Agarwal to include the ramp generation circuit of Ferrario because it will enhance system performance.
The motivation for doing so would be [“accordingly a need in the art for a ramp generator circuit having an accurate and constant slope” (Column 1, lines 26-28 by Ferrario)].
Therefore, it would have been obvious to combine Kientz/Agarwal and Ferrario to obtain the invention as specified in the instant claim.
As for dependent claims 12 and 19, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Qawami et al., US PGPUB 2019/0205030– teaches TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached on Monday-Friday, 8:00 AM to 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135