DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication (Amendment) filed on 07/20/2026.
Status of claims in the instant application:
Claims 21-40 are pending.
Claims 1-20 remain canceled.
No new claim has been added.
Claims 27 and 29 have been amended.
Claim Objections
Claim 29 is objected to because of the following informalities:
Claim 29, as amended, recites, “determine, based on the validation, that at least a portion the data already attempted to be copied to the second memory region was not successfully copied from the first memory region to the second memory region”.
There appears to be grammatical error in the emphasized part of the claim. It should say, “… a portion of the data …”.
Appropriate correction is required.
Response to Arguments
Applicant’s arguments, see page [1] of the remarks filed on 07/20/2026 with respect to objection to claims, have been fully considered in view of claim amendments and are persuasive. Therefore, the claim objections are withdrawn.
Applicant’s arguments, see page [1] of the remarks filed on 07/20/2026 with respect to rejection of claims under 35 USC 112(b), have been fully considered in view of claim amendments and are persuasive. Therefore, the claim rejections are withdrawn.
Applicant’s arguments, see page [6] of the remarks filed on 07/20/2026 with respect to rejection of claims under non-statutory double patenting, have been fully considered. Applicant agreed to Examiner’s double patenting rejection. Therefore, the claim rejections are maintained.
Applicant's arguments, see page [2-6] of the remarks filed on 07/20/2026 with respect to rejection of claims under 35 USC 103, have been fully considered but they are not persuasive. Therefore, the claim rejections are maintained, and the Applicant is directed to Examiner’s response below.
Furthermore, Applicant’s claim amendment (for claim 29) has rendered new grounds for rejection.
Applicant states, see page [2-6] of the remarks filed on 07/20/2026 with respect to independent claims 21 and 29, that Huang prior art does not discloses “copy the data from the first memory region to the second memory region ; and validate, while the data is being copied from the first memory region to the second memory region, the data using the hash value”. Applicant has also reproduced Fig. 8 and related description of Huang prior art in the remarks, and they are not being reproduced here to keep the response concise and to the point.
In response, Examiner respectfully disagrees Applicant’s characterization of Huang prior art not disclosing certain claimed features as claimed by the Applicant.
Huang prior art specifically discloses that “At block 802, a process initiates a GC in a flash memory in response to a predefined triggering event for recovering storage space. For example, the GC process can be activated in response to detecting expired blocks … At block 804, upon identifying a first valid page within a first block marked as an erasable block, a first signature representing the content of the first valid page is determined by a signature generator. For example, the process is capable of hashing the content of the first valid page to generate a unique value representing the first valid page … At block 806, a second valid page is identified within a second block as a duplicated page of the first valid page when the first signature matches with a signature associated with the second valid page … At block 808, the GC process associates LBA of the first valid page to the second valid page … The compressed first valid page is subsequently rewritten to a new block or valid block …”
Huang prior art clearly discloses initiating the process to determine if a valid page (data in a memory region) needs to be copied to a new block (second memory region), and if the determination/validation, using signature/hash, indicates copying of data is needed then the process copies data from one region to a new region in the memory (SSD).
Furthermore, rejection of the claims are in combination of Huang and Annapureddy prior arts. But Applicant argued only about Huang prior art, and not the combination the prior arts used by the Examiner to show how they disclose Applicant’s claimed feature(s) making the claimed invention obvious.
In response to applicant's arguments against the references individually, Examiner notes that, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Examiner asserts that combination of Huang and Annapureddy prior art clearly discloses all elements of Applicant’s claimed feature as noted previously, and that the combination of Huang and Annapureddy makes Applicant’s claimed invention obvious.
Applicant states, see page [6] of the remarks filed on 07/20/2026 with respect to independent claims 36, that Huang prior art does not discloses “The Office Action cited Fig. 8 and paragraphs 35, 36, and 59 of Huang as allegedly teaching such elements. Fig. 8 and paragraphs 35/36 of Huang do not teach or suggest the emphasized elements above for at least the same reasons discussed above with respect to Claims 1 and 9. Paragraph 59 of Huang states, with emphasis added: Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory . The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608.
Huang therefore describes a basic data buffer operation where data that is going to be written into a flash memory may be buffered. However, receiving data from a command processor at a data buffer before it is written into a flash memory is wholly unrelated to the copying data in a memory device from one region to another, and therefore does not recite the elements of Claim 36 including a controller configured to “copy the data from the first memory region to the cache; begin to copy the data from the cache to the second memory region; and perform a validation, while the data is being copied from the cache to the second memory region, of the data using the hash value.”
In response, Examiner respectfully disagrees Applicant’s characterization of Huang prior art not disclosing certain claimed features as claimed by the Applicant.
Examiner would like to note that Applicant’s reference to claim 1 and claim 9 is assumed to be an unintentional error as they were already canceled previously, and they are meant to be claim 21 and claim 29. Examiner has already responded to Applicant’s arguments regarding claims 21 and 29.
Now with respect to Applicant’s arguments regarding claim 36, this claim requires 3 data storing elements (first memory region, cache and second memory region). Applicant’s claim is to copy data from first memory region to the second memory region via cache (cache being the intermediary).
Examiner asserts that Huang also discloses three elements/entities for copying/storing data form one storing element to another storing element via data buffer, where data buffer being the intermediary performing the same function as the cache in applicant’s claimed invention.
Applicant’s claimed invention is not about what makes the memory regions and cache different, it’s rather providing the cache as acting as an intermediary between two memory regions while copying data from one memory region to the other memory region, the same function that Huang’s data buffer performs.
Examiner also notes that
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-40 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18513197 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are just a broader version of the claims in the reference application..
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application
Reference Application (18513197)
21. (New) A device, comprising: a plurality of memory regions, including a first memory region and a second memory region; and a controller configured to: generate a hash value of data stored in the first memory region; copy the data from the first memory region to the second memory region; and validate, while the data is being copied from the first memory region to the second memory region, the data using the hash value.
1. (Currently Amended) A device, comprising: a plurality of memory regions, including a first memory region and a second memory region; and a controller configured to: generate a hash value of first data stored in the first memory region; copy the first data from the first memory region to the second memory region as second data, comprising the controller configured to write the second data to the second memory region; and validate, while the first data is being copied from the first memory region to the second memory region as the second data, the second data using the hash value.
22. (New) The device of claim 21, wherein the data is not fully copied into the second memory region until after the data has been validated using the hash value.
2. (Currently Amended) The device of claim 1, wherein the second data is not fully copied into the second memory region until after a portion of the second data has been validated using the hash value.
23. (New) The device of claim 21, wherein the controller is further configured to erase the data from the first memory region after that data has been validated using the hash value.
3. (Currently Amended) The device of claim 1, wherein the controller is further configured to erase the first data from the first memory region after that the second data has been validated using the hash value.
24. (New) The device of claim 21, wherein the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of flash memory of the solid state drive.
4. (Original) The device of claim 1, wherein the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of flash memory of the solid state drive.
25. (New) The device of claim 21, wherein the hash value of the data is generated while the data is stored in the first memory region.
5. (Currently Amended) The device of claim 1, wherein the hash value of the first data is generated while the first data is stored in the first memory region.
26. (New) The device of claim 25, wherein the hash value of the data is further generated before the data is copied to the second memory region.
6. (Currently Amended) The device of claim 5, wherein the hash value of the first data is further generated before the second data is copied to the second memory region.
27. (New) The device of claim 21, wherein the controller is further configured to store the hash value in a cache while the data is copied from the first memory region to the second memory region.
7. (Currently Amended) The device of claim 1, wherein the controller is further configured to store the hash value in a cache while the first data is copied from the first memory region to the second memory region as the second data.
28. (New) The device of claim 21, wherein the validation of the data using the hash value indicates that the data has been successfully copied from the first memory region to the second memory region.
8. (Currently Amended) The device of claim 1, wherein the validation of the second data using the hash value indicates that the first data has been successfully copied from the first memory region to the second memory region as the second data.
29. (New) A device, comprising: a plurality of memory regions, including a first memory region and a second memory region; and a controller configured to: generate a hash value of data stored in the first memory region; copy the data from the first memory region to the second memory region; perform a validation, while the data is being copied from the first memory region to the second memory region, of the data using the hash value; and determine, based on the validation, that at least a portion the data already attempted to be copied to the second memory region was not successfully copied from the first memory region to the second memory region.
9. (Currently Amended) A device, comprising: a plurality of memory regions, including a first memory region and a second memory region; and a controller configured to: generate a hash value of data stored in the first memory region; copy the data from the first memory region to the second memory region, comprising the controller configured to write the data to the second memory region; perform a validation, while the data is being copied from the first memory region to the second memory region, of the data using the hash value; determine, based on the validation, that at least a portion the data already attempted to be copied to the second memory region was not successfully copied from the first memory region to the second memory region; and based on a determination that the data was successfully copied, lock a cache used to copy the data from the first memory region to the second memory region.
30. (New) The device of claim 29, wherein the controller is further configured to prevent the data from being fully copied from the first memory region to the second memory region based on the determination that the data was not successfully copied from the first memory region to the second memory region.
10. (Original) The device of claim 9, wherein the controller is further configured to prevent the data from being fully copied from the first memory region to the second memory region based on the determination that the data was not successfully copied from the first memory region to the second memory region.
31. (New) The device of claim 29, wherein the controller is further configured to prevent the data from being copied from the second memory region to a third memory region based on the determination that the data was not successfully copied from the first memory region to the second memory region.
11. (Original) The device of claim 9, wherein the controller is further configured to prevent the data from being copied from the second memory region to a third memory region based on the determination that the data was not successfully copied from the first memory region to the second memory region.
32. (New) The device of claim 29, wherein the controller is further configured to, based on the determination that the data was not successfully copied, abort any movement or copying of the data from the first memory region or the second memory region.
12. (Original) The device of claim 9, wherein the controller is further configured to, based on the determination that the data was not successfully copied, abort any movement or copying of the data from the first memory region or the second memory region.
33. (New) The device of claim 29, wherein the controller is further configured to, based on the determination that the data was not successfully copied, generate an alert that the data was not successfully copied from the first memory region or the second memory region.
13. (Original) The device of claim 9, wherein the controller is further configured to, based on the determination that the data was not successfully copied, generate an alert that the data was not successfully copied from the first memory region or the second memory region.
34. (New) The device of claim 29, wherein the controller is further configured to, based on the determination that the data was not successfully copied, restart the copying of the data from the first memory region or the second memory region.
14. (Original) The device of claim 9, wherein the controller is further configured to, based on the determination that the data was not successfully copied, restart the copying of the data from the first memory region or the second memory region.
35. (New) The device of claim 29, wherein the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of flash memory of the solid state drive.
15. (Original) The device of claim 9, wherein the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of flash memory of the solid state drive.
36. (New) A device, comprising: a plurality of memory regions, including a first memory region, a cache, and a second memory region; and a controller configured to: generate a hash value of data stored in the first memory region; copy the data from the first memory region to the cache; begin to copy the data from the cache to the second memory region; and perform a validation, while the data is being copied from the cache to the second memory region, of the data using the hash value.
16. (Currently Amended) A device, comprising: a plurality of memory regions, including a first memory region, a cache, and a second memory region; and a controller configured to: generate a hash value of data stored in the first memory region; copy the data from the first memory region to the cache, comprising the controller configured to write the data to the cache; begin to copy the data from the cache to the second memory region; perform a validation, while the data is being copied from the cache to the second memory region, of the data using the hash value; and based on a determination that the data was successfully copied, lock the cache.
37. (New) The device of claim 36, wherein the controller is further configured to determine, based on the validation, that the data was successfully copied from the first memory region to the cache.
17. (Original) The device of claim 16, wherein the controller is further configured to make the determination, based on the validation, that the data was successfully copied from the first memory region to the cache.
38. (New) The device of claim 37, wherein the controller is further configured to, based on the determination that the data was successfully copied, lock the cache to prevent the data in the cache from being changed while the data from the cache finishes copying to the second memory region.
18. (Original) The device of claim 17, wherein the controller is further configured to, based on the determination that the data was successfully copied, lock the cache to prevent the data in the cache from being changed while the data from the cache finishes copying to the second memory region.
39. (New) The device of claim 38, wherein the controller is further configured to, after the data is fully copied from the cache to the second memory region, unlock the cache so that the data in the cache may be changed.
19. (Original) The device of claim 18, wherein the controller is further configured to, after the data is fully copied from the cache to the second memory region, unlock the cache so that the data in the cache may be changed.
40. (New) The device of claim 36, wherein the controller is further configured to determine, based on the validation, that the data was not successfully copied from the first memory region to the cache.
20. (Original) The device of claim 16, wherein the controller is further configured to determine, based on the validation, that the data was not successfully copied from the first memory region to the cache.
**** Claims 21-37 and 40 are also are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, 9 and 21 of U.S. Patent No. 11822489. Although the claims at issue are not identical, they are not patentably distinct from each other, because the claims of the instant application merely are broader version of claims of the reference patent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 23-28 and 36-37 are rejected under 35 U.S.C. 103 as being unpatentable over Pub. No.: US 20150019797 A1 to Huang et al. (hereinafter “Huang”) in view of Pub. No.: US 20180004505 A1 to Annapureddy et al. (hereinafter “Annapureddy”).
Regarding Claim 21. (New) Huang discloses A device (Huang, Para [0023]: … FIG. 1 is a block diagram 100 illustrating a memory device …), comprising:
a plurality of memory regions, including a first memory region and a second memory region (Huang, Para [0004, 0023-0024, 0059]: … A flash memory device is typically organized in multiple blocks wherein each block is further divided into a set of pages. In some examples, each page can be further divided into multiple addressable sectors … Diagram 100 illustrates a logic diagram of SSD using a group of flash memory 110 to persistently retain information without power supply. The SSD includes multiple non-volatile memories or flash memory blocks 112-114 … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …); and
a controller (Huang, Para [0023-0024]: … Diagram 100 includes input data 108, memory device 110, output data 128, and memory controller 106 … ) configured to:
generate a hash value of data stored in the first memory region (Huang, Para [0023-0024, 0027]: … Memory controller 106 further includes GC 132, GC events 130, de-dupe module 140, compressor 150, sequencer 160 … De-dupe module or du-dupe 140, in one embodiment, is capable of identifying a duplicated page in a valid block based on identified valid page in an erasable block. De-dupe module 140 includes a hasher and a signature table. The hasher, also known as signature generator, is able to generate a unique signature through a hashing operation. The hasher hashes the content of valid page to come up with an identifiable unique signature based on the content of page …);
copy the data from the first memory region to the second memory region (Huang, Para [0035-0036, 0059], FIG. 8: … During an operation, upon identifying a data block subject to a garbage collection, a list of physical addresses of valid pages within the data block that need to be moved for garbage collection is determined. After applying de-dupe procedure in accordance with the list of valid pages, the valid pages are not rewritten or moved if duplicated pages are found in other blocks. If duplicated pages are not found, the valid pages are rewritten to a new block(s) before erasing the erasable block(s). Note that an erasable block means a block subject to the garbage collection … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …); and
validate, [while the data is being copied from the first memory region to the second memory region], the data using the hash value (Huang, Para [0035-0036, 0057], FIG. 8: … In order to de-dupe the data, signature generator 250 generates a hash value or signature based on the content of valid page such as page 234 in block 212 which is marked for deletion. Note that the signature or hash value is generated over the whole data set within page 234 or content of page 234. After generating a signature for page 234, comparator 256 compares the signature of page 234 with every entries of signature table 252. Signature table 252 stores multiple signatures indicating valid pages currently in memory 110. If the signature of page 234 matches with one of the entry in signature table 252 as indicated by numeral 258, a duplicated page in a block is identified … During an operation, upon identifying a data block subject to a garbage collection, a list of physical addresses of valid pages within the data block that need to be moved for garbage collection is determined. After applying de-dupe procedure in accordance with the list of valid pages, the valid pages are not rewritten or moved if duplicated pages are found in other blocks. If duplicated pages are not found, the valid pages are rewritten to a new block(s) … ).
However, Huang does not explicitly teach, but Annapureddy from same or similar field of endeavor teaches:
“validate, while the data is being copied from the first memory region to the second memory region (Annapureddy, Para [0036, 0044]: … FIG. 5 shows an illustrative fault-tolerant UEFI variable region repaving method 500 that is performed in an FOTA update process with reference to the diagram of the memory 400 shown in FIG. 4. The term “repaving” as used herein means some or all of the UEFI variables in the primary region are replaced by corresponding variables from the firmware update payload 230 (FIG. 2) … some of the methods or steps thereof can occur or be performed concurrently and not all the methods or steps have to be performed in a given implementation depending on the requirements of such implementation and some methods or steps may be optionally utilized. In step 505, the contents of the primary region 405 are copied and written to the spare region 410 using the FTW protocol described above (the spare region is typically erased prior to step 505 being performed) … FIG. 8 shows an illustrative cryptographic process 802 that is exposed on a device (e.g., device 110, 114 in FIG. 1) to validate UEFI variable records in a firmware update payload 230 prior to UEFI variable region repaving, as described above in the text accompanying FIG. 5 … The secure boot manifest 810 itself is trusted by verifying that a hash of the public key 812 used for authentication matches that stored on the OTP fuses 270. The process 802 validates the variable records by verifying that a runtime-calculated hash 815 of the variable records matches the hash contained in the secure boot manifest 810, as indicated by reference numeral 820. Thus, the cryptographic validation process provides that the integrity of the variable records is ensured so that only valid variable records are used to repave the UEFI variables in the primary region of the memory …)”
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Annapureddy into the teachings of Huang, because it discloses that, “the cryptographic validation process provides that the integrity of the variable records is ensured so that only valid variable records are used to repave the UEFI variables in the primary region of the memory (Annapureddy, Para [0044])”.
Regarding Claim 23. (New) The combination of Huang-Annapureddy discloses the device of claim 21, Huang further discloses, “wherein the controller is further configured to erase the data from the first memory region after that data has been validated using the hash value (Huang, Para [0028, 0035-0036]: … In operation, when a GC process is initiated by GC events 130 based on a set of predefined triggering events, memory 110 is scanned to identify IDs of erasable blocks as well as IDs of valid page(s) within the identified erasable blocks. For example, after determining a valid page, de-dupe 140 identifies whether a duplicated page containing the same or substantially the same content as the valid page in other valid block(s) … pages requiring rewriting are arranged or sorted in a sequential order. The valid pages, compressed valid pages, and/or sequentially ordered valid pages are subsequently rewritten or moved to a new block(s) via module 170. Depending on the applications, sequencer 160 can be inactive. If sequencer 160 is absent or inactive, the compressed valid page generated by compressor 150 is written to a new block. Also, in the event that the duplicated page is not found, and both compressor 150 and sequencer 160 are absent, writer module 170 receives the output from de-dupe 140 and rewrites or copies the valid page in a new block via multiplexer ("mux") 102 before the erasable block is erased. …).”
Regarding Claim 24. (New) The combination of Huang-Annapureddy discloses the device of claim 21, Huang further discloses, “wherein the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of flash memory of the solid state drive (Huang, Para [0003, 0022, 0035], FIG. 1-2: … One embodiment of the present invention discloses an improved process for garbage collection in a non-volatile memory device such as an SSD. For example, after initiating a process of garbage collection in a non-volatile memory such as flash memory according to a predefined set of triggering events, a first valid page within a first block marked as an erasable block is identified. A signature generator generates a first signature representing the content of first valid page. After comparing the first signature with various signatures stored in a signature table, a second valid page in a second block is identified …)”.
Regarding Claim 25. (New) The combination of Huang-Annapureddy discloses the device of claim 21, Huang further discloses, “wherein the hash value of the data is generated while the data is stored in the first memory region (Huang, Para [0035]: … Diagram 200 illustrates an exemplary de-dupe (de-duplication) process which can be initiated during a GC process requiring data to be copied (or moved) from an old data block marked for deletion to a new data block. In order to de-dupe the data, signature generator 250 generates a hash value or signature based on the content of valid page such as page 234 in block 212 which is marked for deletion …).”
Regarding Claim 26. (New) The combination of Huang-Annapureddy discloses the device of claim 25, Huang further discloses, “wherein the hash value of the data is further generated before the data is copied to the second memory region (Huang, Para [0035-0036]: … In order to de-dupe the data, signature generator 250 generates a hash value or signature based on the content of valid page such as page 234 in block 212 which is marked for deletion …)”.
Regarding Claim 27. (New) The combination of Huang-Annapureddy discloses the device of claim 21, Huang further discloses, “wherein the controller is further configured to store the hash value in a cache while the data is copied from the first memory region to the second memory region (Huang, Para [0057]: … ECC encoder/decoder unit 610 is connected to data buffer manager 608 and flash memory interface controller 611 wherein ECC encoder adds error correction code to pages being written into flash memory interface 611. ECC decoder decodes error correction code for pages being read-out of flash memory interface 611. Compressor and de-dupe module 618 is connected to data buffer manager 618 … Data buffer manager 608 buffers valid pages …)”.
Regarding Claim 28. (New) The combination of Huang-Annapureddy discloses the device of claim 21, Huang further discloses, “wherein the validation of the data using the hash value indicates that the data has been successfully copied from the first memory region to the second memory region (Huang, Para [0035-0036], FIG. 2: … Signature table 252 stores multiple signatures indicating valid pages currently in memory 110. If the signature of page 234 matches with one of the entry in signature table 252 as indicated by numeral 258, a duplicated page in a block is identified. Noted that the hash values (or signatures) of pages containing the same data (or content) are the same. If a duplicated data or page such as page 220 is detected, FTL point 206 is updated as indicated by numeral 262 to indicate the LBA of page 234 to address or point to PPA of page 220 as indicated by dash lines 240-242. In the event that no duplication is found, the process proceeds to writer block 260. Writer block 260 copies or rewrites the data or content of page 234 to new page in a new block …).”
Regarding Claim 36. (New) Huang discloses A device (Huang, Para [0023]: … FIG. 1 is a block diagram 100 illustrating a memory device …), comprising:
a plurality of memory regions, including a first memory region, a cache, and a second memory region (Huang, Para [0004, 0023-0024, 0059]: … A flash memory device is typically organized in multiple blocks wherein each block is further divided into a set of pages. In some examples, each page can be further divided into multiple addressable sectors … Diagram 100 illustrates a logic diagram of SSD using a group of flash memory 110 to persistently retain information without power supply. The SSD includes multiple non-volatile memories or flash memory blocks 112-114 … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …); and
a controller (Huang, Para [0023-0024]: … Diagram 100 includes input data 108, memory device 110, output data 128, and memory controller 106 … ) configured to:
generate a hash value of data stored in the first memory region (Huang, Para [0023-0024]: … Diagram 100 includes input data 108, memory device 110, output data 128, and memory controller 106 … );
copy the data from the first memory region to the cache (Huang, Para [0035-0036, 0059], FIG. 8: … During an operation, upon identifying a data block subject to a garbage collection, a list of physical addresses of valid pages within the data block that need to be moved for garbage collection is determined. After applying de-dupe procedure in accordance with the list of valid pages, the valid pages are not rewritten or moved if duplicated pages are found in other blocks. If duplicated pages are not found, the valid pages are rewritten to a new block(s) before erasing the erasable block(s). Note that an erasable block means a block subject to the garbage collection … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …);
begin to copy the data from the cache to the second memory region (Huang, Para [0035-0036, 0059], FIG. 8: … During an operation, upon identifying a data block subject to a garbage collection, a list of physical addresses of valid pages within the data block that need to be moved for garbage collection is determined. After applying de-dupe procedure in accordance with the list of valid pages, the valid pages are not rewritten or moved if duplicated pages are found in other blocks. If duplicated pages are not found, the valid pages are rewritten to a new block(s) before erasing the erasable block(s). Note that an erasable block means a block subject to the garbage collection … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …); and
perform a validation, [while the data is being copied from the cache to the second memory region], of the data using the hash value (Huang, Para [0035-0036, 0057], FIG. 8: … In order to de-dupe the data, signature generator 250 generates a hash value or signature based on the content of valid page such as page 234 in block 212 which is marked for deletion. Note that the signature or hash value is generated over the whole data set within page 234 or content of page 234. After generating a signature for page 234, comparator 256 compares the signature of page 234 with every entries of signature table 252. Signature table 252 stores multiple signatures indicating valid pages currently in memory 110. If the signature of page 234 matches with one of the entry in signature table 252 as indicated by numeral 258, a duplicated page in a block is identified … During an operation, upon identifying a data block subject to a garbage collection, a list of physical addresses of valid pages within the data block that need to be moved for garbage collection is determined. After applying de-dupe procedure in accordance with the list of valid pages, the valid pages are not rewritten or moved if duplicated pages are found in other blocks. If duplicated pages are not found, the valid pages are rewritten to a new block(s) … ).
However, Huang does not explicitly teach, but Annapureddy from same or similar field of endeavor teaches:
“validate, while the data is being copied from the first memory region to the second memory region (Annapureddy, Para [0036, 0044]: … FIG. 5 shows an illustrative fault-tolerant UEFI variable region repaving method 500 that is performed in an FOTA update process with reference to the diagram of the memory 400 shown in FIG. 4. The term “repaving” as used herein means some or all of the UEFI variables in the primary region are replaced by corresponding variables from the firmware update payload 230 (FIG. 2) … some of the methods or steps thereof can occur or be performed concurrently and not all the methods or steps have to be performed in a given implementation depending on the requirements of such implementation and some methods or steps may be optionally utilized. In step 505, the contents of the primary region 405 are copied and written to the spare region 410 using the FTW protocol described above (the spare region is typically erased prior to step 505 being performed) … FIG. 8 shows an illustrative cryptographic process 802 that is exposed on a device (e.g., device 110, 114 in FIG. 1) to validate UEFI variable records in a firmware update payload 230 prior to UEFI variable region repaving, as described above in the text accompanying FIG. 5 … The secure boot manifest 810 itself is trusted by verifying that a hash of the public key 812 used for authentication matches that stored on the OTP fuses 270. The process 802 validates the variable records by verifying that a runtime-calculated hash 815 of the variable records matches the hash contained in the secure boot manifest 810, as indicated by reference numeral 820. Thus, the cryptographic validation process provides that the integrity of the variable records is ensured so that only valid variable records are used to repave the UEFI variables in the primary region of the memory …)”
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Annapureddy into the teachings of Huang, because it discloses that, “the cryptographic validation process provides that the integrity of the variable records is ensured so that only valid variable records are used to repave the UEFI variables in the primary region of the memory (Annapureddy, Para [0044])”.
Regarding Claim 37. (New) The combination of Huang-Annapureddy discloses the device of claim 36, Huang further discloses, “wherein the controller is further configured to determine, based on the validation, that the data was successfully copied from the first memory region to the cache (Huang, Para [0057-0059]: … ECC encoder/decoder unit 610 is connected to data buffer manager 608 and flash memory interface controller 611 wherein ECC encoder adds error correction code to pages being written into flash memory interface 611. ECC decoder decodes error correction code for pages being read-out of flash memory interface 611. Compressor and de-dupe module 618 is connected to data buffer manager 618. Garbage block identifier 620 is connected to FTL management logic 616 and identifies a data block subject to a garbage collection. FTL management logic 616 determines physical addresses of valid pages within the data block that need to be moved for garbage collection. Data buffer manager 608 buffers valid pages. Compressor and de-dupe module 618 compresses the valid pages and applies de-duplication procedure to the valid pages. Note that de-dupe process is also known as deduplication procedure. Command processor 606 moves the valid pages to a new data block while garbage collection manager 614 erases the data block subject to the garbage collection … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …).”
Claims 22 and 29-35 are rejected under 35 U.S.C. 103 as being unpatentable over Pub. No.: US 20150019797 A1 to Huang et al. (hereinafter “Huang”) in view of Pub. No.: US 20180004505 A1 to Annapureddy et al. (hereinafter “Annapureddy”), as applied to claim 21 above, and further in view of Pat. No.: US 9753802 B1 to Shipilov et al. (hereinafter “Shipilov”).
Regarding Claim 22. (New) The combination of Huang-Annapureddy discloses the device of claim 21, however it does not explicitly teach, but Shipilov from same or similar field of endeavor teaches:
“wherein the data is not fully copied into the second memory region until after the data has been validated using the hash value (Shipilov, clo.11,ln.21-37: … embodiments of the present disclosure may also be applicable to transformation of data without migration of the data. For example, where a goal is to compress a data object but retain it in its current data store, a first host may generate a checksum for the compressed data object while a second host may compress the data object. Upon verification of the compressed data object with the checksum, the compressed data object may be stored in the data store to replace the uncompressed data object. Similarly, embodiments of the present disclosure may be utilized for migration without transformation of data. For example, a first host may generate a checksum for a data object while a second host provides the data object and the checksum to a third host. Upon verification of the data object with the checksum, the third host may store the data object at a new storage location, and the data object may be cleaned/deleted from its original storage location …).”
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shipilov into the combined teachings of Huang-Annapureddy, because it discloses that, “The described and suggested techniques improve the field of computing, and specifically the field of data migration, by providing an efficient system for migrating large amounts of data while minimizing data errors (Shipilov, col.4,ln.12-24)”.
Regarding Claim 29. (New) Huang discloses A device (Huang, Para [0023]: … FIG. 1 is a block diagram 100 illustrating a memory device …), comprising:
a plurality of memory regions, including a first memory region and a second memory region (Huang, Para [0004, 0023-0024, 0059]: … A flash memory device is typically organized in multiple blocks wherein each block is further divided into a set of pages. In some examples, each page can be further divided into multiple addressable sectors … Diagram 100 illustrates a logic diagram of SSD using a group of flash memory 110 to persistently retain information without power supply. The SSD includes multiple non-volatile memories or flash memory blocks 112-114 … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …); and
a controller (Huang, Para [0023-0024]: … Diagram 100 includes input data 108, memory device 110, output data 128, and memory controller 106 … ) configured to:
generate a hash value of data stored in the first memory region (Huang, Para [0023-0024, 0027]: … Memory controller 106 further includes GC 132, GC events 130, de-dupe module 140, compressor 150, sequencer 160 … De-dupe module or du-dupe 140, in one embodiment, is capable of identifying a duplicated page in a valid block based on identified valid page in an erasable block. De-dupe module 140 includes a hasher and a signature table. The hasher, also known as signature generator, is able to generate a unique signature through a hashing operation. The hasher hashes the content of valid page to come up with an identifiable unique signature based on the content of page …);
copy the data from the first memory region to the second memory region (Huang, Para [0035-0036, 0059], FIG. 8: … During an operation, upon identifying a data block subject to a garbage collection, a list of physical addresses of valid pages within the data block that need to be moved for garbage collection is determined. After applying de-dupe procedure in accordance with the list of valid pages, the valid pages are not rewritten or moved if duplicated pages are found in other blocks. If duplicated pages are not found, the valid pages are rewritten to a new block(s) before erasing the erasable block(s). Note that an erasable block means a block subject to the garbage collection … Data buffer manager 608 stores the data coming from SSD interface 602 via command processor 606. The data is buffered in data buffer manager 608 before it is written into the flash memory. The data can be read from the flash memory interface and also temporarily stored or buffered in data buffer manager 608 …);
perform a validation, [while the data is being copied from the first memory region to the second memory region], of the data using the hash value (Huang, Para [0035-0036, 0057], FIG. 8: … In order to de-dupe the data, signature generator 250 generates a hash value or signature based on the content of valid page such as page 234 in block 212 which is marked for deletion. Note that the signature or hash value is generated over the whole data set within page 234 or content of page 234. After generating a signature for page 234, comparator 256 compares the signature of page 234 with every entries of signature table 252. Signature table 252 stores multiple signatures indicating valid pages currently in memory 110. If the signature of page 234 matches with one of the entry in signature table 252 as indicated by numeral 258, a duplicated page in a block is identified … During an operation, upon identifying a data block subject to a garbage collection, a list of physical addresses of valid pages within the data block that need to be moved for garbage collection is determined. After applying de-dupe procedure in accordance with the list of valid pages, the valid pages are not rewritten or moved if duplicated pages are found in other blocks. If duplicated pages are not found, the valid pages are rewritten to a new block(s) … ); and
However, Huang does not explicitly teach, but Annapureddy from same or similar field of endeavor teaches:
“validate, while the data is being copied from the first memory region to the second memory region (Annapureddy, Para [0036, 0044]: … FIG. 5 shows an illustrative fault-tolerant UEFI variable region repaving method 500 that is performed in an FOTA update process with reference to the diagram of the memory 400 shown in FIG. 4. The term “repaving” as used herein means some or all of the UEFI variables in the primary region are replaced by corresponding variables from the firmware update payload 230 (FIG. 2) … some of the methods or steps thereof can occur or be performed concurrently and not all the methods or steps have to be performed in a given implementation depending on the requirements of such implementation and some methods or steps may be optionally utilized. In step 505, the contents of the primary region 405 are copied and written to the spare region 410 using the FTW protocol described above (the spare region is typically erased prior to step 505 being performed) … FIG. 8 shows an illustrative cryptographic process 802 that is exposed on a device (e.g., device 110, 114 in FIG. 1) to validate UEFI variable records in a firmware update payload 230 prior to UEFI variable region repaving, as described above in the text accompanying FIG. 5 … The secure boot manifest 810 itself is trusted by verifying that a hash of the public key 812 used for authentication matches that stored on the OTP fuses 270. The process 802 validates the variable records by verifying that a runtime-calculated hash 815 of the variable records matches the hash contained in the secure boot manifest 810, as indicated by reference numeral 820. Thus, the cryptographic validation process provides that the integrity of the variable records is ensured so that only valid variable records are used to repave the UEFI variables in the primary region of the memory …)”
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Annapureddy into the teachings of Huang, because it discloses that, “the cryptographic validation process provides that the integrity of the variable records is ensured so that only valid variable records are used to repave the UEFI variables in the primary region of the memory (Annapureddy, Para [0044])”.
However, the combination of Huang-Annapureddy does not explicitly teach, but Shipilov from same or similar field of endeavor teaches:
“determine, based on the validation, that at least a portion the data already attempted to be copied to the second memory region was not successfully copied from the first memory region to the second memory region (Shipilov, col.5,ln.33-52; col.6.ln.28-38;clo.11,ln.21-37: … Upon receiving the transformation and the set of error detection codes, the third host may verify the transformation using the provided set of error detection codes and a second set of error detection codes that it generated. For example, the third host may be part of a storage service that generates a checksum for all storage operations. If the verification fails, the third host may notify the second host of the verification failure, and remediation actions may be taken, such as attempting to repeat the operations starting at 102 or 106, or performing troubleshooting actions to isolate the cause of the problem. The verification of the transformation may be used to ensure that errors did not occur during the transformation and migration. For example, if the data object was independently corrupted in a transfer to the first or second hosts, if the data object transformation is incorrect due to a memory error, if the error detection code generation is incorrect due to a bit flip, or if a different data object was somehow processed in 104 than 108, the verification should appropriately fail, thereby providing assurance of data integrity during the transformation and migration process … In the present disclosure, the set of queues 210 may serve as a staging area for migration jobs. That is, the migrator 202 may determine which data objects need to be migrated, and, for each data object to be migrated, delivers a message indicating a data storage location in the data storage 204 for the respective data object to the queue 210. In some embodiments, the queues in the set of queues 210 are separate messaging queues of a messaging service. In some of these embodiments, messages may not be removed from the queue until the messaging service has received notification from the requestor that message delivery was successful. … embodiments of the present disclosure may also be applicable to transformation of data without migration of the data. For example, where a goal is to compress a data object but retain it in its current data store, a first host may generate a checksum for the compressed data object while a second host may compress the data object. Upon verification of the compressed data object with the checksum, the compressed data object may be stored in the data store to replace the uncompressed data object. Similarly, embodiments of the present disclosure may be utilized for migration without transformation of data. For example, a first host may generate a checksum for a data object while a second host provides the data object and the checksum to a third host. Upon verification of the data object with the checksum, the third host may store the data object at a new storage location, and the data object may be cleaned/deleted from its original storage location …).”
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shipilov into the combined teachings of Huang-Annapureddy, because it discloses that, “The described and suggested techniques improve the field of computing, and specifically the field of data migration, by providing an efficient system for migrating large amounts of data while minimizing data errors (Shipilov, col.4,ln.12-24)”.
Regarding Claim 30. (New) The combination of Huang-Annapureddy-Shipilov discloses the device of claim 29, Shipilov further discloses, “wherein the controller is further configured to prevent the data from being fully copied from the first memory region to the second memory region based on the determination that the data was not successfully copied from the first memory region to the second memory region (Shipilov, col.20,ln.3-43;col.5.ln.34-53: … such mitigation action could include the host removing itself from the fleet, rebooting itself, throttling itself to perform fewer transactions, notifying a system administrator that the host may have a problem, or, if the host is a virtual machine, cause its virtual machine instance to be terminated … Upon receiving the transformation and the set of error detection codes, the third host may verify the transformation using the provided set of error detection codes and a second set of error detection codes that it generated. For example, the third host may be part of a storage service that generates a checksum for all storage operations. If the verification fails, the third host may notify the second host of the verification failure, and remediation actions may be taken, such as attempting to repeat the operations starting at 102 or 106, or performing troubleshooting actions to isolate the cause of the problem. The verification of the transformation may be used to ensure that errors did not occur during the transformation and migration. For example, if the data object was independently corrupted in a transfer to the first or second hosts, if the data object transformation is incorrect due to a memory error, if the error detection code generation is incorrect due to a bit flip, or if a different data object was somehow processed in 104 than 108, the verification should appropriately fail, thereby providing assurance of data integrity during the transformation and migration process … …)”.
The motivation to further combine Shipilov remains same as in claim 29.
Regarding Claim 31. (New) The combination of Huang-Annapureddy-Shipilov discloses the device of claim 29, Shipilov further discloses, “wherein the controller is further configured to prevent the data from being copied from the second memory region to a third memory region based on the determination that the data was not successfully copied from the first memory region to the second memory region (Shipilov, col.20,ln.3-43: … As illustrated in FIG. 4, the multiple queues 320A-20B described in conjunction with FIG. 3 may be implemented as a single queue. In a similar manner, in some embodiments, the functionality of the unprocessed work queue 522 is implemented in the single queue 20 of FIG. 4 or may be implemented in one of the queues 320A-20B of FIG. 3. For example, a message that has been in the second queue 320B or the single queue 420 beyond a threshold amount of time, or, after a threshold number of retries, has not been indicated as having been successfully delivered and processed, may be considered dead. The dead message in the second queue 320B or the single queue 420 may be processed in a similar manner to the dead messages in the unprocessed work queue 522 described above. In some of these non-exclusive unprocessed work queue embodiments, rather than the queue being audited for dead messages periodically or according to a trigger (such as may be configured to occur with the unprocessed work queue 522), a host may be configured to regulate itself by tracking the number of times it retrieves a message having its own host ID that it has retrieved before. If a count of the number of repeat messages with its own host ID exceeds a threshold, or is greater than a proportion (e.g., above a certain proportion of an average of similar counts by other hosts in the fleet), the host may perform a mitigation actions. As noted, such mitigation action could include the host removing itself from the fleet, rebooting itself, throttling itself to perform fewer transactions, notifying a system administrator that the host may have a problem, or, if the host is a virtual machine, cause its virtual machine instance to be terminated. Additionally or alternatively, in some implementations, when the second host 418B retrieves the second message 408B, it appends its own host ID as a second host ID and/or may update and append a counter to the second message 418B and push the appended second message to the single queue 420 (also notifying the single queue 420 to delete the unappended second message 418B). In this manner, a host that retrieves a message that includes its host ID as a first host ID can determine the identity of other hosts that have attempted to process the message and/or the number of times processing of the message has been attempted …)”.
The motivation to further combine Shipilov remains same as in claim 29.
Regarding Claim 32. (New) The combination of Huang-Annapureddy-Shipilov discloses the device of claim 29, Shipilov further discloses, “wherein the controller is further configured to, based on the determination that the data was not successfully copied, abort any movement or copying of the data from the first memory region or the second memory region (Shipilov, col.20,ln.3-43; col5,ln.34-53; col19,ln.36-45: … As illustrated in FIG. 4, the multiple queues 320A-20B described in conjunction with FIG. 3 may be implemented as a single queue. In a similar manner, in some embodiments, the functionality of the unprocessed work queue 522 is implemented in the single queue 20 of FIG. 4 or may be implemented in one of the queues 320A-20B of FIG. 3. For example, a message that has been in the second queue 320B or the single queue 420 beyond a threshold amount of time, or, after a threshold number of retries, has not been indicated as having been successfully delivered and processed, may be considered dead. The dead message in the second queue 320B or the single queue 420 may be processed in a similar manner to the dead messages in the unprocessed work queue 522 described above. In some of these non-exclusive unprocessed work queue embodiments, rather than the queue being audited for dead messages periodically or according to a trigger (such as may be configured to occur with the unprocessed work queue 522), a host may be configured to regulate itself by tracking the number of times it retrieves a message having its own host ID that it has retrieved before. If a count of the number of repeat messages with its own host ID exceeds a threshold, or is greater than a proportion (e.g., above a certain proportion of an average of similar counts by other hosts in the fleet), the host may perform a mitigation actions. As noted, such mitigation action could include the host removing itself from the fleet, rebooting itself, throttling itself to perform fewer transactions, notifying a system administrator that the host may have a problem, or, if the host is a virtual machine, cause its virtual machine instance to be terminated. Additionally or alternatively, in some implementations, when the second host 418B retrieves the second message 408B, it appends its own host ID as a second host ID and/or may update and append a counter to the second message 418B and push the appended second message to the single queue 420 (also notifying the single queue 420 to delete the unappended second message 418B). In this manner, a host that retrieves a message that includes its host ID as a first host ID can determine the identity of other hosts that have attempted to process the message and/or the number of times processing of the message has been attempted …)”.
The motivation to further combine Shipilov remains same as in claim 29.
Regarding Claim 33. (New) The combination of Huang-Annapureddy-Shipilov discloses the device of claim 29, Shipilov further discloses, “wherein the controller is further configured to, based on the determination that the data was not successfully copied, generate an alert that the data was not successfully copied from the first memory region or the second memory region (Shipilov, col.5,ln.34-53: … Upon receiving the transformation and the set of error detection codes, the third host may verify the transformation using the provided set of error detection codes and a second set of error detection codes that it generated. For example, the third host may be part of a storage service that generates a checksum for all storage operations. If the verification fails, the third host may notify the second host of the verification failure, and remediation actions may be taken, such as attempting to repeat the operations starting at 102 or 106, or performing troubleshooting actions to isolate the cause of the problem. The verification of the transformation may be used to ensure that errors did not occur during the transformation and migration. For example, if the data object was independently corrupted in a transfer to the first or second hosts, if the data object transformation is incorrect due to a memory error, if the error detection code generation is incorrect due to a bit flip, or if a different data object was somehow processed in 104 than 108, the verification should appropriately fail, thereby providing assurance of data integrity during the transformation and migration process …)”.
The motivation to further combine Shipilov remains same as in claim 29.
Regarding Claim 34. (New) The combination of Huang-Annapureddy-Shipilov discloses the device of claim 29, Shipilov further discloses, “wherein the controller is further configured to, based on the determination that the data was not successfully copied, restart the copying of the data from the first memory region or the second memory region (Shipilov, col.5,ln.34-53: … Upon receiving the transformation and the set of error detection codes, the third host may verify the transformation using the provided set of error detection codes and a second set of error detection codes that it generated. For example, the third host may be part of a storage service that generates a checksum for all storage operations. If the verification fails, the third host may notify the second host of the verification failure, and remediation actions may be taken, such as attempting to repeat the operations starting at 102 or 106, or performing troubleshooting actions to isolate the cause of the problem. The verification of the transformation may be used to ensure that errors did not occur during the transformation and migration. For example, if the data object was independently corrupted in a transfer to the first or second hosts, if the data object transformation is incorrect due to a memory error, if the error detection code generation is incorrect due to a bit flip, or if a different data object was somehow processed in 104 than 108, the verification should appropriately fail, thereby providing assurance of data integrity during the transformation and migration process)”.
The motivation to further combine Shipilov remains same as in claim 29.
Regarding Claim 35. (New) The combination of Huang-Annapureddy-Shipilov discloses the device of claim 29, Huang further discloses, “wherein the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of flash memory of the solid state drive (Huang, Para [0024]: … Diagram 100 illustrates a logic diagram of SSD using a group of flash memory 110 to persistently retain information without power supply. The SSD includes multiple non-volatile memories or flash memory blocks 112-114, FTL 104, and memory controller 106 which further includes GC 132, GC events 130, and de-dupe module 140. Non-volatile memory blocks 112-114 are configured by a group of flash memory blocks wherein each of blocks includes a set of pages. In one example, a block can contain from 128 to 512 pages. Note that a flash memory page is a minimal writable unit …)”.
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Pub. No.: US 20150019797 A1 to Huang et al. (hereinafter “Huang”) in view of Pub. No.: US 20180004505 A1 to Annapureddy et al. (hereinafter “Annapureddy”), and further in view of Pat. No.: US 10733105 B1 to Visvanathan et al. (hereinafter “Visvanathan”).
Regarding Claim 40. (New) The combination of Huang-Annapureddy discloses the device of claim 36, however it does not explicitly teach, but Visvanathan from same or similar field of endeavor teaches:
“wherein the controller is further configured to determine, based on the validation, that the data was not successfully copied from the first memory region to the cache (Visvanathan, col16,ln.17-41: … FIG. 12 is a block diagram illustrating a storage system according to another embodiment of the invention. Storage system 1200 may be implemented as part of storage system 104 of FIG. 1. SSD data cache 119 reserves a block for a descriptive data block (DDB) 1204 to keep track of invalid blocks of WEUs or of entire WEUs of SSD data cache 119. A block of WEU may be invalid for any number of reasons, such as checksum failure, corruption, or disk failure. For example, an operating system event may trigger a disk failure event when a SSD device of SSD data cache 119 fails. A system event such as a disk failure triggers a subroutine to invalidate the affected SSD data blocks. The invalidation is recorded by validation module 1210 in DDB 1204 such that subsequent access to the invalid blocks of SSD data cache 119 will return a read failure. SSD data cache may include a number of devices such as SSD devices 1205-1206. Each of the SSD devices 1205-1206 reserves a descriptive data block such that DDB 1211-1212 is a mirror image of DDB 1204. In other words, DDB 1204 is an abstraction of DDB 1211-1212. Upon a disk failure, DDB 1204 may be recovered from any of DDB 1211-1212. In one embodiment, a copy of DDB 1204 resides on memory (not shown) such that content store 115 can determine invalid blocks in-memory without having to access SSD data cache 119 …).”
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Visvanathan into the combined teachings of Huang-Annapureddy, because it discloses that, “data requested by a higher file system layer (such as NFS) is in the form of block requests, which are converted to extent requests in the cache, while data being written in cache 119 is in a form of a WEU. A WEU, such as WEU 341, includes multiple extents, each of which is compressed therein where each extent can be independently read and accessed to satisfy read requests from the higher layers of the file system. The size of a WEU may be configured to match an erasure unit size of cache 119, which depends upon the specification or characteristics of cache 119. As a result, the lifespan of the cache 119 can be improved (Visvanathan, col.8,ln.10-17)”.
Allowable Subject Matter
Claims 38-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner further notes that, should Applicant amend claims as directed above, contents of claims 38-39 be included in all the independent claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Applicant’s response must address all the objections and rejections noted in this office action.
Reasons for allowance will be furnished upon allowance.
Pertinent Prior Arts
The following prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
US 20110040732 A1; Anglin et al.: Anglin discloses techniques for securing the use of data deduplication activities occurring in a source-deduplicating storage management system. These techniques are intended to prevent fake data backup, target data contamination, and data spoofing attacks initiated by a source. In one embodiment, one technique includes limiting chunk querying to authorized users. Another technique provides detection of attacks and unauthorized access to keys within the target system. Additional techniques include the combination of validating the existence of data from the source by validating the data chunk, validating a data sample of the data chunk, or validating a hash value of the data chunk. A further embodiment involves the use of policies to provide authorization levels for chunk sharing and linking within the target. These techniques separately and in combination provide a comprehensive strategy to avoid unauthorized access to data within the target storage system.
The present invention generally relates to data storage activities occurring within a storage management system. The present invention more specifically relates to techniques and operations used to enhance security within a deduplicating storage management environment.
US 20180089037 A1; Liu et al.: Liu discloses a computer-implemented method for healing images in deduplication storage may include (i) detecting that a data segment stored within deduplication storage is corrupted by executing an algorithm on the data segment to generate a numerical identifier for the data segment and determining that the numerical identifier does not match a previously stored numerical identifier for the data segment, (ii) checking, during a backup operation, whether a digital fingerprint of a data segment of an image being backed up matches a digital fingerprint of the corrupted data segment that was taken prior to corruption and that is already stored within the deduplication storage, and (iii) appending the data segment from the image being backed up to a container that already contains the corrupted data segment rather than replacing the corrupted data segment. Various other methods, systems, and computer-readable media are also disclosed.
US 20120221784 A1; Ban; Amir: Ban discloses A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.
The present invention relates to a memory controller and methods for enhancing write performance of a flash device and, more particularly, to a flash memory controller and methods for enhancing write performance by reducing write amplification of a flash memory device.
US 20200133720 A1; Chinthekindi et al.: Chinthekindi discloses a method for validating data integrity of a seeding process is described. The seeding process for migrating data from a source tier to a target tier persists a perfect hash vector (PHV) to a disk when the seeding process is suspended for various reasons. The PHV includes bits for fingerprints for data segments corresponding to the data, and can be reloaded into memory upon resumption of the seeding process. One or more bits corresponding to fingerprints for copied data segments are reset prior to starting the copy phase in the resumed run. A checksum of the PHV is calculated after the seeding process completes copying data segments in the containers. A non-zero checksum of the PHV indicates that one or more data segments are missing on the source tier or the data segments are not successfully copied to the target tier. The missing data segments and/or one or more related files are reported to a user via a user interface.
Embodiments of the present invention relate generally to data storage systems. More particularly, embodiments of the invention relate to systems and method for checking file data integrity and reporting inconsistencies with data migration from one tier to another.
US 10204042 B2; Bennett; Jon C. R.: Bennett discloses Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.
US 9697217 B1; Salyers et al.: Salyers discloses Methods and apparatus for secure data modification using segmented hashing. An intermediate device on a data path between a storage service and a client receives a modification request for a data segment of a data chunk of a storage object. The device generates a new chunk hash value for the chunk based on an original chunk hash value of the chunk, an original segment hash value of the segment to be modified, and a new segment hash value computed based on the modification. The device generates a modified version of the chunk based on the modification request, and uploads the modified version and the new chunk hash value to the storage service.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAHABUB S AHMED whose telephone number is (571)272-0364. The examiner can normally be reached on 9AM-5PM EST M-F.
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/MAHABUB S AHMED/Examiner, Art Unit 2434
/TESHOME HAILU/Primary Examiner, Art Unit 2434
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