Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (Fig. 4) in the reply filed on 12/16/2025 is acknowledged.
Applicant’s election of Species 1 (Fig. 4, Claims 1-10, 12-14, 17-20 in the reply filed on 12/16/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11, 15, 16 are withdrawn from consideration based on Applicant’s election.
Claims 12-14 are further withdrawn from consideration. Claims 12 and 14 recite the limitation, “a fifth amplifier including a first input terminal to which a voltage corresponding to an average of the first voltage and a second target voltage is applied, a second input terminal, and an output terminal configured to output the second voltage”. In view of the originally filed specification, the average of the first voltage and a second target voltage regards the embodiment in Fig. 6, which is a non-elected species. There is no disclosure of average in relation to the embodiments in Figs. 4 and 5.
Claim 13 depends on claim 11, which is a non-elected claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-6, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (PGPUB 2021/0174742 A1) in view of Park (PGPUB 2017/0039955 A1).
As to claim 1, Hwang (Figs. 3-5) teaches, an adaptive voltage control (AVC) circuit (power manager 40)(¶ 76) comprising:
a voltage application circuit (voltage change sensor 42, third amplifier AMP3 with resistors Rf3, R6 and R7, and first supply voltage generator 41) configured to apply a first voltage (first reference feedback voltage Vreffb1) or a second voltage (voltage difference V_bias) to a voltage output circuit (first supply voltage compensator 44 in Figs. 4 and 5 and fourth amplifier AMP4 with resistors R9, R10 and Rf4)(¶ 78), and
the voltage output circuit configured to generate a third voltage (first supply voltage VSS) based on the first or second voltage and a target voltage (reference voltage Vref may be a target voltage, ¶ 87), and to apply the third voltage to a display panel (pixel area 50)(¶ 72).
Hwang does not specifically teach wherein the first voltage is generated by dividing a panel driving voltage.
Park (Fig. 7B) teaches, wherein the first voltage (setting voltage Voffset) is generated by dividing a panel driving voltage (voltage output by AMP3 - i.e. resistor string voltage-dividing the derivative voltage output by AMP3 of local driving voltage ELVSS_FB and variable driving voltage ELVSS_var as shown in Fig. 7B).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s initialization voltage into Hwang’s power supply generator. Park’s and Hwang’s power generators share similar structures utilizing resistors, amplifiers for generating power signals to drive the display device and utilizing feedback ELVSS voltage (VSS) to generate the power signals. The combination would have been obvious, so as to provide initialization voltage to improve emission response of the pixels (¶ 44).
As to claim 4, Hwang teaches, the panel driving voltage (i.e. first supply voltage VSS_fb, which is a sensed version of low power voltage)(¶ 52) is applied to a cathode electrode (i.e. lower terminal of EL) of the light-emitting element (Fig. 2).
Hwang does not specifically teach the third voltage to an anode electrode.
Park (Figs. 2, 7A) teaches, wherein the voltage output circuit (voltage generator 310, voltage adder 320 and first selector 430) is configured to apply the third voltage (initialization voltage Vinit) to an anode electrode (i.e. upper terminal of EL at node N3) of a light-emitting element (emission element EL) included in the display panel (Fig. 2).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s initialization voltage into Hwang’s power supply generator. Park’s and Hwang’s power generators share similar structures utilizing resistors, amplifiers for generating power signals to drive the display device and utilizing feedback ELVSS voltage (VSS) to generate the power signals. The combination would have been obvious, so as to provide initialization voltage to improve emission response of the pixels (¶ 44).
As to claim 5, Hwang teaches the AVC circuit of claim 1 but does not specifically teach a voltage range.
Park (Fig. 7B) teaches, wherein the first voltage (Vref2), the second voltage (Vref1), and the third voltage (Vinit) fall within a first voltage range (i.e. voltage range of GND to 1V. Vref2 may be 1V, ¶ 85) corresponding to an operating range of the AVC circuit (¶ 85), and
wherein the panel driving voltage (Vref) falls within a second voltage range (GND to 3.7V) that is outside the first voltage range (¶ 56).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s initialization voltage into Hwang’s power supply generator. Park’s and Hwang’s power generators share similar structures utilizing resistors, amplifiers for generating power signals to drive the display device and utilizing feedback ELVSS voltage (VSS) to generate the power signals. The combination would have been obvious, so as to provide initialization voltage to improve emission response of the pixels (¶ 44).
As to claim 6, Hwang teaches the AVC circuit of claim 1 but does not specifically teach a first multiplexer.
Park (Fig. 7A) teaches, wherein the voltage application circuit includes a first multiplexer (second selector 740) including a first input terminal (i.e. 0 terminal) to which the first voltage (ELVSS_var) is applied, a second input terminal (i.e. 1 terminal) to which the second voltage (ELVSS_FB) is applied, and an output terminal (i.e. output terminal of selector that connects to + terminal of BUF2).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s initialization voltage generator 160 into Hwang’s power manager 40, so as to provide initialization voltage to improve emission response of the pixels (¶ 44).
As to claim 17, Hwang (Figs. 3-5) teaches, a control method of an adaptive voltage control (AVC) circuit (power manager 40)(¶76), the control method comprising:
identifying a driving mode (i.e. one mode generating Vreffb based on first offset voltage V_offset1, and another mode generating based on second offset V_offset2) of the AVC circuit (¶ 77); and
controlling the AVC circuit to apply a third voltage (first supply voltage VSS) to a display panel (i.e. display panel with pixel area 50) based on the driving mode (¶ 71),
wherein the AVC circuit includes:
a voltage application circuit (voltage change sensor 42, third amplifier AMP3 with resistors Rf3, R6 and R7, and first supply voltage generator 41) configured to apply a first voltage (first reference feedback voltage Vreffb1) or a second voltage (voltage difference V_bias) to a voltage output circuit (first supply voltage compensator 44 in Figs. 4 and 5 and fourth amplifier AMP4 with resistors R9, R10 and Rf4)(¶ 78) based on the driving mode (i.e. Vreffb based on Voffset1 or Voffset2); and
the voltage output circuit configured to generate the third voltage (first supply voltage VSS) based on the first or second voltage and a target voltage (reference voltage Vref may be a target voltage, ¶ 87), and to apply the third voltage to a display panel (pixel area 50)(¶ 72).
Hwang does not specifically teach wherein the first voltage is generated by dividing a panel driving voltage.
Park (Fig. 7B) teaches, wherein the first voltage (setting voltage Voffset) is generated by dividing a panel driving voltage (i.e. resistor string voltage-dividing the derivative voltage of local driving voltage ELVSS_FB and variable driving voltage ELVSS_var as shown in Fig. 7B).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s initialization voltage into Hwang’s power supply generator. Park’s and Hwang’s power generators share similar structures utilizing resistors, amplifiers for generating power signals to drive the display device and utilizing feedback ELVSS voltage (VSS) to generate the power signals. The combination would have been obvious, so as to provide initialization voltage to improve emission response of the pixels (¶ 44).
As to claim 20, Hwang (Figs. 3-5) teaches, a display device (display device 100) comprising:
a power management integrated circuit (PMIC) (power manager 40) configured to generate a panel driving voltage (first supply voltage VSS)(¶ 49);
a display driving circuit (timing controller 10, data driver 20, scan driver 30, and power manager 40) including an adaptive voltage control (AVC) circuit (power manager 40)(Fig. 2); and
a display panel (i.e. display panel for pixel area 50)(¶ 68, Fig. 1),
wherein the AVC circuit includes:
a voltage application circuit (voltage change sensor 42, third amplifier AMP3 with resistors Rf3, R6 and R7, and first supply voltage generator 41) configured to apply a first voltage (first reference feedback voltage Vreffb1) or a second voltage (voltage difference V_bias) to a voltage output circuit (first supply voltage compensator 44 in Figs. 4 and 5 and fourth amplifier AMP4 with resistors R9, R10 and Rf4)(¶ 78), and
the voltage output circuit configured to generate the third voltage (first supply voltage VSS) based on the first or second voltage and a target voltage (reference voltage Vref may be a target voltage, ¶ 87), and to apply the third voltage to a display panel (pixel area 50)(¶ 72).
Hwang does not specifically teach wherein the first voltage is generated by dividing a panel driving voltage.
Park (Fig. 7B) teaches, wherein the first voltage (setting voltage Voffset) is generated by dividing a panel driving voltage (i.e. resistor string voltage-dividing the derivative voltage of local driving voltage ELVSS_FB and variable driving voltage ELVSS_var as shown in Fig. 7B).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s initialization voltage into Hwang’s power supply generator. Park’s and Hwang’s power generators share similar structures utilizing resistors, amplifiers for generating power signals to drive the display device and utilizing feedback ELVSS voltage (VSS) to generate the power signals. The combination would have been obvious, so as to provide initialization voltage to improve emission response of the pixels (¶ 44).
Allowable Subject Matter
Claims 2, 7 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3, 8-10, and 19 are objected as being dependent on claims 2, 7 and 18.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2 and 18 recite the limitation, “the voltage application circuit is configured to, apply the first voltage to the voltage output circuit when the AVC circuit operates in a first mode to perform adaptive voltage control and, apply the second voltage to the voltage output circuit when the AVC circuit operates in a second mode in which the adaptive voltage control is not performed, and
wherein the voltage output circuit is configured to generate a third-first voltage, which includes the panel driving voltage and a predetermined variation, when the first voltage is received and, generate a third-second voltage based on the second voltage and a first-second target voltage of the second mode, when the second voltage is received”.
Claims 2 and 18 recite the limitation specifying the condition of the first mode and the second mode. The claim limitation specifically recite that the first mode is for applying a first voltage that leads to third-first voltage output, which includes the panel driving voltage and a predetermined variation. Further, the second mode is for applying a second voltage that leads to third-second voltage output, which is based on the second voltage and target voltage of the second mode. Examiner conducted a search but could not find the prior arts that would teach these limitations.
Claim 7 recites the limitation, “a first amplifier including a first input terminal to which the first voltage or the second voltage is applied from the voltage application circuit, a second input terminal, and an output terminal configured to output the third voltage; a first resistor connected between the output terminal of the first amplifier and the second input terminal of the first amplifier; a second resistor connected between the first resistor and an output terminal of a second amplifier; the second amplifier including a first input terminal to which a first reference voltage is applied, a second input terminal, and the output terminal configured to output a first target voltage; a third resistor connected between the output terminal of the second amplifier and the second input terminal of the second amplifier; and a fourth resistor connected between the second input terminal of the second amplifier and a ground terminal”. Claim 7 recites the connection between two sets of operational amplifiers and further recites each operational amplifier is connected to two corresponding resistors with specific connections. Particularly, the limitation reciting, “the fourth resistor connected between the second input terminal of the second amplifier and a ground terminal” while requiring all of the other limitations of claims 1 and 7 would distinguish from the prior art. Examiner conducted a search to find the prior arts that would teach these limitations but could not find them.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623
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