DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the requirement of restriction/election mailed on 4/20/2026, applicant has elected claims 1-7 for further examination without traverse, thus, claims 8-12 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawashimo et al. (USP 7,319,575).
Regarding claim 1, Kawashimo et al.’s figure 4 shows a circuit, configured to: detect a change in a voltage provided at a first terminal of the circuit (VDD by means of VG_n)) while providing an output signal having a first logical state (output of the Buf); and responsive to the change in the voltage exceeding a threshold rate of change and the voltage (ND1) having a value sufficient to cause the output signal to have a second logical state (transistor MN1 on), hold the output signal at the first logical state as called for in claim 1.
Regarding claim 2, wherein the first logical state is a logical high state and the second logical state is a logical low state, and wherein the circuit is configured to: detect a decrease in value of the voltage provided at the first terminal of the circuit (by VG_p); and responsive to the decrease in voltage exceeding the threshold rate of change and the voltage having a value sufficient to cause the output signal to have a logical low value, holding the output signal at a logical high value.
Regarding claim 5, wherein the first logical state is a logical low state and the second logical state is a logical high state, and wherein the circuit is configured to: detect an increase in value of the voltage provided at the first terminal of the circuit (by means of VG_p); and responsive to the increase in voltage exceeding the threshold rate of change and the voltage having a value sufficient to cause the output signal to have a logical high value, holding the output signal at a logical low value as called for in claim 5.
Claim(s) 1-2 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Verhaeghe et al. (USP 5,479,132).
Regarding claim 1, Verhaeghe et al.’s figure 4a shows a circuit, configured to: detect a change in a voltage provided at a first terminal of the circuit (Vin by means of 38, 41) while providing an output signal having a first logical state (output of the buffer 48); and responsive to the change in the voltage exceeding a threshold rate of change and the voltage (schmin) having a value sufficient to cause the output signal to have a second logical state (output of the buffer 48), hold the output signal at the first logical state as called for in claim 1.
Regarding claim 2, wherein the first logical state is a logical high state and the second logical state is a logical low state, and wherein the circuit is configured to: detect a decrease in value of the voltage provided at the first terminal of the circuit (by 38, 40); and responsive to the decrease in voltage exceeding the threshold rate of change (Schmin) and the voltage having a value sufficient to cause the output signal to have a logical low value, holding the output signal at a logical high value.
Regarding claim 5, wherein the first logical state is a logical low state and the second logical state is a logical high state, and wherein the circuit is configured to: detect an increase in value of the voltage provided at the first terminal of the circuit (by means of 38 and 40); and responsive to the increase in voltage exceeding the threshold rate of change and the voltage having a value sufficient to cause the output signal to have a logical high value, holding the output signal at a logical low value as called for in claim 5.
Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Japanese patent (JP 57-192110).
Regarding claim 1, JP-110’s figure 1 shows a circuit, configured to: detect a change in a voltage provided at a first terminal of the circuit (Vcc+ when switch SW is closed by means of R1, C1) while providing an output signal having a first logical state (output of the Amp2); and responsive to the change in the voltage exceeding a threshold rate of change and the voltage (voltage at the junction of R1 and C1) having a value sufficient to cause the output signal to have a second logical state (output of the Amp2), hold the output signal at the first logical state as called for in claim 1.
Regarding claim 5, wherein the first logical state is a logical low state and the second logical state is a logical high state, and wherein the circuit is configured to: detect an increase in value of the voltage provided at the first terminal of the circuit (by means of R1, C1); and responsive to the increase in voltage exceeding the threshold rate of change and the voltage having a value sufficient to cause the output signal to have a logical high value, holding the output signal at a logical low value as called for in claim 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Japanese patent (JP 57-192110) in view of Verhaeghe et al. (USP 5,479,132).
Regarding claim 2, JP110’s reference discloses a circuit comprising all the aspects of the present invention as noted above except JP110’s circuit is detecting an increase in value of the voltage at the first terminal of the circuit (Vcc+ by means of R1, C1) instead of being detecting a decrease in value of the voltage at the first terminal of the circuit (Vcc+) as called for in claim 2.
Verhaeghe et al.’s figure 4 shows a circuit that is capable of removing both positive and negative spike. Thus, one skilled in the art would have recognized to incorporated another detector for detecting a decrease in value of the voltage at the first terminal of the circuit (Vcc+) in JP110’s circuit arrangement. This provides a flexible of removing glitches on both positive spike and negative spike. Thus, outside of any non-obvious results, the obviousness of including a decrease spike detector will not be patentable under 35USC 103.
Allowable Subject Matter
Claims 3-4 and 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Kawashimo et al.’s figure 4 shows a circuit, configured to: detect a change in a voltage provided at a first terminal of the circuit (VDD by means of VG_n)) while providing an output signal having a first logical state (output of the Buf); and responsive to the change in the voltage exceeding a threshold rate of change and the voltage (ND1) having a value sufficient to cause the output signal to have a second logical state (transistor MN1 on), hold the output signal at the first logical state. However, Kawashimo et al. reference fails to teach or fairly suggest to detect a decrease in value of a second voltage provided at a second terminal of the circuit while providing a second output signal having a logical high state; and responsive to the decrease in second voltage exceeding a second threshold rate of change, the decrease in voltage exceeding the threshold rate of change, and the second voltage having a value sufficient to cause the second output signal to have a logical low value, holding the second output signal at a logical high value as called for in claim 3; to detect an increase in value of a second voltage provided at a second terminal of the circuit while providing a second output signal having a logical low state; and responsive to the increase in second voltage exceeding a second threshold rate of change, the increase in voltage exceeding the threshold rate of change, and the second voltage having a value causing the second output signal to have a logical high value, holding the second output signal at a logical low value as called in claim 6.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2836 7/28/2026
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