DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-5, 12-14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ware et al. (US 2012/0011331), “Ware”, in view of Nale (US 2019/0066808).
2. As per claim 1, Ware discloses a memory cell array comprising a set of memory cell rows, each memory cell row of the set of memory cell rows comprising a set of memory cells [a plurality of memory banks comprising a set of rows (inherently comprising a set of memory cells), figure 5]; and a row hammer management circuit configured to: receive, from an external memory controller [Memory Controller 102, figure 8], a precharge command at a second time point in response to an active command of a target memory cell row of the set of memory cell rows received at a first time point [an activate command 304 followed by a precharge command 306, figure 3].
Ware does not disclose expressly update an active count associated with the target memory cell row (based on the precharge command, figure 3, Ware), wherein the active count is associated with a number of times that the target memory cell row of the set of memory cell rows has been accessed by the active command.
Nale discloses update an active count associated with the target memory cell row [counting activations of each of the rows, abstract] (based on the precharge command, figure 3, Ware), wherein the active count is associated with a number of times that the target memory cell row of the set of memory cell rows has been accessed by the active command [such row activation count associated with write/read accesses, figure 4].
Ware and Nale are analogous art because they are from the same field of endeavor of memory cell management.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Ware by including the activation count system as taught by Nale in the abstract.
The motivation for doing so would have been to mitigate data corruption as expressly taught by Nale in paragraph 2.
3. As per claim 2, the cited prior arts disclose wherein the active count is stored in at least one count cell [“the reserved storage cells”, abstract, Nale] associated with the target memory cell row.
4. As per claim 3, the cited prior arts disclose wherein, to update the active count, the row hammer management circuit is configured to: read the active count from the at least one count cell [counting activations of each of the rows, abstract, Nale]; generate an updated active count based on the active count read from the at least one count cell; and write the updated active count in a respective ones of the count cells of the target memory cell row [writing the count value in “the reserved storage cells”, abstract, Nale].
5. As per claim 4, the cited prior arts disclose wherein the active command is associated with a first command designating a memory operation on the target memory cell row, wherein the first command is applied subsequent to the active command [memory access command, paragraph 12, Nale]; and wherein the semiconductor memory device comprising a control logic circuit configured to: perform the memory operation on the target memory cell row based on the first command and control the row hammer management circuit [row hammer control operation(s), figure 3, Nale].
6. As per claim 5, the cited prior arts disclose wherein the row hammer management circuit is configured to activate a precharge signal at a third time point based on the precharge command received at the second time point, and wherein the control logic circuit is configured to precharge the target memory cell row in response to the precharge signal [precharging memory bank 306, figure 3, Ware].
7. As per claims 12-14, the examiner directs the applicant’s attention to claim rejections above.
8. As per claim 20, Ware discloses a semiconductor memory device [Memory Device 104, figure 1]; and a memory controller configured to control the semiconductor memory device [Memory Controller 102, figure 1], wherein the semiconductor memory device comprises: a memory cell array comprising a set of memory cell rows, each memory cell row of the set of memory cell rows comprising a set of memory cells [a plurality of memory banks comprising a set of rows (inherently comprising a set of memory cells), figure 5]; and a row hammer management circuit configured to: receive, from an external memory controller [Memory Controller 102, figure 8], a precharge command at a second time point in response to an active command of a target memory cell row of the set of memory cell rows received at a first time point [an activate command 304 followed by a precharge command 306, figure 3].
Ware does not disclose expressly update an active count associated with the target memory cell row (based on the precharge command, figure 3, Ware), wherein the active count is associated with a number of times that the target memory cell row of the set of memory cell rows has been accessed by the active command.
Nale discloses update an active count associated with the target memory cell row [counting activations of each of the rows, abstract] (based on the precharge command, figure 3, Ware), wherein the active count is associated with a number of times that the target memory cell row of the set of memory cell rows has been accessed by the active command [such row activation count associated with write/read accesses, figure 4].
Ware and Nale are analogous art because they are from the same field of endeavor of memory cell management.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Ware by including the activation count system as taught by Nale in the abstract.
The motivation for doing so would have been to mitigate data corruption as expressly taught by Nale in paragraph 2.
Conclusion
A. Allowable Subject Matter
Claims 6-11 and 15-19 are objected to.
The closest prior art of record, “Ware” discloses activating and precharging memory cells in figure 3.
The primary reasons for allowance of claim 6 in the instant application is the combination with the inclusion in these claims that “wherein the row hammer management circuit is configured to update the active count by performing an internal read-update-write operation between the second time point and the third time point”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 7 in the instant application is the combination with the inclusion in these claims that “a timing control circuit configured to: generate command signals for controlling the row hammer management circuit based on at least one of the precharge command or the first command; and adaptively adjust a number of clock signals corresponding to an activation interval of an active count update signal among command signals based on a frequency of the clock signals from the external memory controller, the row hammer management circuit is configured to initiate the updating of the active count based on the active count update signal”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 15 in the instant application is the combination with the inclusion in these claims that “updating, by the row hammer management circuit, the active count by performing an internal read-update-write operation between the second time point and the third time point”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 16 in the instant application is the combination with the inclusion in these claims that “generating command signals for controlling the row hammer management circuit based on at least one of the precharge command or the first command; adaptively adjust a number of clock signals corresponding to an activation interval of an active count update signal among command signals based on a frequency of the clock signals from the external memory controller; and initiating, by the row hammer management circuit, the updating of the active count based on the active count update signal”. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP.
B. Claims Rejected
Claims 1-5, 12-14, and 20 are rejected.
C. Direction for Future Remarks
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAE U YU/Primary Examiner, Art Unit 2138
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