Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/27/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 17-25 & 27-30 are objected to because of the following informalities:
Claims 17 – 25, line 1 should recite --[[A]]The method according to claim…--.
Claims 27 – 30, line 1 should recite --[[A]]The circuit according to claim…--.
Claim 19 is objected to because the recitation “wherein the working voltage range defines the range in which the system’s function is guaranteed” contains terminology inconsistent with the earlier recitation of “the operating voltage range.” Correction is required. It is suggested that “wherein the working voltage range defines the range in which the system’s function is guaranteed” be amended to read “wherein the operating voltage range defines the range in which the system’s function is guaranteed.”
Claim 20 is objected to because the recitation “the operating voltage range” lacks explicit antecedent basis in claim 16. Correction is required. It is suggested that “the operating voltage range” be amended to read “an operating voltage range.”
Claim 23 is objected to because the recitation “the supply voltage” lacks antecedent basis in claim 16. Correction is required. It is suggested that “the supply voltage” be amended to read “a supply voltage.”
Claim 25 is objected to because the recitation “the second voltage source” lacks antecedent basis in claim 16. Correction is required. It is suggested that “the second voltage source” be amended to read “a second voltage source.”
Claim 29 is objected to because the recitation “the second voltage source” lacks antecedent basis in claim 26. Correction is required. It is suggested that “the second voltage source” be amended to read “a second voltage source.”
Claim 30 is objected to because the recitation “the protective device against feedback” lacks antecedent basis in claim 26. Correction is required. It is suggested that “the protective device against feedback” be amended to read “a protective device against feedback.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-19 & 21-28 & 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sawano (US 2023/0155367 A1) in view of Bisanz et al. (US 2024/0410944 A1).
Regarding claim 16, Sawano discloses Method for checking the functionality of the voltage monitoring of a circuit, comprising the following steps (see paragraph [0054], explaining that microcomputer 27 tests the notification function of drive circuit 23): a computing unit sends a test signal to a first voltage source, which causes a change in the voltage of the voltage source (see paragraph [0053], explaining that microcomputer 27 instructs application circuit 26 to apply a voltage greater than or equal to the reference voltage); a comparison unit compares the voltage at the output of the voltage source with a reference voltage and sends a shutdown signal to a switch if the voltage at the output of the voltage source is outside a tolerance range (see paragraph [0071], explaining that comparator 51 changes its output when the monitored voltage reaches reference voltage Vr and drive unit 50 switches FET 20 off); and the switch interrupts the flow of current upon receipt of a shutdown signal, causing the voltage after the switch to drop (see paragraph [0036], expressly explaining that switching FET 20 off stops power delivery to load 12 and therefore inherently causes the energized downstream node to fall).
Sawano does not disclose the computing unit measures the voltage after the switch and, on the basis of this voltage, draws conclusions about the functionality of the voltage monitor.
Bisanz discloses the computing unit measures the voltage after the switch and, on the basis of this voltage, draws conclusions about the functionality of the voltage monitor (see paragraph [0022], explaining that the controller tests whether driving the semiconductor switch produces the post-switch voltage change and concludes from that change that the protective switch is functional and capable of interrupting the circuit).
It would have been obvious to one skilled in the art, prior to the effective filing date of the claimed invention, to modify Sawano by providing Bisanz’s load-side voltage measurement to Sawano’s microcomputer so that the microcomputer verifies the actual interruption produced by FET 20, as taught by Bisanz. Doing so would provide an end-to-end test of the protection chain rather than testing only the comparator and notification state, because Bisanz explains in paragraph [0022] that detecting the voltage change establishes that the driven switch is functional and capable of interrupting the protected circuit. The modification would predictably improve fault coverage by detecting a switch that received the proper control signal but failed to open. One skilled in the art would have had a reasonable expectation of success because Sawano and Bisanz both employ controller-operated semiconductor switches in DC power lines, and adding a load-side voltage-sensing input requires only a conventional voltage monitor connected to the existing controller.
As to claim 17, Sawano and Bisanz disclose the method of claim 16, wherein Sawano further discloses (see Fig. 5) wherein the test signal causes an increase or decrease in the voltage of the voltage source (see paragraph [0053], explaining that the applied voltage increases from its non-test state to a voltage greater than or equal to the reference voltage).
As to claim 18, Sawano and Bisanz disclose the method of claim 16, wherein Sawano further discloses (see Fig. 8) the computing unit transmits a test signal at regular time intervals (see paragraphs [0017-0018]).
As to claim 19, Sawano and Bisanz disclose the method of claim 16, wherein Sawano further discloses (see Fig. 5) the operating voltage range of the circuit is between 4.5 and 5.5 V, or between 3.0 and 3.6 V, wherein the working voltage range defines the range in which the system's function is guaranteed (see [0114-0115]).
As to claim 21, Sawano and Bisanz disclose the method of claim 16, wherein Sawano further discloses (see Fig. 5) wherein the maximum voltage for ensuring the function of the voltage monitor is between approximately 5.5 and 6 V or between 3.6 and 4 V (see paragraph [0045], explaining that regulator 22 steps down the output of DC power source 11 to constant system voltage Vc, such as 5.5 and 6 V or between 3.6 and 4 V).
As to claim 22, Sawano and Bisanz disclose the method of claim 16, wherein Sawano further discloses wherein the voltage source reduces a supply voltage as input voltage to the system voltage (see paragraph [0045], explaining that regulator 22 steps down the output of DC power source 11 to constant system voltage Vc, such as 5.0 V or 3.3 V).
As to claim 23, Sawano and Bisanz disclose the method of claim 16, wherein Sawano further discloses wherein the supply voltage is between 10 V and 50 V (see paragraph [0045], explaining that regulator 22 steps down the output of DC power source 11 to constant system voltage Vc, such as 10 V and 50 V).
As to claim 24, Sawano and Bisanz disclose the method of claim 16. Sawano does not disclose wherein the operation of the circuit is maintained during the transmission of a test signal and the possible switching off of the switch by means of a second voltage source.
Bisanz discloses wherein the operation of the circuit is maintained during the transmission of a test signal and the possible switching off of the switch by means of a second voltage source (see paragraph [0023], explaining that capacitor C1 supplies the load with a comparatively stable voltage during the test interruption so that opening the semiconductor switch has hardly any effect on the load circuit).
It would have been obvious to one skilled in the art to add Bisanz’s capacitor hold-up source to the load side of Sawano’s FET so that the protected load continues operating during the switch-interruption test. Bisanz explains in paragraph [0023] that C1 provides a comparatively stable voltage during the interruption and thereby prevents the test from materially affecting the load. The predictable benefit is uninterrupted load operation while the protection circuit is tested. One skilled in the art would have had a reasonable expectation of success because a charged capacitor connected to the load of Sawano’s DC power circuit would predictably discharge into that load when the series FET opens.
As to claim 25, Sawano and Bisanz disclose the method of claim 16. Sawano does not disclose wherein the second voltage source comprises capacitors.
Bisanz discloses wherein the second voltage source comprises capacitors (see paragraph [0023], explaining that capacitor C1 stores energy and supplies the load during the switch interruption).
It would have been obvious to one skilled in the art to implement the second voltage source using Bisanz’s capacitor C1 because Bisanz explains in paragraph [0023] that the capacitor supplies the load with a comparatively stable voltage during the test interruption. The use of a charged capacitor as a temporary voltage source would have produced the predictable result of short-duration load hold-up, and one skilled in the art would have had a reasonable expectation of success in the disclosed DC power circuit.
Regarding claim 26, Sawano discloses Circuit for checking the functionality of a voltage monitor (see paragraph [0054], explaining that the disclosed circuit permits microcomputer 27 to test the notification function) comprising; a voltage source that provides an adjustable output voltage (see paragraph [0051], explaining that application circuit 26 selectively applies and stops applying a voltage under microcomputer control); a switch for interrupting the flow of current (see paragraph [0035], explaining that FET 20 interrupts current when switched off); and a comparison unit that compares the voltage at the output of the voltage source with a reference voltage and, based on the comparison result, can send a switch-off signal to the switch (see paragraph [0071], explaining that comparator 51 changes its output when the monitored voltage reaches reference voltage Vr and drive unit 50 switches FET 20 off); Sawano also discloses the test-signal portion of the computing unit is provided to send a test signal to the voltage source in order to change the voltage of the voltage source and to check the operability of the voltage monitoring with the voltage at the output of the switch (see paragraph [0054], explaining that microcomputer 27 instructs application circuit 26 to apply and stop applying the test voltage and determines whether drive circuit 23 made the expected notification).
Sawano does not disclose a computing unit which measures the voltage at the output of the switch, wherein or the requirement to check operability with the voltage at the output of the switch.
Bisanz discloses a computing unit which measures the voltage at the output of the switch, wherein (see paragraph [0021], explaining that monitoring component M senses the reduced load-side voltage and reports the change to controller C; Under the broadest reasonable interpretation, controller C and its connected monitoring input constitute the claimed computing unit, consistent with the examined specification’s use of a separate feedback unit connected to computing unit 19).
Bisanz further discloses checking operability with the voltage at the output of the switch (see paragraph [0022], explaining that the controller determines whether switch actuation produced the post-switch voltage change and concludes that the semiconductor switch is functional).
It would have been obvious to one skilled in the art, prior to the effective filing date of the claimed invention, to modify Sawano’s circuit by connecting Bisanz’s load-side voltage monitor to Sawano’s microcomputer so that the microcomputer evaluates the actual output response of FET 20. Bisanz explains in paragraph [0022] that detecting the voltage change establishes that the switch is functional and capable of interrupting the circuit, providing an end-to-end verification of switch operation. One skilled in the art would have had a reasonable expectation of success because the references use compatible DC supply lines, semiconductor switches, voltage sensing, and electronic controllers, and the added voltage-monitor input does not alter the basic switching operation.
As to claim 27, Sawano and Bisanz disclose the circuit of claim 26, wherein Sawano further discloses wherein the voltage at the output of the voltage source has a tolerance range and the comparison unit sends a switch-off signal to the switch if the measured voltage at the output of the voltage source is outside this tolerance range (see paragraph [0071], explaining that comparator 51 changes its output when the monitored voltage reaches or exceeds reference voltage Vr and drive unit 50 consequently switches FET 20 off).
As to claim 28, Sawano and Bisanz disclose the circuit of claim 26. Sawano does not disclose wherein a second voltage source, in particular capacitors, is provided which, when the current flow through the switch is interrupted, supplies current to the output of the circuit and ensures the continued functioning of the circuit.
Bisanz discloses wherein a second voltage source, in particular capacitors, is provided which, when the current flow through the switch is interrupted, supplies current to the output of the circuit and ensures the continued functioning of the circuit (see paragraph [0023], explaining that capacitor C1 supplies the load with a comparatively stable voltage during the interruption so that the load circuit remains functional).
It would have been obvious to one skilled in the art to add Bisanz’s capacitor C1 to Sawano’s load-side circuit because Bisanz explains in paragraph [0023] that C1 maintains a comparatively stable load voltage and prevents the short test interruption from materially affecting the load. The predictable benefit is continued operation during the self-test. One skilled in the art would have had a reasonable expectation of success because capacitor hold-up across a DC load is compatible with Sawano’s series-FET power path and requires no change to the comparator’s test operation.
As to claim 30, Sawano and Bisanz disclose the circuit of claim 26. Sawano does not disclose wherein the protective device against feedback is formed by a semiconductor circuit, in particular a diode.
Bisanz discloses wherein the protective device against feedback is formed by a semiconductor circuit, in particular a diode (see paragraph [0023], expressly identifying the feedback-blocking element as a reverse-polarity protection diode).
It would have been obvious to one skilled in the art to use Bisanz’s diode as the feedback-blocking device because Bisanz explains in paragraph [0023] that the diode separates the rapidly discharging measurement node from capacitor C1, which continues supplying the load. The predictable result is unidirectional isolation between the hold-up source and the switch-side measurement node. One skilled in the art would have had a reasonable expectation of success because a diode is a conventional semiconductor element whose disclosed polarity necessarily blocks reverse current in the claimed arrangement.
Allowable Subject Matter
Claims 20 & 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In terms of claim 20, the prior art of record does not teach or suggest, either alone or in combination, “wherein the voltage changed by the test signal is outside the operating voltage range and within a defined voltage range in which no overloading of the system takes place,” in combination with all of the other limitations of claim 16 from which claim 20 depends.
In terms of claim 29, the prior art of record does not teach or suggest, either alone or in combination, “wherein a protection device against feedback is arranged between the second voltage source and the switch in such a way that the current can never flow from the second voltage source to the switch and the measurement of the computing unit is not influenced by the second voltage source,” in combination with all of the other limitations of claim 26 from which claim 29 depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 9,557,354 B2 to Chen et al. disclose a circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.
U.S. 2025/0237729 A1 to Mohr discloses a method for checking the functionality of the voltage monitoring of a circuit is presented and described. The method includes a computing unit sending a test signal to a voltage source, which causes a change in the voltage of the voltage source. A comparison unit compares the voltage at the output of the voltage source with a reference voltage and sends a shutdown signal to a switch if the voltage at the output of the voltage source is outside a predetermined tolerance range. The switch interrupts the flow of current when it receives a shutdown signal, causing the voltage after the switch to drop.
U.S. 2021/0011080 A1 to Narwal et al. disclose circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRUNG NGUYEN whose telephone number is (571)272-1966. The examiner can normally be reached on Mon- Friday 8AM - 4:00PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Examiner: /Trung Q. Nguyen/- Art 2858
/GIOVANNI ASTACIO-OQUENDO/ Primary Examiner, Art Unit 2858 9/26/2026
