DETAILED ACTION
Claims 1-20 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/16/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-17 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 and 19-21 of U.S. Patent No. 12,235,319, hereinafter ‘319. Although the claims at issue are not identical, they are not patentably distinct from each other because the current application recites first, second and third sensor outputs couple to the fault logic input, where ‘319 recites receiving sensor data values at an input of a fault logic circuit, wherein each respective sensor data value represents a measurement of a respective system parameter. These differences would be obvious to one of ordinary skill in the art to be a similar recitation.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the nonstatutory double patenting rejection, set forth in this Office action or by timely filing a terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Prejbeanu (A Sensor-Based System for Fault Detection and Prediction for EV Multi-Level Converters, published: 22 April 2023, MDPI, pp. 1-36) teaches Power electronic converters and alternating current motors are the actual driving solution applied to electric vehicles (EVs). Multilevel inverters with high performance are modern and the basis for powering and driving EVs. Fault component detection in multilevel power converters requires the use of a smart sensor-based strategy and an optimal fault analysis and prediction method. An innovative method for the detection and prediction of defects in multilevel inverters for EVs is proposed in this article. This method is based on an algorithm able to determine in a fast and efficient way the faults in a multilevel inverter in different possible topologies. Moreover, the fault detection is achieved not only for a single component, but even for several components, if these faults occur simultaneously. The detection mechanism is based on the analysis of the output current and voltage from the inverter, with the possibility of distinguishing between single and multiple faults of the power electronic components. High-performance simulation programs are used to define and verify the method model. Additionally, with this model, harmonic analysis can be performed to check the correctness of the system’s operation, and different fault scenarios can be simulated. Thus, significant results were obtained by simulation on various topologies of multilevel converters. Further, a test bench was developed in order to verify some failure situations on a three-level inverter. (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 06/26/2026
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