DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d) which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is accepted.
Drawings
The formal drawings are accepted.
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or
composition of matter, or any new and useful improvement thereof, may obtain a patent
therefore, subject to the conditions and requirements of this title.
Claims 1, 4-12, and 15-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) obtaining a statistical result and making a determination based on the statistical result, which is considered a mental process or mathematical concept.
With respect to claim 1:
Eligibility step 1: Yes, the claim as a whole fall within one or more statutory categories.
Eligibility step 2A (prong one): Yes, the claim recites a judicial exception.
An abstract idea is set forth or described in the claim. The limitations of “obtain a statistical result of a physical page corresponding to a first read voltage, wherein the statistical result includes at least one of a first number of bits flipped between two read results of the physical page corresponding to the first read voltage and a read voltage having a voltage difference of less than a preset voltage with the first read voltage, or a second number of bits of the physical page not successfully read using the first read voltage, and wherein the first read voltage is less than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page”. A statistical result is a mathematical concept and is considered an abstract idea. The limitation of “determine a read disturb state of the physical page according the statistical result” are considered mathematical relationships and/or mathematical calculations” is a mental process. The limitation is directed to an observation and judgment and can be reasonably performed in the human mind. A mental process is an abstract idea.
Eligibility step 2A (prong two): No, the claim does not recite additional elements that integrate the judicial exception into a practical application. The limitations regarding a memory controller, memory device and processor are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim.
Eligibility step 2B: The limitations regarding a memory controller, memory device and processor are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim. These elements
individually, and in combination, do not add significantly more than the judicial exception. The claim as a whole does not amount to significantly more than the exception itself and therefore lacks subject matter eligibility.
Independent claim 10 is directed to a memory system including one or more memory device and a memory controller includes a processor generally similar limitation as claim 1. The memory system appears to be a general field of use and is only cited in the preamble of the claim. Furthermore, the data memory system is considered to be generic components and does not add meaningful limitations to the claim. See MPEP 2106.05(f-h). Therefore claim 10 is rejected. Similarly independent claim 12 is directed to a memory device and a peripheral circuit generally recites similar limitations as claims 1 and 10. As previously stated, the memory device and a peripheral circuit are considered to be generic components and do not add meaningful limitations to the claim. Therefore, the additional elements do not provide significantly more than the abstract idea. The claim is not patent eligible. Therefore claim 12 is rejected as well.
Respective dependent claims 4-,9, 11, and 15-20 do not cure the deficiency of parent claims since they do not add anything more to the abstract idea and are therefore rejected at least based on dependency
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will
not be considered a new ground of rejection if the prior art relied upon, and the rationale
supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness
under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or non-obviousness.
Claim(s) 1-4, 6-8, 10-15, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juan “herein as Juan” (U.S. Patent Application Publication #2024/0201875) in view of DeSantis et al. “herein as DeSantis” (U.S. Patent Application Publication #2020/0152278).
As per claims 1 and 10:
Juan substantially teaches or discloses a memory controller (see [0062] coupled to at least one memory device (see [0062]: controller includes device interface pins to send and receive signals to/from semiconductor device), wherein the memory device includes a plurality of word lines, each word line is coupled to a plurality of memory cells, and the plurality of memory cells form at least one physical page (see [0053]: memory cells coupled in series to form row word lines, which form pages); the memory controller includes: a processor, (see [0062]: controller includes a processor) configured to: obtain a statistical result of a physical page corresponding to a first read voltage (see [0098]) wherein the statistical result includes at least one of a first number of bits flipped between two read results of the physical page (see [0090]: data is read at multiple different read voltage) corresponding to the first read voltage and a read voltage having a voltage difference of less than a preset voltage with the first read voltage (see [0092]: data is read at a default voltage, and a second voltage using a voltage step), or a second number of bits of the physical page not successfully read using the first read voltage, and wherein the first read voltage is less than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see DeSantis Below); and determine a read disturb state of the physical page according to the statistical result (see [0091]: If read disturbance is likely to have occurred, read voltages in-between the two lowest-threshold voltage distribution states (e.g., states ER and A in FIG. 3) can be selected, such as voltages intermediate between the peaks of distributions 302 and 304 of FIG. 4A. These selections correspond to the states most likely to be affected by data retention degradation and read disturbance, respectively)
Juan did not explicitly teach a second number of bits of the physical page not successfully read using the first read voltage, and wherein the first read voltage is less than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page.
However, DeSantis in an analogous art discloses a second number of bits of the physical page not successfully read using the first read voltage, and wherein the first read voltage is less than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see [0053]: percentage of cells that are activated using an intermediate read voltage).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify Juan to obtain a statistical result of a second number of bits successfully read, as disclosed by DeSantis. One of ordinary skill in the art would have been motivated to make such a modification to accurately determine a read disturb, as taught by DeSantis. Juan and DeSantis are analogous/in the same field of endeavor as both references are directed to managing data retention in memory systems.
As per claims 2, 11, and 13:
Juan in view of the above rejection teaches wherein the processor is configured to:
determine whether the data disturb state of the physical page is inferior according to a
relationship between the statistical result and a preset threshold (see [0091): it can be determined whether data retention degradation or read disturbance are likely to have occurred. If data retention degradation is likely to have occurred, read voltages in-between the two highest-threshold voltage distribution states (e.g., states B and C in FIG. 3) can be selected, such as voltages intermediate between the peaks of distributions 402a and 306 of FIG. 4A. If read disturbance is likely to have occurred, read voltages in-between the two lowest-threshold voltage distribution states (e.g., states ER and A in FIG. 3) can be selected, such as voltages intermediate between the peaks of distributions 302 and 304 of FIG. 4A. These selections correspond to the states most likely to be affected by data retention degradation and read disturbance, respectively; however, voltages between other states can be used instead or additionally. The controller or the memory can identify a particular state to test and, based on the selected state, determine first and second read voltage, such as voltages that are likely to overlap with a distribution corresponding to the state if the distribution has shifted. Moreover, in some implementations, values of the first read voltage and/or second read voltage can be based on the usage data, e.g., to adapt to threshold voltage distribution shifts.
As per claims 3 and 14:
Juan in view of the above rejection teaches wherein the preset threshold includes at least one of a first threshold or a second threshold; and the processor is configured to: determine that the read disturb state of the physical page is inferior according to at least one of the first number being greater than the first threshold or the second number being greater than the second threshold (see [0091] and [0100]).
As per claims 4 and 15:
DeSantis in view of the above rejection teaches wherein a plurality of storage states of the physical page include a first storage state and a second storage state having a threshold voltage interval with the lowest mean value; and wherein the first read voltage is between a first threshold voltage and a second threshold voltage, the first threshold voltage is a mean value of a threshold voltage interval corresponding to the first storage state when the physical page is writing data, and the second threshold voltage is a mean value of a threshold voltage interval corresponding to the second storage state when the physical page is writing data (see par. [0053]).
As per claim 6:
Juan in view of the above rejection teaches wherein the memory controller further includes an interface coupled to the processor; and the interface is configured to: receive, from the memory device, the statistical result of the physical page corresponding to the first read voltage; or the interface is configured to: receive, from the memory device, read results of the physical page corresponding to the first read voltage and a second read voltage respectively, or the read result of the physical page corresponding to the first read voltage; and the processor is configured to: perform operations and statistics on the read results to obtain a statistical result ([0063], [0131] – [0134]).
As per claim 7:
Juan in view of the above rejection teaches wherein the processor is configured to: obtain the first read voltage and the preset threshold respectively (see [00902]).
As per claims 8 and 17:
Juan in view of the above rejection wherein the processor is configured to: when the memory controller is powered on, obtain the first read voltage and the preset threshold respectively from the memory device, wherein both the first read voltage and the preset threshold are fixed values (see [00902]).
As per claim 12:
Juan substantially teaches or discloses a memory device, including: a plurality of word lines, each word line is coupled to a plurality of memory cells, and the plurality of memory cells form at least one physical page (see [0053]: memory cells coupled in series to form row word lines, which form pages); a peripheral circuit coupled to the plurality of word lines (see [0134]: multiplexing device that provides an interface between the controller and the word lines of the memory) and configured to: obtain a statistical result of a physical page corresponding to a first read voltage (see [0098]: average number of mismatches; see also DESANTIS below), wherein the statistical result includes at least one of a first number of bits flipped between two read results of the physical page (see [0090]: data is read at multiple different read voltage) corresponding to the first read voltage and a read voltage having a voltage difference of less than a preset voltage with the first read voltage (see [0092]: data is read at a default voltage, and a second voltage using a voltage step), or a second number of bits of the physical page not successfully read using the first read voltage, and wherein the first read voltage is less than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see DESANTIS below); and determine a read disturb state of the physical page according to the statistical result and determine a read disturb state of the physical page according to the statistical result (see [0091]: If read disturbance is likely to have occurred, read voltages in-between the two lowest-threshold voltage distribution states (e.g., states ER and A in FIG. 3) can be selected, such as voltages intermediate between the peaks of distributions 302 and 304 of FIG. 4A. These selections correspond to the states most likely to be affected by data retention degradation and read disturbance, respectively)
Juan did not explicitly teach a second number of bits of the physical page not successfully read using the first read voltage, and wherein the first read voltage is less than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page.
However, DeSantis in an analogous art discloses a second number of bits of the physical page not successfully read using the first read voltage, and wherein the first read voltage is less than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see [0053]: percentage of cells that are activated using an intermediate read voltage).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify Juan to obtain a statistical result of a second number of bits successfully read, as disclosed by DeSantis. One of ordinary skill in the art would have been motivated to make such a modification to accurately determine a read disturb, as taught by DeSantis. Juan and DeSantis are analogous/in the same field of endeavor as both references are directed to managing data retention in memory systems.
As per claim 19:
Juan substantially teaches wherein the plurality of memory cells coupled to the word line form a plurality of physical pages, and the plurality of physical pages includes a plurality of target physical pages; the peripheral circuit is configured to: apply the first read voltage to a selected word line of the plurality of word lines; for each target physical page of the plurality of target physical pages coupled to the selected word line(see [0052]-[0056]), determine a read disturb state of a respective target physical page according to the statistical result of the respective target physical page corresponding to the first read voltage; and float the selected word line after completing the read disturb state of all of the target physical pages coupled to the selected word line (see [0091]: If read disturbance is likely to have occurred, read voltages in-between the two lowest-threshold voltage distribution states (e.g., states ER and A in FIG. 3) can be selected, such as voltages intermediate between the peaks of distributions 302 and 304 of FIG. 4A. These selections correspond to the states most likely to be affected by data retention degradation and read disturbance, respectively).
As per claim 20:
Juan substantially teaches wherein the statistical result includes a first number, and the peripheral circuit is configured to: read stored data of the physical page using the first read voltage to obtain a first result (see JUAN [0090]; data read at multiple voltages, the first read uses a first voltage); adjust the first read voltage to obtain an adjusted read voltage, and read the stored data of the physical page using the adjusted read voltage to obtain a second result (see JUAN [0092]: the second read uses a second voltage based on a differential from the first voltage); perform a logical operation on the first result and the second result to obtain a third result (see JUAN [0095]: XOR operation); and count the number of bits in the third result that represent that the second result is flipped relative to the first result (see JUAN [0095]: results of the XOR operation are used to determine a count of mismatches), to obtain the first number, wherein the peripheral circuit includes a first latch, a second latch, and a third latch, and wherein the first latch is configured to store the first result; the second latch is configured to store the second result; and the third latch is configured to store the third result (see JUAN [0103]-[0104]: circuitry for performing the XOR operations stores the result).
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juan (U.S. Patent Application Publication #2024/0201875) and DeSantis (U.S. Patent Application Publication #2020/0152278) and further in view of Desi (U.S. Patent Application Publication #2023/0114146).
As per claims 9 and 18:
Juan and DeSantis substantially teach wherein the processor is configured to: when the memory controller is powered on, obtain an initial value of the first read voltage and an initial value of the preset threshold respectively from the memory device (see Juan [0031]: set feature command to adjust read voltage); and modify, by setting a feature command, at least one of the initial value of the first read voltage or the initial value of the preset threshold to obtain the first read voltage and the preset threshold (see Desai below).
Juan and DeSantis did not explicitly teach modifying by setting a feature command, at least one of the initial value of the first read voltage or the initial value of the preset threshold to obtain the first read voltage and the preset threshold.
However, Desai discloses the following limitations that are not taught by Juan and DeSantis: modify, by setting a feature command, at least one of the initial value of the first read voltage or the initial value of the preset threshold to obtain the first read voltage and the preset
threshold (see [0031]: set feature command to adjust read voltage). The optimal voltage to read data can be affected by multiple conditions. Using the set feature command allows a voltage setting command to adjust the read voltage value to a new, optimal value, for reading the page (see [0031]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify Juan to use the set feature command, as disclosed by DESAI. One of ordinary skill in the art would have been motivated to make such a modification to adjust a read voltage to the optimal value, as taught by Desi. JUAN and DESAI are analogous/in the same field of endeavor as both references are directed to reading data from flash memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
LIU [12,579,023] discloses performing a first and second read, counting the number of bit flips, generating a histogram of bit flips, memory cell degradation and data refresh operations. [Columns 2, 4, 7-9, 13, 14]
REDDY [12,443,348] discloses performing a read scrub of a block before errors occur, targeted wordline refresh if the number or errors exceeds a threshold, estimate the number of bit flips based on age and queueing blocks for relocation based on estimated bit flip count. [Columns 6-7].
RIJO [11,734,110] discloses counting bit flips during a power on process, error testing and a bit flipped count. [Columns 11 and 13].
LU [2020/0117536] discloses multiple reads and counting of flipped bits and calibration of a read voltage level. [0045]-[0049].
SYU [2014/0059405] discloses estimating a data age during power on, data scrubbing to preserve data retention, scrubbing before page hits error rate and maintaining the time since last programming. [0026]-[0036]
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
Prosecution Insights