Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b).The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http ://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.jsp.
Claim 1 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,360,163 in view of Hinz (U.S. Patent No. 8,321,652), hereinafter “Hinz.”
Although the claims are not identical, they are not patentably distinct because both claims are directed to receiving neural-network input activations, determining which input activations are retained based on whether they are zero or non-zero, associating the retained input activations with memory address locations, storing the retained input activations in memory, retrieving the retained input activations from the associated memory address locations, and providing the retrieved input activations to a computational array through a data bus for neural-network computation.
Specifically, claim 1 of U.S. Patent No. 10,360,163 recites receiving multiple inputs for processing by a neural-network layer, determining whether each input has a zero value or a non-zero value, determining a mapping of a subset of non-zero inputs to memory-bank address locations, storing the subset of inputs using the determined mapping, and providing an input from a mapped memory address location to a data bus coupled to one or more multiply-accumulate units of a computational array.
The instant claim differs by expressly reciting generating an index comprising one or more memory address locations and retrieving the input activations using the generated index. However, these additional limitations merely define a particular implementation of the address-mapping and retrieval mechanism already recited in claim 1 of U.S. Patent No. 10,360,163.
Hinz discloses organizing address-related information using an indexed lookup structure. In particular, Hinz discloses a logical block address index table stored in volatile memory, such as DRAM, having pointers to corresponding entries in a logical-to-physical address translation table, with the translation-table entries further pointing to physical memory locations containing stored data (Hinz, Fig. 1; col. 4, l. 62–col. 5, l. 7). For a read operation, a controller calculates a DRAM address for the index table, uses the identified index-table entry to locate a page address in the translation table, and follows a further pointer to identify the physical memory location containing the requested data (Hinz, col. 5, ll. 8–16). Hinz further teaches accessing the index table according to the requested logical addresses, obtaining an address pointer identifying the corresponding translation-table entry, and reading the data using the resulting logical-to-physical address translation (Hinz, col. 6, ll. 10–16).
Claim 1 of U.S. Patent No. 10,360,163 and Hinz are analogous art because they are reasonably pertinent to the same problem-solving area of efficiently organizing, locating, and retrieving selected stored data through associated memory addresses.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of claim 1 of U.S. Patent No. 10,360,163 and Hinz before him or her, to modify the mapping of retained non-zero input activations to memory address locations recited in claim 1 of U.S. Patent No. 10,360,163 by organizing the mapped memory address locations into an address index table having pointers to the corresponding memory locations, as taught by Hinz. location for provision to the data bus and computational array.
The suggestion or motivation for doing so would have been to provide quick and efficient access to the retained input activations while reducing the amount of address information that must be directly searched or accessed during retrieval.
Therefore, it would have been obvious to combine the teachings of Hinz with claim 1 of U.S. Patent No. 10,360,163 to obtain the invention as recited in the instant claim.
Claim 1 of the application 19/025,263
Claim 1 of Pat. No. 10360163
1. A computer-implemented method, comprising:
receiving, by a computing device, a plurality of input activations, the input activations being provided, at least in part, from a source external to the computing device;
determining, by a controller of the computing device, whether each of the plurality of input activations has one of a zero value or a non-zero value;
storing, in a memory bank of the computing device, at least one of the input activations; generating, by the controller, an index comprising one or more memory address locations having input activation values that are non-zero values; and
providing, by the controller and from the memory bank, at least one input activation onto a data bus that is accessible by one or more units of a computational array, wherein the activations are provided, at least in part, from a memory address location associated with the index.
1. A computer-implemented method for performing neural network computations for a neural network comprising a plurality of layers, the method comprising:
receiving, by a computing device, multiple inputs for processing at a first layer of the neural network, the multiple inputs being provided, at least in part, from a source external to the computing device;
determining, by a controller of the computing device, whether each of the multiple inputs has one of a zero value or a non-zero value;
determining, by the controller, a mapping of a subset of inputs to address locations for a memory bank at the computing device based on the determined value of each input, wherein inputs having a zero value are excluded from the subset;
storing, in the memory bank, the subset of inputs using the determined mapping of the subset of inputs to address locations for the memory bank; and
providing, by the controller and from the memory bank, an input from the subset of inputs to a data bus coupled to one or more multiply accumulate units of a computational array, wherein the input is provided from a memory address location to which the subset of inputs are mapped.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Vlietinck et al. (US Pab. No. 20160322042), hereinafter referred to as Vlietinck in view of Hinz (US Pat. No. 8321652).
As to claim 1, Vlietinck discloses a computer-implemented method (processor-executed DNN processing performed in computer 600, Figs. 1, 2A, 4, and 6, paras. 0028–0033, 0056, and 0063), comprising:
receiving (speech recognition front-end 112 produces feature vector 114 that is received and used by DNN processing unit 116, Fig. 1, paras. 0027–0029), by a computing device (DNN processing unit 116 implemented by processor 506 or central processor unit 618, Figs. 1, 5, and 6, paras. 0028–0029 and 0062–0063), a plurality of input activations (input values associated with the plurality of input neurons of previous DNN layer 252, Figs. 1 and 2B, paras. 0029 and 0036–0037), the input activations being provided (feature vector 114 is provided to DNN processing unit 116 and respective non-zero input values are loaded into hardware registers for processing, Figs. 1 and 2B, paras. 0028 and 0042–0043), at least in part, from a source external (speech recognition front-end 112 is a separate functional component providing feature vector 114 to DNN processing unit 116, Fig. 1, para. 0028), to the computing device (feature vector 114 passes from speech recognition front-end 112 to DNN processing unit 116, Fig. 1, para. 0028);
determining (selecting non-zero input neurons while encountering and skipping zero-skip neurons, Figs. 2B and 4, paras. 0037, 0041, and 0056–0059), by a controller of the computing device (processor 506 executing update unit 508 and related DNN-processing functions, Fig. 5, para. 0062), whether each of the plurality of input activations (each input neuron has an associated input value and is categorized as a non-zero input neuron or a zero-skip neuron, Fig. 2B, paras. 0036–0037 and 0041), has one of a zero value (null input value associated with a zero-skip neuron, Fig. 2B, paras. 0037 and 0041) or a non-zero value (non-zero input value associated with a non-zero input neuron, Fig. 2B, paras. 0037 and 0041);
storing (respective input values are obtained from memory and loaded into hardware registers, Fig. 2B, paras. 0042–0043), at least one of the input activations (selected non-zero input values are loaded into hardware registers after being obtained from memory, Fig. 2B, paras. 0042–0043),
having input activation values that are non-zero values (identifies and selects the non-zero input values to be retrieved and processed, Figs. 2B and 4, paras. 0037, 0041–0043, and 0056); and
providing (selected non-zero input values are loaded from memory into hardware registers for use in computing incremental output values, Fig. 2B, paras. 0042–0043), by the controller (processor 506 or central processor unit 618, Figs. 5 and 6, paras. 0062–0063), at least one input activation (input value of a selected non-zero input neuron 256, Fig. 2B, paras. 0040–0043) onto a data bus (computer system bus 602 transfers information between memory 608 and central processor unit 618, Fig. 6, para. 0063) that is accessible by one or more units of a computational array (DNN processing unit 116 executes DNN topology 118 comprising arrays of input neurons, hidden-layer neurons, and output neurons that perform computations using the selected input values, Fig. 1, paras. 0028–0029), wherein the activations are provided (selected non-zero input values are loaded for computation, Fig. 2B, paras. 0042–0043).
Hinz discloses, what Vlietinck lacks, in a memory bank of the computing device (volatile memory 302, such as an SDRAM, stores address-index information and buffers data, and nonvolatile memory 301 stores addressable data, Figs. 1 and 3, col. 4, ll. 25–32 and 54–65);
generating (forms and updates a logical block address index table whose entries provide pointers for locating stored data, Figs. 1–2, col. 4, ll. 25–32 and 54–65; col. 6, ll. 1–16; col. 7, ll. 42–52), by the controller (controller 303 coupled to volatile memory 302 and nonvolatile memory 301, Fig. 3, col. 7, ll. 10–28), an index (DRAM logical block address index table containing pointers to corresponding entries of the flash logical block address translation table, Figs. 1–2, col. 4, ll. 54–65; col. 5, ll. 1–16) comprising one or more memory address locations (index-table pointers identify translation-table locations, whose further pointers identify physical flash-management-block locations containing requested data, Figs. 1–2, col. 5, ll. 8–16; col. 6, ll. 10–16);
from the memory bank (controller 303 transfers data between volatile memory 302 and nonvolatile memory 301, which store the index information and addressable data, Fig. 3, col. 7, ll. 10–38);
from a memory address location (controller calculates the index-table address, follows the index-table pointer to a translation-table page address, and follows the translation-table pointer to the physical memory location containing the requested data, Figs. 1–2, col. 5, ll. 8–16; col. 6, ll. 10–16) associated with the index (DRAM logical block address index table contains pointers associated with translation-table locations and corresponding physical locations of stored data, Figs. 1–2, col. 4, ll. 54–65; col. 5, ll. 8–16; col. 7, ll. 42–52).
Vlietinck and Hinz are analogous art because they are from the same problem-solving area of improving computer processing efficiency through optimized memory access and retrieval of selected stored data.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Vlietinck and Hinz before him or her, to modify the memory-access architecture used by the DNN processing unit of Vlietinck to include the address-index table, address pointers, and controller-directed indexed retrieval technique of Hinz.
The suggestion/motivation for doing so would have been to reduce unnecessary memory accesses, conserve memory bandwidth, and efficiently retrieve selected non-zero input values stored at different memory-address locations.
Therefore, it would have been obvious to combine Hinz with Vlietinck to obtain the invention as specified in the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cho et al. (US Pub. No. 20090327239) A method and apparatus for identifying devices using a bitmap are disclosed. In one embodiment, the method comprises: accessing a memory to obtain one or more bitmaps that map each bit location in the bitmap to an index value, where one index value is assigned to each remote wireless media device of a wireless network in a wireless communication system.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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