DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/16/2025, 08/28/2025 and 01/07/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-8, 10, 15-18 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Park (US 2012/0105680).
Regarding claim 1, Park discloses a method executable by an image sensor (image sensor, i.e. video codec-embedded image sensor) (Park, fig. 1, 3, 4, par [0040]), the method comprising:
in response to receiving a clock signal (low speed clock) from an external clock source (clock generation unit 500), transitioning from a sleep mode (an idle state S10) to an active mode (image data obtaining operation S20) in which an operation (image signal processing operation) is performed (Park, figs. 1, 3, 4, par [0079-0080], wherein with the low speed clock from clock generation unit 500, the image sensor changes to image signal processing operation from an idle state); and
in response to a discontinuation of the clock signal (no clock) from the external clock source, transitioning from the active mode (image signal processing operation) to the sleep mode (idle state S10) in which the operation cannot be performed (Park, figs. 1, 3, 4, par [0079-0080], wherein without clock from clock generation unit 500, the image sensor changes from image signal processing operation to an idle state in which image signal processing operation is not performed).
Regarding claim 5, Park discloses a method executable by an image system (image sensor, i.e. video codec-embedded image sensor) (Park, fig. 1, 3, 4, par [0040]), the method comprising:
a) transmitting, from a processor (domain 100) to a clock generator (clock generation unit 500), a first signal instructing the clock generator to transmit a clock signal (low speed clock) to an image sensor (image sensor) (Park, figs. 1, 3, 4, par [0041,0045], wherein the low speed clock from clock generation unit 500 is sent to image sensor under overall control by domain 100);
b) transitioning, by the image sensor and in response to receiving the clock signal, from a sleep mode (idle state S10) to an active mode (image data obtaining operation S20) in which an operation is performed (Park, figs. 1, 3, 4, par [0079-0080], wherein with the low speed clock from clock generation unit 500, the image sensor changes to image signal processing operation from an idle state); and
c) transitioning, by the image sensor and in response to a discontinuation of the clock signal (no clock), from the active mode to the sleep mode in which the operation cannot be performed (Park, figs. 1, 3, 4, par [0079-0080], wherein without clock from clock generation unit 500, the image sensor changes from image signal processing operation to an idle state in which image signal processing operation is not performed).
Regarding claim 6, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses:
(d) transmitting, from the image sensor (image sensor) to the processor (domain 100), an interrupt signal (interrupt signal at the end of image data obtaining operation S20 ) indicating the completion of the operation (Park, figs. 1, 3, 4, par [0041, 0045, 0078-0080], wherein an interrupt signal at the end of data obtaining operation S20 is sent from image sensor to domain 100).
Regarding claim 7, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses:
(e) instructing, by the processor, the clock generator to discontinue transmitting the clock signal to the image sensor (Park, figs. 1, 3, 4, par [0079-0080], wherein without clock from clock generation unit 500, the image sensor changes from image signal processing operation to an idle state in which image signal processing operation is not performed).
Regarding claim 8, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses:
(f) acquiring, by the processor (domain 100) and from the image sensor,(image sensor) status information (status information) indicating whether the operation was performed successfully (Park, figs. 1, 3, 4, par [0041, 0045, 0078-0080], wherein status information is communicated between image sensor and domain 100);
(g) determining, by the processor, whether the operation was performed successfully based on the status information (Park, figs. 1, 3, 4, par [0041, 0045, 0078-0080], wherein domain 100 determines success of data obtaining operation S20); and
(h) repeating operations (a) through (g) in response to determining the operation was performed unsuccessfully (Park, figs. 1, 3, 4, par [0041, 0045, 0078-0080], wherein domain 100 repeats sending no clock or low speed clock in block S10 and S20).
Regarding claim 10, Park discloses a processor comprising:
a controller (domain 100) receiving a clock signal (low speed clock from clock generation unit 500) from outside and configured to generate an operation command (operation command to domain 200) (Park, figs. 1, 4, [0041, 0045, 0078-0080] wherein with low speed clock from clock generation unit 500, the domain 100 controls domain 200); and
an interface circuit (bus 150) providing the clock signal and the operation command to a sensor (image sensor pixel 210), wherein as a response to the operation command from the sensor, the interface circuit receives a first signal (signal on bus 150) comprising a result of an operation corresponding to the operation command or a second signal indicating completion of the operation (Park, figs. 1, 3, 4, where bus 150 receives signal from domain 200 having image sensor pixel 210), wherein
the controller (domain 100) is configured to discontinue the clock signal (no clock) provided to the sensor based on the first signal (signal on bus 150) or the second signal (Park, figs. 1, 3, 4, par [0087-0091], wherein no clock signal is sent to image sensor domain 200 having image sensor pixel 210 based on signal on bus 150).
Regarding claim 15, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses:
the controller (domain 100) receives the clock signal (low speed clock) from a clock generator (clock generation unit 500) and, in response to the second signal (signal to domain 100), provides a clock control signal of a first level to the clock generator (Park, figs. 1, 3, 4, wherein low speed clock signal is provided).
Regarding claim 16, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses:
the controller (domain 100) provides a clock control signal (normal clock)of a second level to the clock generator (clock generation unit 500) for generation of the clock signal by the clock generator (Park, figs. 1, 3, 4, wherein normal clock signal is provided).
Regarding claim 17, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses:
the controller (domain 100) is configured to receive a power signal from a power management integrated circuit (PMIC) (inherent part), provide the power signal to the sensor, and discontinue the power signal based on the first signal or the second signal (Park, fig. 1, par [0059, 0089], wherein power to domain 100-400 may be cut off).
Regarding claim 18, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses:
transmits a power control signal of a first level to the PMIC for receiving the power signal from the PMIC (Park, fig. 1, par [0059, 0089], wherein power to domain 100-400 may be controlled, and
transmits the power control signal of a second level to the PMIC for discontinuing generation of the power signal of the PMIC (Park, fig. 1, par [0059, 0089], wherein power to domain 100-400 may be cut off).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 9, 11, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2012/0105680) in view of Hanzawa (US 2023/0156323).
Regarding claim 2, Park discloses aforementioned limitations of the parent claim. However, Park does not disclose:
the operation is motion detection.
On the other hand, in the same endeavor, Hanzawa discloses:
the operation is motion detection (motion detection) (Hanzawa, fig. 4, par [0099-0102], wherein motion detection is performed).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Hanzawa into the method by Park so as to achieve the invention as claimed because such incorporation makes it possible suitably reduce power consumption of the imaging apparatus (Hanzawa, par [0012]).
Regarding claim 3, Park discloses aforementioned limitations of the parent claim. However, Park does not disclose:
the operation is face detection.
On the other hand, in the same endeavor, Hanzawa discloses:
the operation is face detection (feature detection mode) (Hanzawa, fig. 4, par [0118], wherein feature detection mode performs face detection).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Hanzawa into the method by Park so as to achieve the invention as claimed because such incorporation makes it possible suitably reduce power consumption of the imaging apparatus (Hanzawa, par [0012]).
Regarding claim 4, Park discloses aforementioned limitations of the parent claim. However, Park does not disclose:
the operation is a transmission of an image to an external processor.
On the other hand, in the same endeavor, Hanzawa discloses:
the operation is a transmission of an image (image transmission) to an external processor (external apparatuses) (Hanzawa, fig. 1, par [0063-0065], wherein image transmission is performed with external apparatuses).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Hanzawa into the method by Park so as to achieve the invention as claimed because such incorporation makes it possible suitably reduce power consumption of the imaging apparatus (Hanzawa, par [0012]).
Regarding claim 9, Park discloses aforementioned limitations of the parent claim. However, Park does not disclose:
(f) acquiring, by the processor and from the image sensor, image data of an object acquired by the image sensor;
(g) determining, by the processor, whether the image data matches a registered image; and
(h) repeating operations (a) through (g) in response to determining the image data does not match the registered image.
On the other hand, in the same endeavor, Hanzawa discloses:
(f) acquiring, by the processor (control unit 15) and from the image sensor (pixel array portion 11), image data of an object (feature) acquired by the image sensor (Hanzana, fig. 2, par [0067], wherein image data of a feature is acquired by control unit 15 from pixel array portion 11 for image processing);
(g) determining, by the processor, whether the image data matches a registered image (Hanzana, fig. 2, par [0067], wherein a match in step ST105 to ST106 is determined); and
(h) repeating operations (a) through (g) in response to determining the image data does not match the registered image (Hanzana, fig. 2, par [0067], wherein a none-match in step ST105 to ST107 and ST101 is determined).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Hanzawa into the method by Park so as to achieve the invention as claimed because such incorporation makes it possible suitably reduce power consumption of the imaging apparatus (Hanzawa, par [0012]).
Regarding claim 11, Park discloses aforementioned limitations of the parent claim. Additionally, Park discloses
the second signal comprises an interrupt signal (interrupt signal at the end of image data obtaining operation S20) indicating completion of a detection operation of the sensor (Park, figs. 1, 3, 4, par [0041, 0045, 0078-0080], wherein an interrupt signal at the end of data obtaining operation S20 is sent from image sensor to domain 100).
However, Park does not disclose:
the operation command comprises a motion detection command or a face detection command, and
the second signal comprises an interrupt signal indicating completion of a detection operation of the sensor.
On the other hand, in the same endeavor, Hanzawa discloses:
the operation command comprises a motion detection command (motion detection) (Hanzawa, fig. 4, par [0099-0102], wherein motion detection is performed) or a face detection command (feature detection mode) (Hanzawa, fig. 4, par [0118], wherein feature detection mode performs face detection).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Hanzawa into the processor by Park so as to achieve the invention as claimed because such incorporation makes it possible suitably reduce power consumption of the imaging apparatus (Hanzawa, par [0012]).
Regarding claim 13, Park discloses aforementioned limitations of the parent claim. Additionally, Park does not disclose
the operation command comprises a face detection command, and the first signal comprises image data generated by the sensor.
On the other hand, in the same endeavor, Hanzawa discloses:
the operation command comprises a face detection command (feature detection mode) (Hanzawa, fig. 4, par [0118], wherein feature detection mode performs face detection), and
the first signal comprises image data (image data) generated by the sensor (image sensor 10) (Hanzawa, fig. 1).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Hanzawa into the processor by Park so as to achieve the invention as claimed because such incorporation makes it possible suitably reduce power consumption of the imaging apparatus (Hanzawa, par [0012]).
Claims 12, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2012/0105680) and Hanzawa (US 2023/0156323) in view of Shirota (US 2016/0080652 to Shirota et al).
Regarding claim 12, Park and Hanzawa disclose aforementioned limitations of the parent claim. However, Park and Hanzawa do not disclose
the interface circuit comprises a general-purpose input/output (GPIO) pin receiving the interrupt signal.
On the other hand, in the same endeavor, Shirato discloses:
the interface circuit (interface, i.e. I2C) comprises a general-purpose input/output (GPIO) pin receiving the interrupt signal (interrupt signal) pin (GPIO pin) (Shirato, figs. 25-28, par [0070, 0153], wherein interface I2C comprises a GPIO pin for interrupt signal).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Shirato into the processor by Park and Hanzawa so as to achieve the invention as claimed because such incorporation improves input and output communication.
Regarding claim 14, Park and Hanzawa disclose aforementioned limitations of the parent claim. However, Park and Hanzawa do not disclose
the interface circuit uses, for receiving the image data, a communication protocol of serial peripheral interface (SPI), inter-integrated circuit (I2C), or improved inter-integrated circuit (I3C).
On the other hand, in the same endeavor, Shirato discloses:
the interface circuit (interface, i.e. I2C) uses, for receiving the image data, a communication protocol of serial peripheral interface (SPI), inter-integrated circuit (I2C), or improved inter-integrated circuit (I3C) (Shirato, figs. 25-28, par [0070, 0153], wherein interface I2C comprises a GPIO pin for interrupt signal).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Shirato into the processor by Park and Hanzawa so as to achieve the invention as claimed because such incorporation improves input and output communication.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2012/0105680) in view of Shirota (US 2016/0080652 to Shirota et al).
Regarding claim 19, Park discloses aforementioned limitations of the parent claim. However, Park does not disclose
the interface circuit uses a communication protocol of serial peripheral interface (SPI), inter-integrated circuit (I2C), or improved inter-integrated circuit (I3C).
On the other hand, in the same endeavor, Shirato discloses:
the interface circuit uses a communication protocol of serial peripheral interface (SPI), inter-integrated circuit (I2C), or improved inter-integrated circuit (I3C) (Shirato, figs. 25-28, par [0070, 0153], wherein interface I2C is utilized).
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Shirato into the processor by Park so as to achieve the invention as claimed because such incorporation improves input and output communication.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2012/0105680) in view of Veeder (US 2010/0213352 ).
Regarding claim 19, Park discloses aforementioned limitations of the parent claim. However, Park does not disclose
the sensor comprises an inertia sensor, a photoresistor sensor, or a voice sensor.
On the other hand, in the same endeavor, Veeder discloses:
the sensor comprises an inertia sensor, a photoresistor sensor (photoresistor sensor), or a voice sensor (Veeder, par [0030])
Therefore, it would have been obvious to an artisan before the effective filing date of the current application to incorporate the disclosure by Veeder into the processor by Park so as to achieve the invention as claimed because such incorporation enhances system versatility.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN H LE whose telephone number is (571)270-1130. The examiner can normally be reached Mon-Fri 9:00 am- 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at 5712727372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUAN H LE/Examiner, Art Unit 2638
/LIN YE/Supervisory Patent Examiner, Art Unit 2638
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