Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 20230169641(hereinafter Lee) in view of Wang et al. US 20250322507 (hereinafter Wang).
Regarding claim 1, Lee provides for obtaining a printed solder paste image of a printed circuit board, wherein the printed circuit board is determined as having defective solder paste printing ( see [0006], see “ generating a first segmentation image from a reference scanning electron microscope (SEM) image without a defect and a second segmentation image from a defect SEM image with the defect, with respect to a learning semiconductor element”) wherein the determining is performed by an automated optical inspection apparatus ( see [0006], see “a deep learning-based defect detection method for a semiconductor element”; using a classification model to classify the printed solder paste image, wherein the
classification model is a deep learning model ( see [0006], see “classifying a type of the defect in the learning semiconductor element according to at least one among a color and an aspect ratio of the defect”); when the classification model classifies a plurality of image features of the printed solder paste image corresponding to one or more soldering point areas on the printed circuit board as good solder paste printing (see [0033], see “classifying the type of the defect, and generating the defect detection model by using deep learning and detecting the defect of the semiconductor element by using a defect detection process using the defect detection model”), Examiner interprets that the effect detection model detects all of the semiconductor elements and detect (shows) the defected ones).
Lee does not provide for extracting a plurality of soldering point window images corresponding to each of the soldering point areas from the printed solder paste image; and using the classification model to determine whether each of the soldering point window images indicates that one or more corresponding soldering point areas can be classified as having good solder paste printing.
Wang teaches the above missing limitation (see [0047] of Wang, see “The RPN is shown in FIG. 4 as two network layers, but is not limited to this. After prediction, a category 410 and a bounding box 412 of the circuit board image 402 are determined. The category 410 indicates that a region within the bounding box 412 has a defect. The bounding box 412 covers a portion of the circuit board image 402 (only a local region is shown) to obtain the first defect region 414, wherein the bounding box 412 is indicated by a solid white line. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teaching of Wang with the system and method of Lee in order to obtain the claimed invention, via the RPN is used for determining a region of interest including a defect, a finding that one of ordinary skill in the art would have recognized that the result of the combination were predictable (MPEP 2143).
Regarding claim 6, see the rejection of claim 1. It recites similar limitations as claim 6. Except for, memory for storing computer instruction and a processor (see [0034] and [0052] of Lee. Hence it is similarly analyzed and rejected.
Allowable Subject Matter
2. Claims 2-5 and 7-10 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Reasons for Allowance
3. The following is an examiner’s statement of reasons for allowance: the prior arts of Lee et al. US 20230169641 in view of Wang et al. US 20250322507, failed to teach or suggest for features/limitations of claims 2-5 and 7-10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Adler et al. US 20210010953 is cited because the reference teaches “As another example, the system may flag a solder joint as a possible defective solder joint by comparing the X-ray image of that solder joint to the reference model but could not be 100% sure that it is a defective solder joint”, see [0073].
AHN et al. US 20250217255 is cited because the reference teaches “In embodiments for images of products, the classes may represent respective types of defects that occur during the manufacturing process of the products. For example, the classes may be contamination, foreign substances, broken, state of soldering marks (balls), character abnormality, and/or the like”, see [0046].
NORMAN et al. US 20220120698 is cited because the reference teaches “[0002] This application relates generally to the technical field of defect detection, and more particularly, to defect detection within semiconductor systems”.
Contact Information
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/ALI BAYAT/ Primary Examiner, Art Unit 2677
