DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application 19/025512 filed on January 16, 2025 in which Claims 1-20 are presented for examination.
Status of Claims
Claims 1-20 are pending, of which Claims 1-20 are rejected under 103.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 29, 2025 was filed after the mailing date of the Application on January 16, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on February 2, 2025 was filed after the mailing date of the Application on January 16, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-9, 11-16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Butcher (US Patent 10,152,264) in view of Brandyberry (US Patent Application 2008/0270827).
Claim 1, Butcher teaches a processor (View Butcher Col. 10, Line 60 – Col. 11, Line 25; processor), comprising: a control circuit (View Butcher Col. 6, Lines 31-48; NVDIMM controller), and wherein the processor is communicatively connected to a reset-safe non-volatile storage medium (View Butcher Col. 10, Line 60 – Col. 11, Line 25; self-refresh mode; memory subsystem includes processor); and store the related information in the reset-safe non-volatile storage medium (View Butcher Col. 10, Line 60 – Col. 11, Line 25; update NVDIMM).
Butcher does not explicitly teach a first register, and a cache; and the control circuit is configured to: obtain a reset indication, wherein the reset indication is an indication generated when the processor runs abnormally, obtain related information of the processor based on the reset indication, wherein the related information comprises at least one of register information of the first register or data stored in the cache.
However, Brandyberry teaches a first register (View Brandyberry ¶ 8, 9, 22; update CPU register), and a cache (View Brandyberry ¶ 8, 9, 22; cache); and the control circuit is configured to: obtain a reset indication, wherein the reset indication is an indication generated when the processor runs abnormally (View Brandyberry ¶ 8, 9; uncorrectable error in COU, reboot CPU), obtain related information of the processor based on the reset indication, wherein the related information comprises at least one of register information of the first register or data stored in the cache (View Brandyberry ¶ 8, 9; retrieve error data from CPR registers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Butcher with a first register, and a cache; and the control circuit is configured to: obtain a reset indication, wherein the reset indication is an indication generated when the processor runs abnormally, obtain related information of the processor based on the reset indication, wherein the related information comprises at least one of register information of the first register or data stored in the cache since it is known in the art that a processor can be reset (View Brandyberry ¶ 8, 9). Such modification would have allowed processor reset information to be stored.
Claim 8 is the method corresponding to the processor of Claim 1 and is therefore rejected under the same reasons set forth in the rejection of Claim 1.
Claim 15 is the device corresponding to the processor of Claim 1 and is therefore rejected under the same reasons set forth in the rejection of Claim 1.
Claim 2, most of the limitations of this claim has been noted in the rejection of Claim 1. Brandyberry further teaches the processor further comprises a second register, the second register is a register used when the processor runs, the first register is configured to record register information of the second register, the first register is a reset-safe non-volatile register, and the reset indication indicates to reset the processor (View Brandyberry ¶ 4, 7, 17; dump selected system registers); and the control circuit is configured to indicate, based on the reset indication, the first register to stop recording the register information of the second register, and after the processor is reset based on the reset indication, obtain the register information of the first register (View Brandyberry ¶ 18; error data retrieved from CPU registers; hard reset).
Claim 9 is the method corresponding to the processor of Claim 2 and is therefore rejected under the same reasons set forth in the rejection of Claim 2.
Claim 16 is the device corresponding to the processor of Claim 2 and is therefore rejected under the same reasons set forth in the rejection of Claim 2.
Claim 4, most of the limitations of this claim has been noted in the rejection of Claim 1. Brandyberry further teaches the processor has a reset pin, and the reset pin is configured to generate the reset indication and transmit the reset indication to the control circuit (View Brandyberry ¶ 4; hard reset).
Claim 18 is the device corresponding to the processor of Claim 4 and is therefore rejected under the same reasons set forth in the rejection of Claim 4.
Claim 5, most of the limitations of this claim has been noted in the rejection of Claim 1. Brandyberry further teaches the control circuit is communicatively connected to a reset circuit, and the reset circuit is configured to send the reset indication to the control circuit (View Brandyberry ¶ 14, 18; program code enabled to hard reset).
Claim 19 is the device corresponding to the processor of Claim 5 and is therefore rejected under the same reasons set forth in the rejection of Claim 5.
Claim 6, most of the limitations of this claim has been noted in the rejection of Claim 1. Butcher further teaches the reset-safe non-volatile storage medium comprises at least one of a reset-safe non-volatile memory inside the processor, a non-volatile storage medium inside the processor, a reset-safe non-volatile memory outside the processor, or a non-volatile storage medium outside the processor (View Butcher Col. 10, Line 60 – Col. 11, Line 25; NVDIMM self-refresh mode).
Claim 13 is the method corresponding to the processor of Claim 6 and is therefore rejected under the same reasons set forth in the rejection of Claim 6.
Claim 20 is the device corresponding to the processor of Claim 6 and is therefore rejected under the same reasons set forth in the rejection of Claim 6.
Claim 7, most of the limitations of this claim has been noted in the rejection of Claim 1. Brandyberry further teaches the control circuit is further configured to: after the processor is reset, obtain the related information from the reset-safe non-volatile storage medium, and generate a running abnormality record based on the related information (View Brandyberry ¶ 7, 17; error register, recover error data from the processor registers).
Claim 14 is the method corresponding to the processor of Claim 7 and is therefore rejected under the same reasons set forth in the rejection of Claim 7.
Claim 11, most of the limitations of this claim has been noted in the rejection of Claim 8. Brandyberry further teaches the processor has a reset pin, and the method further comprises: generating, by the processor, the reset indication via the reset pin (View Brandyberry ¶ 4; hard reset); and transmitting, by the processor, the reset indication to the control circuit via the reset pin; and the obtaining a reset indication comprises: receiving the reset indication (View Brandyberry ¶ 14, 18; program code enabled to hard reset).
Claim 12, most of the limitations of this claim has been noted in the rejection of Claim 8. Brandyberry further teaches the control circuit is communicatively connected to a reset circuit, and the reset circuit is configured to send the reset indication to the control circuit (View Brandyberry ¶ 4; hard reset); and the obtaining a reset indication comprises: receiving the reset indication sent by the reset circuit (View Brandyberry ¶ 14, 18; program code enabled to hard reset).
Claim(s) 3, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Butcher (US Patent 10,152,264) in view of Brandyberry (US Patent Application 2008/0270827) and further in view of Henry (US Patent Application 2011/0202796).
Claim 3, most of the limitations of this claim has been noted in the rejection of Claim 2. The combination of teachings does not explicitly teach the second register comprises at least one of a program counter (PC), a stack pointer (SP), a frame pointer (FP), a control register (CR), or a link register (LR).
However, Henry teaches the second register comprises at least one of a program counter (PC), a stack pointer (SP), a frame pointer (FP), a control register (CR), or a link register (LR) (View Henry ¶ 21; control register).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with the second register comprises at least one of a program counter (PC), a stack pointer (SP), a frame pointer (FP), a control register (CR), or a link register (LR) since it is known in the art that a processor can be reset (View Henry ¶ 21). Such modification would have allowed processor reset information to be stored in a register.
Claim 10 is the method corresponding to the processor of Claim 3 and is therefore rejected under the same reasons set forth in the rejection of Claim 3.
Claim 17 is the device corresponding to the processor of Claim 3 and is therefore rejected under the same reasons set forth in the rejection of Claim 3.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Sekigawa et al. (U.S. Patent 7,817,537); teaches the backup CPU executes the processing by functioning as the Web server such as those described above while the main CPU is operating normally. However, when a failure occurs in the main CPU (CPU detects its failure and resets the CPU to restart), the backup CPU terminates the Web server program to serve as the main CPU and executes the above-describe switching processing and switching command transfer processing which have been executed by the CPU.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAI E BUTLER whose telephone number is (571)270-3823. The examiner can normally be reached 8 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARAI E BUTLER/Primary Examiner, Art Unit 2114