Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 11,232,049. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims 1-20 fall entirely within the scope of claims 1-13 of U.S. Patent No. 11,232,049. The elements in claims 1-20 of the current application and the corresponding elements in claims 1-13 of U.S. Patent No. 11,232,049 are substantially the same and therefore the instant claims 1-20 are obvious over claims 1-13 of U.S. Patent No. 11,232,049.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12,229,060. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims 1-20 fall entirely within the scope of claims 1-16 of U.S. Patent No. 12,229,060. The elements in claims 1-20 of the current application and the corresponding elements in claims 1-16 of U.S. Patent No. 12,229,060 are substantially the same and therefore the instant claims 1-20 are obvious over claims 1-16 of U.S. Patent No. 12,229,060.
For example, claim 1 of U.S. Patent No. 11,232,049 and claim 1 of U.S. Patent No. 12,229,060 teach claim 1 of the present application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roberts(US 2018/0113628).
Regarding claim 1, Roberts discloses a memory device, comprising: at least one interface device(Figure 1, Serdes 170A) configured to: communicate data for the memory device such that the data is configured to bypass at least one external processor(Figure 1, Host 05A) of a computing device(Paragraph 24, Ports 230A-B are coupled to other memory modules via SerDes links. Serial data is sent to and received from other memory modules via ports 230A-B without host involvement); and at least one arbiter(Figure 2, Arbiter 220) configured to: arbitrate access to the data when at least one controller(Figure 2, Control unit 210A) of the memory device and the at least one external processor of the computing device attempt to access the data(Paragraph 25, Arbiter/switch unit 220 is configured to arbitrate between requests received on ports 230A-B with requests received from host 205 on interface 215).
Regarding claim 2, Roberts discloses memory device of claim 1, wherein the at least one interface device is further configured to: communicate the data for the memory device such that the data is configured to bypass a data bus(Paragraph 24, Ports 230A-B are coupled to other memory modules via SerDes links. Serial data is sent to and received from other memory modules via ports 230A-B without host involvement).
Regarding claim 3, Roberts discloses memory device of claim 1, wherein the at least one arbiter is further configured to: resolve a conflict between the at least one controller and the at least one external processor of the computing device when access to the data is attempted(Paragraph 25, Arbiter/switch unit 220 is configured to arbitrate between requests received on ports 230A-B with requests received from host 205 on interface 215).
Regarding claim 5, Roberts discloses memory device of claim 1, further comprising: a first bus(Figure 2, internal DDR/HBM bus) connectable as part of a second bus(Figure 2, external DDR/HBM bus) to which the at least one external processor(Figure 2, Host 205) is connected; and at least one memory chip(Figure 2, HBM 210) connected to the first bus(Figure 2, DDR/HBM bus).
Regarding claim 6, Roberts discloses memory device of claim 5, wherein the at least one arbiter is further configured to: queue memory requests to the at least one memory chip in order of processing(Paragraph 25, Arbiter/switch unit 220 is configured to arbitrate between requests received on ports 230A-B with requests received from host 205 on interface 215. In one embodiment, requests received from host 205 on interface 215 are processed with a higher priority than requests received on ports 230A-B).
Regarding claim 7, Roberts discloses memory device of claim 5, wherein the at least one arbiter comprises a part of the at least one memory chip(Paragraph 12, Each memory module includes one or more memory devices, a buffer chip, an arbiter, and multiple interfaces).
Regarding claim 8, Roberts discloses memory device of claim 1, wherein the at least one arbiter comprises a part of the at least one controller(Paragraph 12, Each memory module includes one or more memory devices, a buffer chip, an arbiter, and multiple interfaces).
Regarding claim 9, Roberts discloses memory device of claim 1, wherein the at least one arbiter is further configured to: arbitrate the data communicated over a bus and at least one connection that bypasses the bus(Paragraph 25, Arbiter/switch unit 220 is configured to arbitrate between requests received on ports 230A-B with requests received from host 205 on interface 215).
Regarding claim 10, Roberts discloses memory device of claim 1, further comprising: a printed circuit board; and at least one electrical contact positioned on a side of the printed circuit board(Paragraph 17, memory modules 110A-B and 115A-B are dual in-line memory modules (DIMMs)).
Regarding claim 11, Roberts discloses memory device of claim 1, wherein at least one computation of the at least one controller is coordinated by at least one external controller(Paragraph 22, Host 205 includes memory controller 207 with logic for writing and reading to memory devices 210A-N).
Regarding claim 12, Roberts discloses memory device of claim 1, where at least one communication of the at least one interface device is coordinated by at least one external controller(Paragraph 22, Host 205 includes memory controller 207 with logic for writing and reading to memory devices 210A-N).
Regarding claim 13, Roberts discloses a system, comprising: a memory module, comprising: at least one interface device configured to: provide data for the memory module such that the data is configured to bypass a first data bus in communication with the memory module(Paragraph 24, Ports 230A-B are coupled to other memory modules via SerDes links. Serial data is sent to and received from other memory modules via ports 230A-B without host involvement); and at least one arbiter configured to: control access to the data when at least one controller of the memory module and at least one processor external to the memory module attempt to access the data(Paragraph 25, Arbiter/switch unit 220 is configured to arbitrate between requests received on ports 230A-B with requests received from host 205 on interface 215).
Regarding claim 14, Roberts discloses system of claim 13, wherein the at least one interface device is further configured to: communicate the data for the memory module such that the data is configured to bypass the at least one processor(Paragraph 24, Ports 230A-B are coupled to other memory modules via SerDes links. Serial data is sent to and received from other memory modules via ports 230A-B without host involvement).
Regarding claim 15, Roberts discloses system of claim 13, further comprising: a printed circuit board configured for insertion into a memory slot associated with the memory module(Paragraph 17, memory modules 110A-B and 115A-B are dual in-line memory modules (DIMMs)).
Regarding claim 16, Roberts discloses system of claim 13, wherein the at least one arbiter is further configured to: resolve a conflict between the at least one controller and the at least one first processor when the at least one controller and the at least one first processor attempt to access the data(Paragraph 25, Arbiter/switch unit 220 is configured to arbitrate between requests received on ports 230A-B with requests received from host 205 on interface 215).
Regarding claim 17, Roberts discloses system of claim 13, further comprising: a second bus connectable to the first bus to which the at least one processor is connected(Figure 2, external DDR/HBM bus is connected to the internal DDR/HBM bus).
Regarding claim 18, Roberts discloses system of claim 13, wherein the memory module further comprises at least one connection configured to connect a plurality of memory chips to at least one electrical contact to communicate the data(Paragraph 12, Each memory module includes one or more memory devices, a buffer chip, an arbiter, and multiple interfaces).
Regarding claim 19, Roberts discloses a method, comprising: communicating, by utilizing at least one interface device of a memory device, data for the memory device such that the data is configured to bypass at least one external processor(Paragraph 24, Ports 230A-B are coupled to other memory modules via SerDes links. Serial data is sent to and received from other memory modules via ports 230A-B without host involvement); and: arbitrating, by utilizing at least one arbitrator of the memory device, access to the data when at least one controller of the memory device and the at least one external processor attempt to access the data(Paragraph 25, Arbiter/switch unit 220 is configured to arbitrate between requests received on ports 230A-B with requests received from host 205 on interface 215).
Regarding claim 20, Roberts discloses method of claim 19, further comprising communicating the data for the memory device such that the data is configured to bypass a data bus(Paragraph 24, Ports 230A-B are coupled to other memory modules via SerDes links. Serial data is sent to and received from other memory modules via ports 230A-B without host involvement).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts and Brower(US 2014/0149969).
Regarding claim 4, Roberts does not specifically disclose the at least one interface device further comprises at least one wireless interface device configured to communicate at least in part wirelessly over at least one wireless communication network. However, Brower discloses a card comprising at least one wireless interface device that communicates at least in part wirelessly(Paragraph 91). It would have been obvious to one of ordinary skill in the art and before the effective filing date to combine the teachings of Roberts and Brower to at least one interface device further comprises at least one wireless interface device configured to communicate at least in part wirelessly over at least one wireless communication network. The motivation to do so would be communicate wirelessly.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMESH G PATEL whose telephone number is (571)272-3640. The examiner can normally be reached on Monday-Friday, 8:15-4:15.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NIMESH G PATEL/ Primary Examiner, Art Unit 2185
Prosecution Insights