DETAILED ACTION
FINAL REJECTION
Response to Arguments
Applicant's arguments filed 09/04/26 have been fully considered but they are not Persuasive. This action is responsive to the Applicant's amendments filed on 09/04/26. Claims 1-20 remain pending in the application. Claims 1, 8, and 14 have been amended. Any examiner's note, objection, and rejection not repeated is withdrawn due to Applicant's amendment.
Applicants’ Argument:
Hashimoto fail to disclose invention screening of defective memory units in a memory system and further Hashimoto fails to disclose monitoring an error rate in reading data from the memory cells; and screen the memory cells for defects in response to the error rate, as claimed by Applicant in independent Claim 1 and the other independent claims.
The Examiner respectfully disagrees:
Hashimoto in col. 9, lines 43-62 describes in the case that the read is performed to the same block many times, the electric field is applied to the tunnel oxide film of the memory cell many times. As a result, the electrons are injected to the floating gate electrode of the unselected memory cell to shift the threshold voltage, and possibly the written data of the unselected memory cell is lost. The fluctuation in threshold voltage of the unselected memory cell during the read operation is referred to as read disturb, and the data breakage of the unselected memory cell due to the read disturb is referred to as a read disturb failure (a read disturb error). A failure rate of the read disturb failure is susceptible to the state of the tunnel oxide film or floating gate electrode of the memory cell, and the failure rate fluctuates largely depending on the block or NAND memory chip. Therefore, it is necessary that the block having a high disturb failure rate be detected and marked as a bad block before the shipment of the SSD, and that the SSD controller 2 be prevented from accessing the bad block. Desirably the SSD having the high read disturb failure rate is determined to be a defective product and is not shipped. Further, Hashimoto in col. 11, lines 2-67 teaches a test method (the screening operation) of the first embodiment will be described below. When the self-running mode starts, the SSD controller 2 performs the screening operation to the NAND flash memory 3 (NAND screening). In the NAND screening, the NAND flash memory 3 is aged (worn out) by repeating the erase, program, and write of the block, and a block failure that possibly becomes an initial failure is detected before shipment (reliability acceleration). The SSD controller 2 marks the block, in which failures such as the erase error, the write error, and an uncorrectable ECC error (a read error) are detected, as the bad block (registers the block in the bad block management table 3D), thereby previously preventing the user from using the block that possibly causes the failure in the future. The SSD controller or the test device 100 determines the SSD having many failures, and reports or records a test result such that the SSD is not shipped. Therefore, the user is previously prevented from using the SSD having the high failure rate. Because the host device 10 is not required during the NAND screening in which the SSD 1 is operated in the self-running mode, desirably only a power supply device 40 is connected to the SSD 1 as illustrated in FIG. 8 from the viewpoint of reducing cost of a NAND screening apparatus. Specifically, the SSD 1 is connected to the power supply device 40 through the power supply line 12. The interface 11 is not connected to the outside. Thus, the NAND screening can be performed only by preparing the inexpensive power supply device 40 as the external power supply for the SSD. Therefore, the applicants’ argument although acknowledged, has not been found to be convincing and in light of the above, the final rejection holds strong in view of the recited reference (Hashimoto). Applicants are also advised to review Hashimoto reference in its entirety for a complete and better understanding of the prior art applied. This may enhance the Applicants ability to formulate claim language that includes novelty of the application. It is the Examiner's conclusion that the claims of the present application, as presented, are not patentably distinct or novel over the prior arts of record. Applicants are encouraged to formulate claim language that clearly differentiates the claims from the prior art of record.
Furthermore, the response does not specifically point out disagreements to overcome 112 and 101 rejections in view of the amendments. Therefore, all the rejection is maintained and in addition to that the examiner would like to point out that claims 1-20 of the present application are still obvious variations of claims 1-20 Of U.S. PNs: 10,777,295, 11,430,540, and 12,512,177 not patentable distinct. The examiner would like to point out that this action is final.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of non-statutory obviousness-type double
patenting as being unpatentable over claims 1-20 of U.S. Patent Numbers:
12512177, 11430540, and 10,777,295.
For example, claim 1 of the present application teaches “A device, comprising: memory cells; and a logic circuit coupled to the memory cells and configured to: monitor an error rate in reading data from the memory cells; and, screen the memory cells for defects in response to the error rate reaching a threshold” Whereas claim 1 of U.S. PN: 10,777,295 “A memory system, comprising: non-volatile media having a set of memory units; a controller configured to process requests from a host system to store data in the non- volatile media or retrieve data from the non-volatile media; wherein the memory system stores an indicator indicating whether the memory system is operating in a user mode or a manufacturing mode; and wherein a defect manager of the memory system identifies a threshold based on the indicator, monitors an error rate in reading data from the non-volatile media and, in response to the error rate reaching the threshold, screens the non-volatile media for defective memory units”.
The instant application is a broader version of claim 1 of U.S. Patent No. 10,777,295, and several limitations in patented claim 1 have removed from the instant application of claim 1. Thus, claim 1 of the instant application may be considered as defining a broader genus version of the species defined in claim 1 of U.S. Patent No. 10,777,295. Therefore, the claims are obvious variations of each other and not patentably distinct.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi. 759 F.2d at 896, 225
USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue
were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at
1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent
application claim to a genus is anticipated by a patent claim to a species within that genus). ELI
LILLY AND COMPANY V BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Other parallel dependent claims of the instant application have corresponding issues
with the dependent claims of U.S. patent no. 10,777,295 are also rejected under
non-statutory obviousness-type double patenting =
Dependent claims of the instant application are deemed obvious over the dependent claims U.S. patent no. 10,777,295 for the same rationales discussed above.
For example, claim 1 of the present application teaches "A device, comprising: memory cells; and a logic circuit coupled to the memory cells and configured to: monitor an error rate in reading data from the memory cells; and, screen the memory cells for defects in response to the error rate reaching a threshold" Whereas claim 1 of U.S. PN: 11,430,540 "A device, comprising: a controller of a memory system having non-volatile media, the controller configured to: determine a current mode of operation of the memory system, the current mode being selected from a plurality of predefined modes; and a defect manager configured to: identify a threshold based on the current mode of operation of the memory system; determine that an error rate in reading data from non-volatile media of the memory system is above the threshold; and screen, responsive to the error rate reaching the threshold, the non-volatile media for defective memory units".
The instant application is a broader version of claim 1 of U.S. Patent No. 11,430,540, and several limitations in patented claim 1 have removed from the instant application of claim 1. Thus, claim 1 of the instant application may be considered as defining a broader genus version of the species defined in claim 1 of U.S. Patent No. 11,430,540. Therefore, the claims are obvious variations of each other and not patentably distinct.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is
obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225
USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue
were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at
1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent
application claim to a genus is anticipated by a patent claim to a species within that genus). ELI
LILLY AND COMPANY V BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Other parallel dependent claims of the instant application have corresponding issues with the dependent claims of U.S. patent no. 11,430,540 are also rejected under non-statutory obviousness-type double patenting
Dependent claims of the instant application are deemed obvious over the dependent claims U.S. patent no. 11,430,540 for the same rationales discussed above.
For example, claim 1 of the present application teaches "A device, comprising:
memory cells: and a logic circuit coupled to the memory cells and configured to: monitor
an error rate in reading data from the memory cells; and screen the memory cells for
defects in response to the error rate reaching a threshold " Whereas claim 1 of (U.S. PN: 12,512,177) "A device, comprising: memory cells; and a logic circuit coupled to the memory cells and configured to: monitor an error rate in reading data from the memory cells; identify a
manufacturing mode threshold, in response to the memory system operating in the
manufacturing mode; screen the memory cells for defects in response to the error rate
reaching the manufacturing mode threshold; identify a user mode threshold, in response to the memory system operating in the user mode; and screen the memory cells for defective memory units in response to the error rate reaching a user mode threshold; wherein the manufacturing mode threshold is lower than the user mode threshold".
The instant application is a broader version of claim 1 of U.S. Patent No. 12,512,177, and several limitations in patented claim 1 have removed from the instant application of claim 1. Thus, claim 1 of the instant application may be considered as defining a broader genus version of the species defined in claim 1 of U.S. Patent No. 12,512,177. Therefore, the claims are obvious variations of each other and not patentably distinct.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is
obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225
USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue
were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at
1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent
application claim to a genus is anticipated by a patent claim to a species within that genus). ELI
LILLY AND COMPANY V BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Other parallel dependent claims of the instant application have corresponding issues
with the dependent claims of U.S. patent no. 12,512,177 are also rejected under
non-statutory obviousness-type double patenting
Dependent claims of the instant application are deemed obvious over the dependent
claims U.S. patent no. 12,512,177 for the same rationales discussed above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or
A joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out
and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second
paragraph, as being indefinite for failing to particularly point out and distinctly claim the
subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards
as the invention.
Claims 1, 8, and 15 recite the limitation "determining or monitoring an error rate in reading data from memory cells of the memory cells; and in response to the error rate, screening the memory cells for defective memory cells reaching a threshold ".
There is no clear criteria for determining or monitoring error rate and screening the memory cells for defective memory cells, "determining or monitoring error rate and screening the memory cells for defective memory cells" attempts to define the subject matter in terms of the result to be achieved, which merely amounts to a statement of underlying problem, without providing the technical features necessary for achieving the result. Further, the claims are vague with respect to how this determination or monitoring is done as well as this ties into the preceding screening step.
Dependent claims depend on the base claims and inherently include limitations therein and therefore are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph
as well.
Applicants are encouraged to review all claims and make corrections as needed to clarify claim language. Corrections are requested.
Claim Rejections -35 USC § 101
35. U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or
composition of matter, or any new and useful improvement thereof, may obtain a patent
Therefore, subject to the conditions and requirements of this title.
Claim 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed
to an abstract idea without significantly more.
Claim 15:
A method comprising: determining an error rate in reading data from memory cells of the
memory system is above the threshold; and in response to the error rate being above the
threshold, screening the memory cells for defective memory cells.
Claim 15 is directed to an abstract idea mathematical concept. The inventive concept
appears to be an improvement to the abstract idea itself (determining of an error rate and
screening memory cells for defect based on the error rate - mathematical concept).
The claims does/do not include additional elements that are sufficient to
amount to significantly more than the judicial exception.
This claim recited no additional elements and there is nothing to amount to significantly
more than the judicial exception within the claims. The steps merely refer to the calculations
which cannot provide an inventive concept. Thus claim 1 is not eligible.
The determination of error rate for screening memory defects is something that could
be done mentally or on pen and paper since there is simply a difference between error rates and
the screening threshold,
The claims(s) do not include additional elements that are sufficient to amount to
significantly more than the judicial exception because compute as recited is a generic computer
component that performs functions (i.e., determining of an error rate and screening memory
cells for defect). These are generic computer functions (i.e., "screening memory cells for defect
based on determining of an error rate) that are well-understood, routine, and conventional
activities previously known to the industry. The claim also recites a device, a logic circuit, and
computer storage medium (as in independent claims 1 and 8), which do not add meaningful
limitations to the idea of intermediate settlement beyond generally linking the system to a
technological environment, that is, implementation via computers. The claim does not
amount to significantly more than the underlying abstract idea of intermediate settlement.
Therefore, claim 1 and 8 are rejected for similar reasons.
Dependent claims do not add anything significantly more to the independent claims and
Therefore, they are rejected as well.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AJA 35 U.S.C. 102 and 103) is incorrect, any correction
of the statutory basis for the rejection will not be considered a new ground of rejection if
the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the
basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a) (1) the claimed invention was patented, described in a printed publication, or in
public use, on sale, or otherwise available to the public before the effective filing date
of the claimed invention.
Claims 1, 2, 8, and 15-17 are rejected under 35 U.S.C. 102(a) (1) as being anticipated
by Hashimoto (U.S. PN: 9,032,264).
As per claim 1:
Hashimoto substantially teaches or discloses a device, comprising memory cells and a
logic circuit coupled to the memory cells (see figure 1 and col. 3, lines 30-67 to col. 4, lines 1-7) and configured to: monitor an error rate in reading data from the memory cells and, screen the memory cells for defects in response to the error rate (see col. 9, lines 43-62, col. 11, lines 2-67 to col. 12, lines 1-27, col. 17, lines 44-67 to col. Col. 18, lines 1-7, col. 18, lines 55-67 to col. 19, lines 1-48 and col. 29, lines 41-67 to col. 30, lines 1-67).
As per claim 2:
Hashimoto in view of the above rejection teaches wherein the memory cells comprise of
a flash memory of a memory system that is a solid-state drive; and the memory system
communicates with a host system over a communication channel in accordance with a
communication protocol for peripheral component interconnect express bus (see figure 1 and col.
3, lines 30-67 to col. 4, lines 1-7).
As per claim 8:
Hashimoto substantially teaches or discloses a non-transitory computer storage medium
storing instructions which, when executed by a memory system having memory cells, and a logic
circuit, cause the logic circuit (see figure 1 and col. 3, lines 30-67 to col. 4, lines 1-7) to perform
a method: method comprising determining if an error rate in reading data from memory cells
of the memory system is above a threshold; and in response to the error rate being above a
threshold, screening the memory cells for defective memory (see col. 9, lines 43-62, col. 11,
lines 2-67 to col. 12, lines 1-27, col. 17, lines 44-67 to col. Col. 18, lines 1-7, col. 18, lines 55-67
to col. 19, lines 1-48 and col. 29, lines 41-67 to col. 30, lines 1-67).
As per claim 15:
Hashimoto substantially teaches or discloses a method comprising: determining an error rate in reading data from memory cells of the memory system; and in response to the error rate being above the threshold, screening the memory cells for defective memory cells (see col. 9, lines 43-62, col. 11, lines 2-67 to col. 12, lines 1-27, col. 17, lines 44-67 to col. Col. 18, lines 1-7, col. 18, lines 55-67 to col. 19, lines 1-48 and col. 29, lines 41-67 to col. 30, lines 1-67).
As per claim 16:
Hashimoto in view of the above rejection teaches where in the memory cells comprise of a flash memory (see figure 1 and col. 3, lines 30-67 to col. 4, lines 1-7).
As per claim 17:
Hashimoto in view of the above rejection teaches wherein the memory system is a solid-
state drive (see figure 1 and col. 3, lines 30-67 to col. 4, lines 1-7).
Examiner's Note
The Examiner cites particular columns, paragraphs, figures, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may also apply. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 3-7, 9-14, and 18-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. However, such an allowance is conditioned on the resolution of all of the identified rejections based upon 35 U.S.C. 112 and 35 USC 101, in the base and intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kantipudi (U.S. PN: 10,446,251) teaches a method of screening for configuration related defects in integrated circuits is provided. To detect configuration defects, test pattern configuration data and error correction data for that test pattern are loaded into configuration memory. Existing cyclic redundancy check circuitry on the integrated circuit is recruited to compute check-sum signatures based on the data stored in each frame of the memory array. Defects in configuration memory cells and configuration- related circuitry are identified by comparing the error correction data of frame to the computed check-sum signature of a frame. Localized freezing of programmable logic associated with configuration memory is optionally applied to eliminate data contention and ensure maximum coverage of the memory array during screening. Several test patterns of configuration data are also provided.
Lee et al. (US 2017/0098478) teach a method provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word line; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.
Navon et al. (U.S. PN: 9,483,339) describe programming a sample population of memory cells with test data; subsequently reading the sample population of memory cells to obtain read data; comparing the read data and the test data to identify a number of bad bits in the read data; calculating a bit error rate for the sample population from the number of bad bits in the sample population; and extrapolating the calculated bit error rate to user data stored in memory cells outside the sample population (see col. 3, lines 43-52).
Frayer et al. (U.S. PN: 8,976,609) describe depending on the circumstances, bad regions may include a single word line or a group (e.g., a plurality) of word lines. In various circumstances, the bad regions may be completely unusable as-manufactured, may have been manufactured with defects such that they failed a burn-in test, may have an unacceptably high bit error rate (BER), and/or have a combination of these problems. In addition, in some embodiments, the bad regions are sub-units of the die planes (e.g., the bad regions are blocks of memory, or word lines of memory, or even pages of memory).
Cornwell et al. (U.S. PN: 7,609,561) teach a flash memory package may include any practical number of flash memory dies, such as two, three, four, eight, or sixteen, for example. The flash memory package 110 includes four flash memory dies 115a, 115b, 115c, and 115d. During its manufacture, the flash memory package 110 may be tested. In some implementations, the tests may return test performance, such as a test score, for at least one flash memory die. Based on the test performance, some of the flash memory dies in the package may be identified to be defective according to a set of criteria, such as bit error rate, for example.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
Prosecution Insights