DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-3, 9 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Nair et al. (US 2018/0286840)(hereafter Nair) in view of Chen et al. (US 2014/0002188)(hereafter Chen).
Regarding claims 1, Nair discloses a packaged module comprising:
a package substrate (see, para [0022]); a system-on-a-chip (SoC) supported by the package substrate (see, Fig. 2, the SOC chip, 215); a crystal stacked with the SoC (see, para [0036], bottom package, 210 with crystal oscillator); and a front end integrated circuit that is integrated with the package substrate (see, Fig. 1, the top package, 105, see, para [0039], the second/top package 305 contains multiple embedded electronic components, which may include one or more packaged components, one or more active components or integrated circuits (U9 and U1 in this example), and one or more passive components (capacitors C20 and C21 and inductor L1 in this example). but does not explicitly disclose: the front end integrated circuit including an amplifier configured to amplify a radio frequency signal. However, in same field of endeavor, Chen teaches [0703], The die 618 can include an integrated circuit (e.g., power amplifier circuit) having one or more transistors 648; and such a circuit can be controlled from an external circuit, as for example, through terminal 659. [0835] The die 774 can be a power amplifier die embodied in a single Gallium Arsenide (GaAs) Microwave Monolithic Integrated Circuit (MMIC) that includes all active circuitry of the module 770. Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Chen with the Nair as a whole, so as to incorporate the power amplifier circuit in the integrated circuit, the motivation is to amplify the signal.
Regarding claim 2, Nair further discloses the packaged module wherein the crystal has a smaller footprint than the SoC (see, Figs. 1 and 2, the Fig. 5, the crystal, 540 as shown).
Regarding claim 3, Nair further discloses the packaged module wherein the SoC is disposed between the crystal and the package substrate (see, Figs 2-4, the SOC module, 215 is disposed between the bottom package, 210 having crystal oscillator and motherboard, 450 which is substrate).
Regarding claim 9, Nair further discloses the packaged module wherein the SoC includes a microprocessor, radio frequency transmitter circuitry, and radio frequency receiver circuitry (see, Fig. 9, the Rx/Tx, 932, processor, 924).
Regarding claim 20, the combined teachings as a whole further discloses all the limitations of the claim 20, Nair further discloses an antenna in communication with the amplifier (see, para [0075]).
Regarding claim 21, Nair further discloses 21. The wireless communication device of claim 20 wherein the wireless communication device is an Internet of things device. (see, para [0075]).
Regarding claim 22, the combined teachings as a whole further discloses all the limitations of the claim 20, Nair further discloses a system board and other components on the system board (see, para [0004]. [0022]).
Claim(s) 4, 5, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nair and Chen and further in view of Park (US 2014/0232477)(hereafter Park).
Regarding claim 4, the combined teachings do not disclose the packaged module further comprising one or more load capacitors, the crystal and the one or more load capacitors being included in a crystal oscillator, and the SoC being disposed between the one or more load capacitors and the package substrate. however, In same field of endeavor, Park teaches a crystal and one or more load capacitors supported by a substrate (paragraph 0088: in an alternative embodiment, the sealed quartz oscillator 10 may be formed on the substrate 201. Paragraph 0073: A circuit diagram of the sealed quartz oscillator 10 may be as illustrated in FIG. 3. Capacitors Cg and Cd may be connected to both ends of the quartz blank 150, thus representing "one or more load capacitors". Further, since substrate 201 supports all components, the capacitors are also directly or indirectly supported by the substrate). Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Park with the Nari and Chen, as a whole, so as to use crystal assembly structure disposed between the SOC and package substrate, to yield predictable results.
Regarding claim 5, the combined teachings do not discloses the packaged module wherein the crystal is included in a crystal assembly, and the crystal assembly is disposed between the SoC and the package substrate, however, In same field of endeavor, Park teaches a crystal and one or more load capacitors supported by a substrate (paragraph 0088: in an alternative embodiment, the sealed quartz oscillator 10 may be formed on the substrate 201. Paragraph 0073: A circuit diagram of the sealed quartz oscillator 10 may be as illustrated in FIG. 3. Capacitors Cg and Cd may be connected to both ends of the quartz blank 150, thus representing "one or more load capacitors". Further, since substrate 201 supports all components, the capacitors are also directly or indirectly supported by the substrate). Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Park with the Nari and Chen, as a whole, so as to use crystal assembly structure disposed between the SOC and package substrate, to yield predictable results.
Regarding claim 7, Nair does not explicitly discloses the packaged module wherein the front end integrated circuit is disposed on a same side of the package substrate as the crystal and the SoC, However, Park in paragraph 0020 teaches that the integrated circuit chip may comprise a plurality of stacked integrated circuit chips. Similar arrangement is also shown in Fig. 8 with a description in paragraph 0092 describing a plurality of integrated circuit chips 210 and 210b which may be stacked in mirror type. Further, as stated in paragraph 0093, a sealed quartz oscillator 10 may still be formed on the package substrate 201, as shown in Fig. 6. Therefore, it would have been obvious to one skilled in the art to combine the teachings of Park with the Nair and Chen to dispose front end circuit on a same side of the package substrate as the crystal and the SoC, as its merely design choice to arrange components so as to keep front end circuit same side of the package substrate as the crystal and SOC, so as to yield predictable results as this does not alter the operation of the device, also, one can be motivated to do so to reduce the number of wires or connectors to connect the components on same side of circuit. since, according to the Supreme Court, "[t]the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results." KSR Int'l Co. V. Teleflex, Inc., 550See, MPEP, 2144, VI, also, In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
Regarding claim 8, the combined teachings do not explicitly disclose the packaged module of claim 1 wherein the front end integrated circuit is disposed on an opposite side of the package substrate as the crystal and the SoC. However, its merely design choice to arrange components so as to keep front end circuit opposite side of the package substrate as the crystal and SOC, so as to yield predictable results as this does not alter the operation of the device, also, one can be motivated to do so to reduce the overcrowding of the components on the one side to dissipate the power. See, MPEP, 2144, VI, In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
8. Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nair, Chen and Park and further in view of England et al. (US 2013/0037802) (hereafter England).
Regarding claim 6, the combined teachings do not disclose the packaged module of claim 5 wherein the crystal assembly includes a conductive pillar and an enclosure, the conductive pillar extending from a top surface to a bottom surface of the enclosure, and the enclosure enclosing the crystal , however, in same field of endeavor, England teaches in para [0004], [0004] The provider of the logic die or the SoC die conventionally mounts their device to an interposer, such as a ball grid array (BGA) substrate, the logic or SoC die including conductive through vias for connection to the conductive pillars on the underside of the MPGA. The MPGA is mounted to the logic die or SoC die on the interposer, and the assembly is then over molded with an encapsulant into a finished BGA package. Therefore, it would have been obvious to one of ordinary skilled in the art before to combine the teachings of England with the Nair, Chen and Park, as a whole, so as to use the conductive pillar extending from top to bottom surface of enclosure, the motivation is to provide thermal conductivity.
9. Claim(s) 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nair and Chen and further in view of Wang et al. (US 2016/0164476)(hereafter Wang).
Regarding claim 10, the combined teachings do not disclose the packaged module wherein the amplifier is a low noise amplifier that includes a first inductor, an amplification circuit, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier. However, in same field of endeavor, However, in same field of endeavor, Wang teaches a front end system comprising: a low noise amplifier (see, Fig. 3, 300 LNA) in a receive path of the front end system, the low noise amplifier including a first inductor (see, Fig. 3, 302a), an amplification circuit (see, Fig. 3, 304, transistor are amplification circuit), and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier (see, Fig. 3, 310b, second inductor, see abstract, the second inductor magnetically coupled to the first inductor which is interpreted as provide negative feedback to linearize the low noise amplifier, see, paragraph [0032], coupling the inductor, 302 to the inductors 308 and 310 improve the linearity of the amplifier and thus interpreted as linearize the low noise amplifier); a power amplifier in a transmit path of the front end system (see, fig. 2, the LNA, 240pa is power amplifier at the front end). Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Wang with the Chiu, as a whole, so as to incorporate the structure of front end components having the radio frequency structure and separate from antenna outside the shielding structure on the package substrate, the motivation is to meet the linearize standards and reduce the outside interference of the RF components from the external environment.
Regarding claim 11, the combined teachings further discloses the packaged module of claim 10 wherein the low noise amplifier includes a series inductor having a first end configured to receive the radio frequency signal and a second end electrically coupled to the first inductor (Wang teaches a front end system comprising: a low noise amplifier (see, Fig. 3, 300 LNA) in a receive path of the front end system, the low noise amplifier including a first inductor (see, Fig. 3, 302a), an amplification circuit (see, Fig. 3, 304, transistor are amplification circuit), and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier (see, Fig. 3, 310b, second inductor, see abstract, the second inductor magnetically coupled to the first inductor which is interpreted as provide negative feedback to linearize the low noise amplifier, see, paragraph [0032], coupling the inductor, 302 to the inductors 308 and 310 improve the linearity of the amplifier and thus interpreted as linearize the low noise amplifier); a power amplifier in a transmit path of the front end system (see, fig. 2, the LNA, 240pa is power amplifier at the front end).
10. Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nair and Chen and further in view of Borodulin et al. (US 6188277)(hereafter Boroudin).
Regarding claim 12, the combined teachings do not disclose the packaged module wherein the amplifier is a low noise amplifier, and the front end integrated circuit includes a switch and an overload protection circuit configured to adjust an impedance of the switch based on a signal level of the low noise amplifier. However, Borodulin teaches in Fig. 1, switch, (20) having an analog control input (input of 20) operable to control an impedance of the input switch (20), a low noise amplifier (PA to PA-N) which is configured to provide amplification to a RF input signal (RF INPUT) received from the input switch (20), and an overload protection circuit (62, 64, 74, 76, M.C.) which is configured to provide feedback to the analog control input (input of 20) of the input switch (20) based on a detected signal level (VP2, VP3) of the low noise amplifier (PA to PA-N). Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention before the effective filing date of the claimed invention to combine the teachings of Borodulin with the Wang, as a whole, so as to adjust the impedance of the switch based on the overload current condition of the low noise amplifier, the motivation is to providing protection for the system.
11. Claim(s) 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nair and Chen and further in view of Eldesouki et al (US2012/0274409) (hereafter Eldesouki).
Regarding claim 16, the combined teachings do not disclose the packaged module of claim 1wherein the amplifier includes an injection-locked oscillator power amplifier driver stage. However, in same field of endeavor, Eldesouki teaches injection locking based on a power amplifier in which [0005] In one aspect, a method includes inputting a reference signal through an injection circuit of an oscillator circuit that generates an output signal of high power that oscillates at an inherent frequency of oscillation of the oscillator circuit. accordance with its respective amplifier gain. Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Eldesouki with Nair and Chen, as a whole, so as to electrically connect the output of the injection-locked oscillator to the output stage with the supply voltage, the motivation is to generate the amplified output voltage.
Allowable Subject Matter
17. Claims 13-15 and 17-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
18. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kojo (US 9831414) discloses surface mounted piezoelectric vibrator.
Wallis (U S9825597) discloses impedance transformation circuit for amplifiers.
Nguyen et al. (US 2017/0301986) discloses selectively shielding radio frequency module with multi-layer antenna.
Van Zeijl et al. (US 2015/0222012) discloses radiofrequency module.
Sun et al. (US 2015/0187300) discloses driving circuit of LCD panel, the LCD panel and device.
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/DHAVAL V PATEL/Primary Examiner, Art Unit 2631
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