Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/7/2025 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 2-3, 5-10, 12-17 and 19-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,314,582 in view of Norgren (US 7,739,470).
19/025,830
US Patent No. 12,314,582
2. A method by a memory system, comprising:
selecting a compensation parameter based at least in part on determining that a bandwidth of a backend of the memory system satisfies one or more performance criteria, wherein the one or more performance criteria are based at least in part on a performance between the memory system and a host system; and
allocating a quantity of one or more slots of a buffer to a frontend of the memory system based at least in part on the compensation parameter.
A method, comprising:
determining that a bandwidth of a backend of a memory system satisfies one or more performance criteria that are based at least in part on performance between the memory system and a host system that is external to the memory system; and
allocating a quantity of one or more slots of a buffer to a frontend of the memory system based at least in part on determining that the bandwidth of the backend satisfies the one or more performance criteria.
Regarding claims 2, 9 and 16, Patent 12,314,582 discloses determining that a bandwidth of a backend of the memory system satisfies one or more performance criteria, wherein the one or more performance criteria are based at least in part on a performance between the memory system and a host system; and allocating a quantity of one or more slots of a buffer to a frontend of the memory system based at least in part on the compensation parameter [see table above].
The patent does not expressly disclose selecting a compensation parameter and allocating a quantity of one or more slots of a buffer based at least in part on the compensation parameter.
Norgren discloses a I/O queue based memory system in which a queue depth adjustment (compensation parameter) may be determined and selected in order to increase the depth/size of an I/O queue [see Col. 17, lines 23-57].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the queue depth adjustment determination of Norgren in the 12,314,582 Patent.
The motivation for doing so would have been to achieve a selected performance goal [see Norgren, Col. 17 lines 64-66].
Therefore, it would have been obvious to combine Norgren with Patent 12,314,582 for the benefits listed above, to obtain the invention as specified in claims 2-3, 5-10, 12-17 and 19-20.
Regarding claims 3, 10 and 17, the combination discloses determining a quantity of valid blocks of a transfer unit of the memory system, wherein determining the bandwidth of the backend of the memory system is based at least in part on the quantity of valid blocks of the transfer unit [see Patent 12,314,582; claims 7 and 17].
Regarding claims 5, 12 and 19, the combination discloses the bandwidth is based at least in part on a quantity of commands processed by the backend over a duration and a quantity of occupied slots of the buffer that are allocated to the frontend [see Patent 12,314,582; claims 11 and 19].
Regarding claims 6, 13 and 20, the combination discloses the quantity of the one or more slots of the buffer is based at least in part on the compensation parameter [see Norgren, Col. 17, lines 23-67; amount to expand I/O queue based on queue depth adjustment].
Regarding claims 7, 14 and 21, the combination discloses the compensation parameter is associated with a desired performance level of the memory system [see Norgren, Col. 17, lines 23-67; I/O queue adjustment based on selected performance goal].
Regarding claims 8 and 15, the combination discloses the one or more slots of the buffer allocated to the frontend of the memory system are configured to store access commands received from the host system or data associated with the access commands [see Norgren, Col. 17, lines 23-67; I/O queue stores data associated with commands].
Claims 2-3, 5-10, 12-17 and 19-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,520,502 in view of Norgren (US 7,739,470).
19/025,830
US Patent No. 11,520,502
2. A method by a memory system, comprising:
selecting a compensation parameter based at least in part on determining that a bandwidth of a backend of the memory system satisfies one or more performance criteria, wherein the one or more performance criteria are based at least in part on a performance between the memory system and a host system; and
allocating a quantity of one or more slots of a buffer to a frontend of the memory system based at least in part on the compensation parameter.
1. A method, comprising:
monitoring a bandwidth of a backend of a memory sub-system for writing data to a memory device;
determining that the bandwidth of the backend satisfies one or more performance criteria that are based at least in part on performance between the memory sub-system and a host system that is external to the memory sub-system; and
allocating a quantity of one or more slots of a buffer to a frontend of the memory sub-system based at least in part on determining that the bandwidth of the backend satisfies the one or more performance criteria.
Regarding claims 2, 9 and 16, Patent 11,520,502 discloses determining that a bandwidth of a backend of the memory system satisfies one or more performance criteria, wherein the one or more performance criteria are based at least in part on a performance between the memory system and a host system; and allocating a quantity of one or more slots of a buffer to a frontend of the memory system based at least in part on the compensation parameter [see Patent 11,520,502; claims 1, 11 and 20].
The patent does not expressly disclose selecting a compensation parameter and allocating a quantity of one or more slots of a buffer based at least in part on the compensation parameter.
Norgren discloses a I/O queue based memory system in which a queue depth adjustment (compensation parameter) may be determined and selected in order to increase the depth/size of an I/O queue [see Col. 17, lines 23-57].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the queue depth adjustment determination of Norgren in the 11,520,502 Patent.
The motivation for doing so would have been to achieve a selected performance goal [see Norgren, Col. 17 lines 64-66].
Therefore, it would have been obvious to combine Norgren with Patent 11,520,502 for the benefits listed above, to obtain the invention as specified in claims 2-3, 5-10, 12-17 and 19-20.
Regarding claims 3, 10 and 17, the combination discloses determining a quantity of valid blocks of a transfer unit of the memory system, wherein determining the bandwidth of the backend of the memory system is based at least in part on the quantity of valid blocks of the transfer unit [see Patent 11,520,502; claims 6 and 16].
Regarding claims 5, 12 and 19, the combination discloses the bandwidth is based at least in part on a quantity of commands processed by the backend over a duration and a quantity of occupied slots of the buffer that are allocated to the frontend [see Patent 11,520,502; claims 10 and 19].
Regarding claims 6, 13 and 20, the combination discloses the quantity of the one or more slots of the buffer is based at least in part on the compensation parameter [see Norgren, Col. 17, lines 23-67; amount to expand I/O queue based on queue depth adjustment].
Regarding claims 7, 14 and 21, the combination discloses the compensation parameter is associated with a desired performance level of the memory system [see Norgren, Col. 17, lines 23-67; I/O queue adjustment based on selected performance goal].
Regarding claims 8 and 15, the combination discloses the one or more slots of the buffer allocated to the frontend of the memory system are configured to store access commands received from the host system or data associated with the access commands [see Norgren, Col. 17, lines 23-67; I/O queue stores data associated with commands].
Claims 2-3, 6-10, 13-17 and 20-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,899,948 in view of Norgren (US 7,739,470).
19/025,830
US Patent No. 11,899,948
2. A method by a memory system, comprising:
selecting a compensation parameter based at least in part on determining that a bandwidth of a backend of the memory system satisfies one or more performance criteria, wherein the one or more performance criteria are based at least in part on a performance between the memory system and a host system; and
allocating a quantity of one or more slots of a buffer to a frontend of the memory system based at least in part on the compensation parameter.
1. A method, comprising:
monitoring, by one or more processing cores of a memory sub-system, a bandwidth of a backend of the memory sub-system for writing data to a memory device, wherein the bandwidth is based at least in part on a quantity of commands processed by the backend of the memory sub-system over a duration and a quantity of occupied slots of a buffer associated with a frontend of the memory sub-system, wherein the slots of the buffer are configured to receive data from the frontend for writing to the memory device by the backend;
determining, by the one or more processing cores, that the bandwidth of the backend satisfies one or more performance criteria that are based at least in part on performance between the memory sub-system and a host system that is external to the memory sub-system;
transmitting signaling to the host system based at least in part on determining that the bandwidth of the backend satisfies the one or more performance criteria, wherein the signaling comprises instructions for the host system to continue transmitting access commands to the memory sub-system; and
allocating, by the one or more processing cores, a quantity of one or more slots of the buffer to the frontend of the memory sub-system based at least in part on determining that the bandwidth of the backend satisfies the one or more performance criteria and transmitting the signaling to the host system, wherein the quantity of slots allocated for the buffer associated with the frontend is based at least in part on the bandwidth relative to the one or more performance criteria.
Regarding claims 2, 9 and 16, Patent 11,899,948 discloses determining that a bandwidth of a backend of the memory system satisfies one or more performance criteria, wherein the one or more performance criteria are based at least in part on a performance between the memory system and a host system; and allocating a quantity of one or more slots of a buffer to a frontend of the memory system based at least in part on the compensation parameter [see Patent 11,899,948; claims 1, 11 and 20].
The patent does not expressly disclose selecting a compensation parameter and allocating a quantity of one or more slots of a buffer based at least in part on the compensation parameter.
Norgren discloses a I/O queue based memory system in which a queue depth adjustment (compensation parameter) may be determined and selected in order to increase the depth/size of an I/O queue [see Col. 17, lines 23-57].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the queue depth adjustment determination of Norgren in the 11,899,948 Patent.
The motivation for doing so would have been to achieve a selected performance goal [see Norgren, Col. 17 lines 64-66].
Therefore, it would have been obvious to combine Norgren with Patent 11,899,948 for the benefits listed above, to obtain the invention as specified in claims 2-3, 5-10, 12-17 and 19-20.
Regarding claims 3, 10 and 17, the combination discloses determining a quantity of valid blocks of a transfer unit of the memory system, wherein determining the bandwidth of the backend of the memory system is based at least in part on the quantity of valid blocks of the transfer unit [see Patent 11,899,948; claims 6 and 16].
Regarding claims 6, 13 and 20, the combination discloses the quantity of the one or more slots of the buffer is based at least in part on the compensation parameter [see Norgren, Col. 17, lines 23-67; amount to expand I/O queue based on queue depth adjustment].
Regarding claims 7, 14 and 21, the combination discloses the compensation parameter is associated with a desired performance level of the memory system [see Norgren, Col. 17, lines 23-67; I/O queue adjustment based on selected performance goal].
Regarding claims 8 and 15, the combination discloses the one or more slots of the buffer allocated to the frontend of the memory system are configured to store access commands received from the host system or data associated with the access commands [see Norgren, Col. 17, lines 23-67; I/O queue stores data associated with commands].
REASONS FOR ALLOWANCE
Claims 2-21 recite allowable subject matter, provided the above double patenting rejections are overcome.
Claims 4, 11 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record including the disclosure of Fillingim (US 2012/0066439) generally teaches managing a lifetime of a storage device by throttling write operations on a data storage device in response to a write bandwidth failing to meet a target. Jinzaki (US 2001/0014936) generally teaches a FIFO memory implemented as an elastic buffer to adjust a transfer rate and a processing rate. Daglis (2018/0173673) generally teaches allocating one or more of a plurality of buffer slots in a buffer pool to a write buffer as write buffer slots or to a read buffer as read buffer slots memory system to provide optimal read and write performance. However, none of the prior art of record anticipates nor renders obvious the claim limitations directed towards allocating one or more slots of a buffer of the frontend of a memory system based on a compensation parameter, when a bandwidth of a backend of the memory system satisfies performance criteria between the memory sub-system and a host.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure generally teach:
Yun (US 2019/0250858) – Generally teaches adjusting the capacities of input buffers and output buffers to increase throughput in a memory controller.
Creed (US 2021/0365379) – Generally teaches a cache slot allocation system in which cache slots of a front-end may be allocated based on an expected amount of time the data will remain in the cache slot as write pending. The filing data of Creed, however, is after the filing date of application 16/731,936, which the current application is a continuation of and claims priority from.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137