Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/15/2025 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 12236125. Although the claims at issue are not identical, they are not patentably distinct from each other because they claim modifying a value of a counter that is for the state of metadata bits that is assigned to a set of memory cells.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Di Vincenzo et al. (U.S. Publication No. 2021/0225454 A1), hereafter referred to as DiVincenzo’454.
Referring to claim 1, DiVincenzo’454 as claimed, a method, comprising: modifying a value of a counter that is for a state of metadata bits assigned to a set of memory cells in a memory system based at least in part on the metadata bits assigned to the set of memory cells being the state at receipt of an access command (a count of memory cells equals the number of memory cells in the pre-defined logic state as retrieved from the BIT COUNTER 395, see paras. [0068], [0073], [0075] and Fig. 3); and transmitting state information for the set of memory cells that is based at least in part on the value of the counter (retrieved from the BIT COUNTER 395, see paras. [0068], [0084], [0086]).
As to claim 2, DiVincenzo’454 also discloses receiving the access command for the set of memory cells; and determining the state of the metadata bits based at least in part on receiving the access command (receiving the command, see para. [0033]), wherein modifying the value of the counter is based at least in part on determining the state of the metadata bits (determines a number of bits in the predefined state (e.g. how many bits are stored in the memory cells as a logic 1 state, for example). When the encoded/manipulated DATA and PARITY are written to the memory cells, the associated bit-flip information is stored in the codeword encoder region and the number of bits in the predefined state is stored in the associated bit counter region, see para. [0059]; the number of bits in a pre-defined logic state is counted and stored in the codeword bit counter 395 for future use at a subsequent access operation, see para. [0076] and Fig. 9).
As to claim 3, DiVincenzo’454 also discloses the value of the counter indicates a quantity of commands received for the set of memory cells with the metadata bits in the state (receive commands and data, see para. [0040]; a count of memory cells equals the number of memory cells in the pre-defined logic state as retrieved from the BIT COUNTER 395, see paras. [0068], [0073], [0075] and Fig. 3; also note: accumulator counts how many cells are in a predetermined logic state, see paras. [0073]-[0075]; codeword bit counter, see paras. [0075], [0076], [0080]).
As to claim 4, DiVincenzo’454 also discloses configuring a set of counters (accumulator counts how many cells are in a predetermined logic state, see paras. [0073]-[0075]; codeword bit counter, see paras. [0075], [0076], [0080]) prior to modifying the value of the counter, wherein the counter is included in the set of counters (N represents the number of bits expected to be in the predefined logic state (e.g. the value in CODEWORD BIT COUNTER), see para. [0124]; also note: expected number, see para. [0094]).
As to claim 5, DiVincenzo’454 also discloses each counter of the set of counters is associated with a respective state of the metadata bits assigned to the set of memory cells and indicates a respective quantity of commands received for the set of memory cells with the metadata bits in the respective state (a count of memory cells equals the number of memory cells in the pre-defined logic state as retrieved from the BIT COUNTER 395, see paras. [0068], [0073], [0075] and Fig. 3; also note: accumulator counts how many cells are in a predetermined logic state, see paras. [0073]-[0075]; codeword bit counter, see paras. [0075], [0076], [0080]).
As to claim 6, DiVincenzo’454 also discloses configuring the set of counters further comprises: setting each counter of the set of counters to a value (N represents the number of bits expected to be in the predefined logic state (e.g. the value in CODEWORD BIT COUNTER), see para. [0124]; also note: expected number, see para. [0094]); assigning each counter of the set of counters to a respective set of memory cells of the memory system (a count of memory cells equals the number of memory cells in the pre-defined logic state as retrieved from the BIT COUNTER 395, see paras. [0068], [0073], [0075] and Fig. 3; also note: cells in memory array or other memory cells, see para. [0059]; first plurality of memory cells and second plurality of memory cells, see para. [0063] and Fig. 4); and assigning each counter of the set of counters to the respective state of the metadata bits assigned to the respective set of memory cells, wherein modifying the value of the counter is based at least in part on assigning each counter of the set of counters the respective state of the metadata bits (a count of memory cells equals the number of memory cells in the pre-defined logic state as retrieved from the BIT COUNTER 395, see paras. [0068], [0073], [0075] and Fig. 3; also note: accumulator counts how many cells are in a predetermined logic state, see paras. [0073]-[0075]; codeword bit counter, see paras. [0075], [0076], [0080]).
As to claim 7, DiVincenzo’454 also discloses modifying the metadata bits assigned to the set of memory cells based at least in part on a type of the access command (when the encoded/manipulated DATA and PARITY are written to the memory cells, the associated bit-flip information is stored in the codeword encoder region and the number of bits in the predefined state is stored in the associated bit counter region, see paras. [0059]-[0067], Figs. 4 and 5).
As to claim 8, DiVincenzo’454 also discloses adjusting the value of the counter based at least in part on the metadata bits assigned to the set of memory cells being equal to metadata bits associated with the counter (count of memory cells equals the number of memory cells in the pre-defined logic state as retrieved from the BIT COUNTER, see paras. [0068], [0084]- [0086], [0109]).
Note claim 15 recites similar limitations of claim 1. Therefore it is rejected based on the same reason accordingly.
Note claim 16 recites similar limitations of claim 4. Therefore it is rejected based on the same reason accordingly.
Note claim 17 recites similar limitations of claim 6. Therefore it is rejected based on the same reason accordingly.
Note claim 18 recites similar limitations of claim 3. Therefore it is rejected based on the same reason accordingly.
Note claim 19 recites similar limitations of claim 2. Therefore it is rejected based on the same reason accordingly.
Note claim 20 recites similar limitations of claim 8. Therefore it is rejected based on the same reason accordingly.
Claim(s) 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HUTCHISON et al. (U.S. Publication No. 2020/0341688 A1), hereafter referred to as HUTCHISON’688.
Referring to claim 9, HUTCHISON’688 as claimed, a method, comprising: receiving, from a device coupled with a memory system, a message that comprises an identifier for a command and indicates an operation performed by the device (instructions are received and processed by the controller 102…the controller 102 communicates with the host according to PCIe, SAS, SCSI, SATA, NVMe, NVMEeoF, etc. (e.g. completions are sent), see para. [0025]); conventionally and implicitly disclosed is that a solid state drive would report [service of a command and] “non-service”, see para. [0037], [0039], [0048]); stopping a timer associated with a type of the operation based at least in part on receiving the message (command latency is the amount of time taken by the system to service a command, see para. [0037]); and transmitting, to a host system and based at least in part on a latency for the operation associated with stopping the timer, latency information for the type of the operation (sending a message to a host that a latency threshold has been exceeded or expected completion latency, see paras. [0056]-[0058], [0062]).
As to claim 10, HUTCHISON’688 also discloses starting, at the memory system, the timer for the command to initiate the operation at the device based at least in part on the timer being assigned to the type of the operation, wherein determining the latency is based at least in part on starting the timer (a timer is started when the command is added to the heap, see paras. [0043], [0049], Fig. 2).
As to claim 11, HUTCHISON’688 also discloses determining that the timer associated with the type of operation is stopped; and storing a transaction identifier for the command in a register associated with the timer based at least in part on determining that the timer is stopped (command latency is the amount of time taken by the system to service a command, see para. [0037]), wherein starting the timer is based at least in part on storing the transaction identifier for the command (a timer is started when the command is added to the queue/heap, see paras. [0043], [0049], [0061], and Fig. 2).
As to claim 12, HUTCHISON’688 also discloses checking a value of a register associated with the memory system prior to receiving the message; and determining whether the timer assigned to the type of the operation is started based at least in part on checking the value of the register (starting a timer when the command is added to the queue, wherein a value of the timer is set according to a required latency threshold, see paras. [0049], [0051]; timestamping commands received, see paras. [0011], [0056], [0061], and Fig. 2).
As to claim 13, HUTCHISON’688 also discloses the latency information is based at least in part on the latency for the operation (a latency threshold has been exceeded or expected completion latency, see paras. [0056]-[0058], [0062]).
As to claim 14, HUTCHISON’688 also discloses the device comprises a memory device (solid state drive used in a computer or a swerver including NAND flash memory, see para. [0024]), the method further comprising: receiving the command from the host system, wherein the message is received based at least in part on receiving the command (command is received, see paras. [0046], [0049], [0050] and Fig. 3A-B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
BENISTY (U.S. Publication No. 2021/0042039 A1) discloses a data storage device for adaptive command completion posting.
YU et al. (U.S. Publication No. 2022/0292033 A1) discloses a memory device with internal processing interface.
TOKUTOMI et al. (U.S. Publication No. 2022/0044738 A1) discloses a memory system including a nonvolatile memory with a memory cell array including cell units each with memory cells and a memory controller.
Noyes et al. (U.S. Publication No. 2017/0261956 A1) discloses a counter operation in a state machine lattice.
PYEON (U.S. Publication No. 2013/0010562 A1) discloses DRAM device and method for self-refreshing memory cells with temperature compensated self-refresh.
Klein (U.S. Publication No. 2014/0112087 A1) discloses power management control and controlling memory refresh operations.
Xu et al. (U.S. Publication No. 2015/0046889 A1) discloses state grouping for element utilization.
YUN et al. (U.S. Publication No. 2022/0101931 A1) discloses a method of operation a memory device that includes stages each having page buffers and performing a verify operation of a program loop from program loops.
Pan et al. (U.S. Publication No. 2017/0221568 A1) discloses methods to read memory cells based on clock pulse counts.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TITUS WONG whose telephone number is (571)270-1627. The examiner can normally be reached Monday-Friday, 10am-6pm.
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/TITUS WONG/Primary Examiner, Art Unit 2181
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