DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2, 6, 11 and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hahn et al. [US 10,572,185 B2].
Regarding claim 2, Hahn teaches “A method by a memory system, comprising:” as “A memory system includes a non-volatile memory and a controller connected to the non-volatile memory. ” [Abstract]
“storing, at a first queue, an indication of a set of transfer units for one or more media management operations in accordance with an order of a first set of read commands, wherein the first set of read commands is associated with the set of transfer units;” as “An NVMe command (e.g. Read or Write) is initiated at the host and sent to a particular submission queue that lives in host memory. Once the command is inserted into a queue, the host writes to a per-queue doorbell register on the controller.” [Col 7, lines 4-10]
“updating, at the first queue and in response to receiving a set of read responses corresponding to a second set of read commands, one or more values associated with one or more transfer units of the set of transfer units, wherein the one or more transfer units are associated with the second set of read commands;” as “The controller maintains the head pointer and begins to read the queue once notified of the tail pointer update. It can continue to read the queue until empty. As it consumes entries, the head pointer is updated, and sent back to the host via completion queue entries.” [Col 7, line 65-col 8, line 2]
“buffering, in accordance with the one or more values associated with the one or more transfer units, a set of write commands corresponding to the set of read responses; and” as “ In step 550, in response to fetching the command, Controller 102 updates the Submission Head Pointer (SQHP0) on Controller 102. The Submission Head Pointer (SQHP0) will be sent back to the host via the Completion Queue, as discussed below. ” [Col 10, lines 50-56]
“issuing the set of write commands in accordance with the order of the one or more transfer units stored at the first queue.” as “ The host sends a set features command 1628 to set features of the memory system. In a fourth stage, Begin I/O 1630, a host submits read and write commands to I/O queues 1632.” [Col 16, lines 60-64]
Regarding claim 6, Hahn teaches “wherein the first queue is a linked list, a ring buffer, a circular buffer, a tree, or any combination thereof.” as “A submission queue (SQ) is a circular buffer with a fixed slot size that the host software uses to submit commands for execution by the controller. ” [Col 7, lines 29-31]
Claim 11 is rejected over Hahn under the same rationale of anticipation of claim 2.
Claim 15 is rejected over Hahn under the same rationale of anticipation of claim 6.
Claim 19 is rejected over Hahn under the same rationale of anticipation of claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al. [US 10,572,185 B2] in view of Subbarao et al. [US 2020/0004701 A1].
Claim 7 is rejected over Hahn and Subbarao.
Hahn does not explicitly teach wherein buffering the set of write commands further comprises: storing the set of write commands at a write buffer.
However, Subbarao teaches “wherein buffering the set of write commands further comprises: storing the set of write commands at a write buffer.” as “In storage device 120, RDMA interface 304 and buffer memory 306, in conjunction with coordination from SVC 110, may allow host 102 to send the data to be stored in the host write command to buffer memory 306 in storage device 120 without them passing through SVC 110 or another storage controller.” [¶0089]
Hahn and Subbarao are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn and Subbarao before him/her, to modify the teachings of Hahn to include the teachings of Subbarao with the motivation of disaggregated storage brings significant cost savings via decoupling compute and storage node life cycles and allowing different nodes or subsystems to have different compute to storage ratios. [Subbarao, ¶0003]
Claim 21 is rejected over Hahn and Subbarao.
Hahn does not explicitly teach wherein issuing the set of write commands comprises: issuing the set of write commands, wherein the set of write commands transfer the valid data from the one or more transfer units to one or more second transfer units in accordance with the order of the first set of read commands.
However, Subbarao teaches “wherein issuing the set of write commands comprises: issuing the set of write commands, wherein the set of write commands transfer the valid data from the one or more transfer units to one or more second transfer units in accordance with the order of the first set of read commands.” as “request handler 212 may be configured to receive commands from a host (e.g. host 102 in FIG. 1) via host interface 206, such as host read commands and host write commands.” [¶0058]
Hahn and Subbarao are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn and Subbarao before him/her, to modify the teachings of Hahn to include the teachings of Subbarao with the motivation of disaggregated storage brings significant cost savings via decoupling compute and storage node life cycles and allowing different nodes or subsystems to have different compute to storage ratios. [Subbarao, ¶0003]
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al. [US 10,572,185 B2] in view of Shapiro. [US 2005/0198062 A1].
Claim 8 is rejected over Hahn and Shapiro.
Hahn does not explicitly teach wherein the one or more values associated with the one or more transfer units indicate a respective status of a respective transfer unit of the one or more transfer units, wherein the status may indicate that a lookup request has been issued for a respective transfer unit, a lookup response has been received for a respective transfer unit, a respective transfer unit contains valid data, a read command has been issued for a respective transfer unit, a read response has been received for a respective transfer unit, or a write command has been issued for a respective transfer unit.
However, Shapiro teaches “wherein the one or more values associated with the one or more transfer units indicate a respective status of a respective transfer unit of the one or more transfer units, wherein the status may indicate that a lookup request has been issued for a respective transfer unit, a lookup response has been received for a respective transfer unit, a respective transfer unit contains valid data, a read command has been issued for a respective transfer unit, a read response has been received for a respective transfer unit, or a write command has been issued for a respective transfer unit.” as “the write (or read commands) may be passed directly to the memory cache 26 and/or write cache 28 which can then perform a CAT lookup operation (if provided with a copy of the CAT tables) or the caches 26, 28 may issue a CAT lookup request to the DBIC 22.” [¶0039]
Hahn and Shapiro are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn and Shapiro before him/her, to modify the teachings of Hahn to include the teachings of Shapiro with the motivation of on average, the DBIC may be expected to deliver data faster than the network storage system. [Shapiro, ¶0041]
Claim 16 is rejected over Hahn and Shapiro under the same rationale of rejection of claim 8.
Claim(s) 9-10 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al. [US 10,572,185 B2] in view of Bolkhovitin et al. [US 2019/0294339 A1].
Claim 9 is rejected over Hahn and Bolkhovitin.
Hahn does not explicitly teach wherein a first read response of the set of read responses is received prior to a second read response of the set of read responses and wherein issuing the set of write commands further comprises: issuing a first write command of the set of write commands, the first write command corresponding to the second read response; and issuing, after the first write command and in accordance with the order of the first set of read commands, a second write command of the set of write commands.
However, Bolkhovitin teaches “wherein a first read response of the set of read responses is received prior to a second read response of the set of read responses and wherein issuing the set of write commands further comprises: issuing a first write command of the set of write commands, the first write command corresponding to the second read response; and issuing, after the first write command and in accordance with the order of the first set of read commands, a second write command of the set of write commands.” as “In some embodiments, after transfer of read data from buffers 150 to the requesting host system using RDMA, in the case of read commands, and after notification of execution completion in the case of write commands, the completed command is removed from completion queue.” [¶0075]
Hahn and Bolkhovitin are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn and Bolkhovitin before him/her, to modify the teachings of Hahn to include the teachings of Bolkhovitin with the motivation of communication bus effectively replaces network for communications between the host systems/servers. [Bolkhovitin, ¶0055]
Claim 10 is rejected over Hahn and Bolkhovitin.
Hahn does not explicitly teach receiving a second set of write commands, wherein buffering the set of write commands is in accordance with reception of the second set of write commands, and wherein issuance of the set of write commands is in accordance with a completion of the second set of write commands.
However, Bolkhovitin teaches “receiving a second set of write commands, wherein buffering the set of write commands is in accordance with reception of the second set of write commands, and wherein issuance of the set of write commands is in accordance with a completion of the second set of write commands.” as “ allocates storage buffers 150 in data storage devices, and translates the host commands into data storage device commands to facilitate remote DMA transfers of data corresponding to the read and write commands between host buffers on host systems 110 and storage buffers 150 on associated data storage devices 120. ” [¶0062]
Hahn and Bolkhovitin are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hahn and Bolkhovitin before him/her, to modify the teachings of Hahn to include the teachings of Bolkhovitin with the motivation of communication bus effectively replaces network for communications between the host systems/servers. [Bolkhovitin, ¶0055]
Claim 17 is rejected over Hahn and Bolkhovitin under the same rationale of rejection of claim 9.
Claim 18 is rejected over Hahn and Bolkhovitin under the same rationale of rejection of claim 10.
Allowable Subject Matter
Claims 3-5, 12-14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 3, 12 and 20, the prior art of Hahn et al. US 10,572,185 B2, Subbarao et al. US 2020/0004701 A1, and Shapiro US 2005/0198062 A1, whether considered individually or in combination, fails to teach or suggest issuing a set of lookup requests corresponding to a set of transfer units and receiving a corresponding set of lookup responses that each explicitly indicate whether the respective transfer unit comprises valid or invalid data.
In particular, the cited references do not disclose or suggest a coordinated, per-transfer-unit lookup-response mechanism that provides validity status at the granularity of individual transfer units in response to a batch of lookup requests. Instead, the references generally describe data access, caching, or lookup operations without providing explicit validity/invalidity indications tied to each transfer unit via corresponding lookup responses as claimed.
Accordingly, the claimed subject matter, as a whole, is not rendered obvious by the cited art.
Claims 4-5 and 13-14 are objected because they are dependent on claim 3.
Conclusion
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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