DETAILED ACTION
Response to Amendment
The amendment filed 7/24/2026 has been entered. Claims 1-11, and 14-19 remain pending in the application. Applicant’s amendment has overcome the objections to the specification and the drawings set forth in the Non-Final Office Action mailed 5/26/2026 (“FAOM”), which are hereby withdrawn.
Response to Argument
Applicant's arguments, see pages 7-10 of the Remarks filed 7/24/2026 (“Remarks”), with respect to the rejections of record have been fully considered but found not persuasive. The rejection of claims 1-11, and 14-16 is maintained. In addition, new grounds of rejections have been made, which were necessitated by the applicant’s amendment.
Regarding claim 1, the applicant argues (Remarks at 8) that
Anand [misspelled as “Akash”] does not disclose that the solid-state varactors are connected via a conductive interface to any electrically controllable switch mounted at the dielectric layer. Accordingly, Anand cannot anticipate amended independent claim 1.
The examiner respectfully disagrees. As set forth in the FAOM, Anand discloses the solid-state varactors (Skyworks SMV1405) functioning as switches, mounted on a dielectric layer exposed as ring gaps, and connected to the conductive tuning pattern via their conductive interfaces (anodes and cathodes interfaces) (FAOM at 4, 6-7).
Anand uses a Rogers TMM®3 substrate comprising multiple laminated dielectric resin layers laminated with a conductive layer on both its top and bottom surfaces. Most of the substrate body laminated with the conductive layer(s), for example, bottom surface conductive layer, can be considered the claimed “dielectric block comprising a surface coated with a conductive layer.” At least portions of the top conductive layer are etched out exposing the top surface dielectric layer as ring gaps. Such portions can be considered the recited dielectric layer arranged at the dielectric block. For the foregoing reasons, Anand discloses all the limitations of the amended claim 1, as set forth in detail below.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 17-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention.
Claim 17 recites “wherein the dielectric layer attached to the dielectric block.” There is insufficient antecedent basis for the term “the dielectric layer attached to the dielectric block” because claim 1 recites “a dielectric layer arranged at the dielectric block.”
For examination purposes, this limitation will be understood to mean “wherein the dielectric layer is attached to the dielectric block.”
Claims 18-19 are also rejected under 35 U.S.C. 112(b) as dependent on the rejected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by A. Anand et al., Theory and Design of Octave Tunable Filters With Lumped Tuning Elements, IEEE Transact. on Microwave Theory and Techniques, vol. 61, no. 12, pp. 4353-4364, Dec. 2013 (“Anand”), cited by the applicant.
Anand discloses in Figs. 2, 9, 15, 18, 23-24 and the corresponding description:
Claim 1
A frequency tunable resonator (Abstract; pp. 4354, 4359, SIW surface ring gap cavity resonator with solid-state varactors as tuners), comprising:
a dielectric block (Fig. 18, p. 4359, Table III, Rogers TMM® substrate) comprising a surface coated with a conductive layer (p. 4360, Rogers TMM® substrate includes two surfaces with conductive layers, see, e.g., Rogers TMM®3 Datasheet, cited herein as a teaching reference. Most of the substrate body laminated with a conductive layer, for example, bottom surface conductive layer, can be considered the claimed dielectric block);
a dielectric layer arranged at the dielectric block (p. 4360, Rogers TMM® substrate comprises multiple laminated dielectric resin layers, with at least surface layer thereof partially exposed as ring gaps on which the varactors are surface-mounted as seen in Figs. 2, 9, 18 of Anand);
an input port configured to receive an input signal (Figs. 18, 24; CPW feed lines),
an output port configured to output an output signal (Figs. 18, 24; CPW feed lines),
a resonator arranged inside the dielectric block and being electromagnetically connected to the input port and the output port (Figs. 2, 9, 15, 18, 23-24, pp. 4354, 4359-60, SIW surface ring gap cavity resonator formed by the metallic vias inside the substrate to create the outer wall of the cavity),
at least one dielectric opening in the conductive layer delimiting a conductive tuning pattern at the surface of the dielectric block (Figs. 9, 18a, pp. 4357-4360, one ring or two ring gaps in the top conductive surface layer of the substrate), and
at least one electrically controllable switch mounted at the dielectric layer and connected to the conductive tuning pattern via a conductive interface, the at least one electrically controllable switch being configured to conductively connect a conductive tuning pattern to a conductive structure when operating in its active state (Figs. 2, 9, 18, Table III, Skyworks SMV1405 varactors are used as tunable elements, “electrically controllable switches”, connecting the rings to the conductive layer of the substrate via the varactors’ conductive interfaces, anodes and cathodes. The varactors are surface-mounted on the exposed dielectric layer. The varactors disclosed in Anand meet this limitation because the present disclosure explicitly states that the claimed “electrically controllable switch may be any suitable controllable switch known in the art, [including] a variable capacitance.” See, e.g., Specification at ¶60; claim 9),
wherein the frequency tunable resonator is configured to:
resonate at a first frequency when the electrically controllable switch is operating in its non-active state (Figs. 3, 10, 11; p. 4355, “as the varactor is tuned to a lower capacitance, the frequency will increase”; see also SMV1405 Datasheet, Fig. 1, cited herein as a teaching reference, indicating that when no reverse voltage is applied to the tuning varactor--i.e., when the varactor is in its non-active state--its capacitance is the highest and the resonator frequency is the lowest) and
resonate at a second frequency when the electrically controllable switch is operating in its active state (Figs. 3, 10, 11; p. 4355, “as the varactor is tuned to a lower capacitance, the frequency will increase”; see also SMV1405 Datasheet, Fig. 1, indicating that when a reverse voltage is applied to the tuning varactor--i.e., when the varactor is in its active state--its capacitance is the lowest and the resonator frequency is the highest).
Claim 2
wherein the conductive tuning pattern comprises a first conductive section (Fig. 18, two-ring design, the inside ring) connected to a second conductive section (the outside ring) via at least one additional electrically controllable switch (multiple varactors).
Claim 3
wherein the second conductive section is circumferentially arranged around the first conductive section (Fig. 18, the outside ring is circumferentially arranged around the inside ring).
Claim 4
wherein the conductive tuning pattern comprises a single conductive section (Figs. 2 and 9, one ring design with a single ring as a single conductive section).
Claim 5
wherein the conductive tuning pattern is coaxially arranged in relation to the resonator in the dielectric block (Figs. 2, 9, 15, 18, 23-24, pp. 4359-60, the surface rings are coaxially arranged in relations to the resonator formed by the metallic vias inside the substrate).
Claim 6
wherein the resonator is a resonator cavity comprising an opening extending inwards from the surface of the dielectric block (Figs. 2, 9, 15, 18, 23-24, pp. 4359-60, the resonator is formed by the metallic vias inside the substrate to create the outer wall of the cavity with the center via representing an opening extending inward from the surface of the dielectric substrate).
Claim 7
wherein the opening of the resonator cavity and the conductive tuning pattern are arranged on opposite surfaces of the dielectric block (Figs. 2, 9, 15, 18, 23-24, pp. 4359-60, the resonator is formed by the metallic vias inside the substrate to create the outer wall of the cavity, which is arranged on the opposite surface from the rings, i.e., conductive tuning pattern).
Claim 8
wherein the dielectric block has a cubic or a cuboid shape (Figs. 2, 9, 15, 18, 23-24).
Claim 9
wherein the electrically controllable switch is a semiconductor, a variable capacitance (Skyworks SMV1405 varactors), or a variable inductance.
Claim 10
wherein the electrically controllable switch (tuning varactors) is mounted at the dielectric block (Figs. 9, 15, 18, 23-24, tuning varactors are surface-mounted).
Claim 11
wherein the conductive layer is the conductive structure (Figs. 9, 15, 18, 23-24, conductive rings are formed on Rogers TMM® substrate conductive layers, Table III).
Claim 14
wherein the conductive structure is arranged at the dielectric layer or connected to the dielectric layer (Figs. 9, 15, 18, 23-24; p. 4360, Table III, Rogers TMM® dielectric substrate includes two surfaces with conductive layers and one or two rings formed therefrom.
Claim 15
further comprising:
at least one second resonator (Figs. 223-24, two or three resonator design);
at least one second conductive tuning pattern (each resonator comprising two conductive rings); and
at least one second controllable switch (multiple varactors),
wherein the resonator and the at least one second resonator are electromagnetically coupled to each other (Fig. 21 showing two resonators with inter-resonator coupling).
Claim 16
wherein the frequency tunable resonator comprises at least one inner cavity coated with a conductive layer and forming a wall section extending inside the dielectric block and at least partially between the resonator and the second resonator (Figs. 21, 23-24).
Claim 17 (as best understood)
wherein the dielectric layer (exposed portion of the substrate) attached to the dielectric block, wherein the electrically controllable switch is a semiconductor mounted on the dielectric layer (Figs. 2, 9, 15, 18, 23-24, pp. 4354, 4359-60, the varactors are surface-mounted on the exposed dielectric layer), and wherein the conductive interface includes at least one conductor mounted on the dielectric layer (Skyworks SMV1405 include two conductors, anode and cathode, mounted on the dielectric layer).
Claim 18
wherein the conductive interface comprises a plurality of overlapping conductors mounted on the dielectric layer (Figs. 2, 9 showing a plurality of varactors whose conductive interfaces include a plurality of conductors overlapping the conductive tuning pattern).
Claim 19
wherein the dielectric layer is attached to the dielectric block via soldering or adhesive (Rogers TMM®3 Datasheet, the topmost exposed dielectric layer of the substrate is attached to the dielectric block via adhesive).
Claims 1, 17-19 are additionally rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qin W. et al., Low-loss filtering switch by using dielectric waveguide resonators. Int’l J. RF Microw. Comp. Aided Eng. 2021, vol. 31, issue 12, pp. 1-6 (“Qin”), cited by the applicant.
Qin discloses in Figs. 1-8 and the corresponding description:
Claim 1
A frequency tunable resonator (Figs. 1, 3, Abstract, a filtering switch including dielectric waveguide resonators), comprising:
a dielectric block comprising a surface coated with a conductive layer (Fig. 3, Dielectric Part),
a dielectric layer arranged at the dielectric block (Fig. 3, PCB Board),
an input port configured to receive an input signal (Fig. 8),
an output port configured to output an output signal (Fig. 8),
a resonator (DWRs) arranged inside the dielectric block and being electromagnetically connected to the input port and the output port,
at least one dielectric opening in the conductive layer delimiting a conductive tuning pattern at the surface of the dielectric block (Fig. 1, p. 2, circular patch on the upper surface of the dielectric part), and
at least one electrically controllable switch (Fig. 1, p. 2, PIN diodes) mounted at the dielectric layer and connected to the conductive tuning pattern via a conductive interface, the at least one electrically controllable switch being configured to conductively connect a conductive tuning pattern to a conductive structure when operating in its active state (Abstract, p. 2, the switching function is realized on the PCB by simply changing the resonant frequency of the DWR),
wherein the frequency tunable resonator is configured to: resonate at a first frequency when the electrically controllable switch is operating in its non-active state (Fig. 2, p. 2, switching PIN diodes on/off), and
resonate at a second frequency when the electrically controllable switch is operating in its active state (Fig. 2, p. 2, switching PIN diodes on/off).
Claim 17 (as best understood)
wherein the dielectric layer attached to the dielectric block (Fig.1, PCB is attached to the dielectric part),
wherein the electrically controllable switch is a semiconductor mounted on the dielectric layer (p. 3, PIN diodes used are the Skyworks SMP 1340-079LF semiconductor diodes), and
wherein the conductive interface includes at least one conductor mounted on the dielectric layer (Figs. 1, 3, 8).
Claim 18
wherein the conductive interface comprises a plurality of overlapping conductors mounted on the dielectric layer (Fig. 8 showing a plurality of PIN diodes whose conductive interfaces include a plurality of conductors overlapping the conductive tuning pattern).
Claim 19
wherein the dielectric layer is attached to the dielectric block via soldering or adhesive (Abstract, the PCB board is attached by soldering).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR COLE, telephone number (571) 272-4686. The examiner can be reached Monday-Friday, 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA LINDGREN BALTZELL, can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/VICTOR COLE/
Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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