DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 5 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 5 has been amended to specify “the first command”. Paragraph 0072 states “Byway of example, the system 300 may be operating in a first power mode and may receive a command (e.g., from a host system) to transition to the second power mode. Upon receiving the command, the power management unit 315 may transmit signaling to the direct memory access 310 to load code stored to the buffer manager 305.” The command in this context is not the first command but rather the second command. Thus, this limitation is not supported by the application as originally filed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 2 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iyengar et al. (US 2019/0095220).
In regards to claim 2, Iyengar teaches an apparatus, comprising:
a buffer manager configured to receive a first command (DRAM controller 170, figure 1; Figure 1 shows how BL4 is stored in DRAM 190);
a power management unit configured to receive a second command to initiate a transition from a first power mode to a second power mode and analyze the first command received by the buffer manager (“The techniques for bootup described herein where multiple cores are enabled in a pre-boot environment may be used to bootup the same types of SoC as the conventional techniques described with respect to FIG. 1A, but enable multiple cores instead of only a single core in the pre-boot environment. In FIG. 1B, BSP 111 (e.g., as initialized by BL0) executes BL1a. CPU BSP 111 further executes BL2, BL3, and BL4.”, paragraph 0044; “In certain aspects (e.g., in a flashless boot configuration), instead of initializing storage controller 180 and storage 195, bootloader BL1a also initializes boot I/F controller 183, and causes CPUSS 105 to load the firmware received over the transport layer into DRAM 190 for execution. Accordingly, the SoC 100 can access firmware images from DRAM 190.”, paragraph 0033);
a first processing element (“For example, CPU cores 112, 121, and 122 may be used as secondary cores and referred to as auxiliary processors (APs) 112, 121, and 122.”, paragraph 0041); and
a second processing element (“For example, CPU cores 112, 121, and 122 may be used as secondary cores and referred to as auxiliary processors (APs) 112, 121, and 122.”, paragraph 0041), wherein the first processing element and the second processing element are configured to be initialized based at least in part on reception of the second command (“However, unlike FIG. 1A, each of APs 112, 121, and 122 can begin executing code (e.g., tasks of firmware images) once BL3 is executed and before execution of the OS. In particular, as part of execution of BL3, each of APs 112, 121, and 122 executes AK, which as will be discussed further enables the APs to request services from the BSP 111.”, paragraph 0044) and at least partially concurrent with the power management unit analyzing the command received by the buffer manager (Figure 1B shows how the AP’s execution of BL3 overlaps in time with BSP’s execution of BL4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Iyengar et al. (US 2019/0095220) in view of Asnaashari et al. (US 2010/0262721).
In regards to claim 3, Iyengar teaches claim 2. Iyengar fails to teach a direct memory access component coupled with the buffer manager, the power management unit, and the first processing element, wherein the direct memory access component is configured to execute one or more operations at the buffer manager. Asnaashari teaches a direct memory access component coupled with the buffer manager, the power management unit, and the first processing element (Front end DMA 316, figure 3), wherein the direct memory access component is configured to execute one or more operations at the buffer manager (“The front end DMA 316 can be configured to distribute data associated with a particular command to a corresponding channel DMA, e.g., 354-1, . . . , 354-N.”, paragraph 0044) “in order to increase the efficiency of distributing the commands from the command queue, e.g., 386 in FIG. 3, to the various back end channels and thereby increasing the speed of commands thorough the command queue, e.g., 386 in FIG. 3.” (paragraph 0084) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Iyengar with Asnaashari to include a direct memory access component coupled with the buffer manager, the power management unit, and the first processing element, wherein the direct memory access component is configured to execute one or more operations at the buffer manager “in order to increase the efficiency of distributing the commands from the command queue, e.g., 386 in FIG. 3, to the various back end channels and thereby increasing the speed of commands thorough the command queue, e.g., 386 in FIG. 3.” (id.)
In regards to claim 4, Asnaashari further teaches that the direct memory access component is further configured to:
receive signaling from the first processing element to initiate execution of the one or more operations at the buffer manager (Figure 3 shows a two-way arrow between the front end DMA and the channel processors).
In regards to claim 5, Asnaashari further teaches that the direct memory access component is further configured to:
receive a code from the buffer manager based at least in part on reception of the first command (“The host FIFO 322 can be communicatively coupled to an encryption device 324 having a number of encryption engines, e.g., encryption engines implementing an AES algorithm. The encryption device 324 may be configured to process, e.g., encrypt, a payload associated with a particular command, and transmit the payload to the front end DMA 316.”, paragraph 0039); and
transmit the code to the first processing element to initiate initialization of the first processing element (“The front end DMA 316 can be configured to distribute data associated with a particular command to a corresponding channel DMA, e.g., 354-1, . . . , 354-N.”, paragraph 0044).
In regards to claim 6, Iyengar teaches claim 2. Iyengar fails to teach a host interface configured to:
receive one or more commands from a host system; and
transmit the one or more commands to the buffer manager, wherein the buffer manager is configured to receive the first command based at least in part on reception of the first command from the host interface.
Asnaashari teaches a host interface (Host interface 314, figure 3) configured to:
receive one or more commands from a host system (“Command dispatcher 318 can receive a number of commands from the host, e.g., 202 in FIG. 2, through the host interface 314 and application layer 320.”, paragraph 0047); and
transmit the one or more commands to the buffer manager, wherein the buffer manager is configured to receive the first command based at least in part on reception of the first command from the host interface (“According to one or more embodiments, a command (including the command parameters), e.g., a command portion of the input information, can be directed to the task file 315, and an associated payload, e.g., a data portion of the input information, can be directed to the host FIFO 322.”, paragraph 0037)
in order to communication information with another device (paragraph 0028).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Iyengar with Asnaashari to include a host interface configured to:
receive one or more commands from a host system; and
transmit the one or more commands to the buffer manager, wherein the buffer manager is configured to receive the first command based at least in part on reception of the first command from the host interface
in order to communication information with another device (id.).
In regards to claim 7, Asnaashari further teaches that the host interface is further configured to:
transfer the one or more commands to a queue of the host interface (“According to one or more embodiments, a command (including the command parameters), e.g., a command portion of the input information, can be directed to the task file 315, and an associated payload, e.g., a data portion of the input information, can be directed to the host FIFO 322.”, paragraph 0037).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iyengar et al. (US 2019/0095220) in view of Sauber et al. (US 2014/0129759).
In regards to claim 8, Iyengar teaches claim 2. Iyengar fails to teach that the power management unit is further configured to:
determine a type of the first command based at least in part on analyzing the first command; and
determine to initiate initializing the second processing element based at least in part on the type of the first command.
Sauber teaches that the power management unit is further configured to:
determine a type of the first command based at least in part on analyzing the first command (“the low power operation sub-method 800 proceeds to decision block 830 where it is determined whether a simple command is received”, paragraph 0045); and
determine to initiate initializing the second processing element based at least in part on the type of the first command (“If, at decision block 830, it is determined that a simple command is received, the low power operation sub-method 800 proceeds to block 832 where the simple command is executed. In an embodiment, the low power function processing element 210 is operable to execute simple commands received at decision block 830. Following block 832, the method 800 proceeds to decision block 812, discussed above. If, at decision block 830, it is determined that a simple command has not been received, the low power operation sub-method 800 proceeds to block 834 where the full function flag is cleared and power is enabled to all functions (e.g., because a command has been received that cannot be executed or journaled in the lower power mode.)”, paragraph 0045)
“which allows major portions of the storage system to be powered down” (paragraph 0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Iyengar with Sauber such that the power management unit is further configured to:
determine a type of the first command based at least in part on analyzing the first command; and
determine to initiate initializing the second processing element based at least in part on the type of the first command
“which allows major portions of the storage system to be powered down” (id.).
Response to Arguments
Applicant’s arguments, see pages 8 and 11-12, filed 6 July 2026, with respect to the drawing objection and double patenting rejection have been fully considered and are persuasive. The drawing objection and double patenting rejection have been withdrawn.
Applicant's arguments, see pages 9-11, filed 6 July 2026, with respect to the prior art rejections have been fully considered but they are not persuasive.
In response to the arguments, the Examiner is interpreting Iyengar’s BSP as teaching the claimed power management unit. The bootloaders BL1a-BL4 are all commands that initiate a transition from a first power mode to a second power mode, specifically powered off to booted. Iyengar teaches how BL3 is received/accessed from DRAM 190 (paragraph 0033). Iyengar also teaches how execution of BL3 is part of the initialization of the AP’s (paragraph 0044).
Conclusion
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 22 July 2026
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