DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7 April 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because many of the reference characters in figure 3 are not underlined despite not having lead lines. See 37 CFR 1.84(q). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 2 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iyengar et al. (US 2019/0095220).
In regards to claim 2, Iyengar teaches an apparatus, comprising:
a buffer manager configured to receive a command (DRAM controller 170, figure 1; Figure 1 shows how BL3 is stored in DRAM 190);
a power management unit configured to analyze the command received by the buffer manager (“In FIG. 1B, BSP 111 (e.g., as initialized by BL0) executes BL1a. CPU BSP 111 further executes BL2, BL3, and BL4.”, paragraph 0044);
a first processing element (“For example, CPU cores 112, 121, and 122 may be used as secondary cores and referred to as auxiliary processors (APs) 112, 121, and 122.”, paragraph 0041); and
a second processing element (“For example, CPU cores 112, 121, and 122 may be used as secondary cores and referred to as auxiliary processors (APs) 112, 121, and 122.”, paragraph 0041), wherein the first processing element and the second processing element are configured to be initialized at least partially concurrent with the power management unit analyzing the command received by the buffer manager (“FIG. 1B is a block diagram illustrating an example bootup of SoC 100 where multiple cores are enabled in a pre-boot environment, in accordance with certain aspects of the present disclosure. … However, unlike FIG. 1A, each of APs 112, 121, and 122 can begin executing code (e.g., tasks of firmware images) once BL3 is executed and before execution of the OS. In particular, as part of execution of BL3, each of APs 112, 121, and 122 executes AK, which as will be discussed further enables the APs to request services from the BSP 111.”, paragraph 0044; See also figure 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Iyengar et al. (US 2019/0095220) in view of Asnaashari et al. (US 2010/0262721).
In regards to claim 3, Iyengar teaches claim 2. Iyengar fails to teach a direct memory access component coupled the buffer manager, the power management unit, and the first processing element, wherein the direct memory access component is configured to execute one or more operations at the buffer manager. Asnaashari teaches a direct memory access component coupled the buffer manager, the power management unit, and the first processing element (Front end DMA 316, figure 3), wherein the direct memory access component is configured to execute one or more operations at the buffer manager (“The front end DMA 316 can be configured to distribute data associated with a particular command to a corresponding channel DMA, e.g., 354-1, . . . , 354-N.”, paragraph 0044) “in order to increase the efficiency of distributing the commands from the command queue, e.g., 386 in FIG. 3, to the various back end channels and thereby increasing the speed of commands thorough the command queue, e.g., 386 in FIG. 3.” (paragraph 0084) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Iyengar with Asnaashari to include a direct memory access component coupled the buffer manager, the power management unit, and the first processing element, wherein the direct memory access component is configured to execute one or more operations at the buffer manager “in order to increase the efficiency of distributing the commands from the command queue, e.g., 386 in FIG. 3, to the various back end channels and thereby increasing the speed of commands thorough the command queue, e.g., 386 in FIG. 3.” (id.)
In regards to claim 4, Asnaashari further teaches that the direct memory access component is further configured to:
receive signaling from the first processing element to initiate execution of the one or more operations at the buffer manager (Figure 3 shows a two-way arrow between the front end DMA and the channel processors).
In regards to claim 5, Asnaashari further teaches that the direct memory access component is further configured to:
receive a code from the buffer manager based at least in part on reception of the command (“The host FIFO 322 can be communicatively coupled to an encryption device 324 having a number of encryption engines, e.g., encryption engines implementing an AES algorithm. The encryption device 324 may be configured to process, e.g., encrypt, a payload associated with a particular command, and transmit the payload to the front end DMA 316.”, paragraph 0039); and
transmit the code to the first processing element to initiate initialization of the first processing element (“The front end DMA 316 can be configured to distribute data associated with a particular command to a corresponding channel DMA, e.g., 354-1, . . . , 354-N.”, paragraph 0044).
In regards to claim 6, Iyengar teaches claim 2. Iyengar fails to teach a host interface configured to:
receive one or more commands from a host system; and
transmit the one or more commands to the buffer manager, wherein the buffer manager is configured to receive the command based at least in part on reception of the command from the host interface.
Asnaashari teaches a host interface (Host interface 314, figure 3) configured to:
receive one or more commands from a host system (“Command dispatcher 318 can receive a number of commands from the host, e.g., 202 in FIG. 2, through the host interface 314 and application layer 320.”, paragraph 0047); and
transmit the one or more commands to the buffer manager, wherein the buffer manager is configured to receive the command based at least in part on reception of the command from the host interface (“According to one or more embodiments, a command (including the command parameters), e.g., a command portion of the input information, can be directed to the task file 315, and an associated payload, e.g., a data portion of the input information, can be directed to the host FIFO 322.”, paragraph 0037)
in order to communication information with another device (paragraph 0028).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Iyengar with Asnaashari to include a host interface configured to:
receive one or more commands from a host system; and
transmit the one or more commands to the buffer manager, wherein the buffer manager is configured to receive the command based at least in part on reception of the command from the host interface
in order to communication information with another device (id.).
In regards to claim 7, Asnaashari further teaches that the host interface is further configured to:
transfer the one or more commands to a queue of the host interface (“According to one or more embodiments, a command (including the command parameters), e.g., a command portion of the input information, can be directed to the task file 315, and an associated payload, e.g., a data portion of the input information, can be directed to the host FIFO 322.”, paragraph 0037).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iyengar et al. (US 2019/0095220) in view of Sauber et al. (US 2014/0129759).
In regards to claim 8, Iyengar teaches claim 2. Iyengar fails to teach that the power management unit is further configured to:
determine a type of the command based at least in part on analyzing the command; and
determine to initiate initializing the second processing element based at least in part on the type of the command.
Sauber teaches that the power management unit is further configured to:
determine a type of the command based at least in part on analyzing the command (“the low power operation sub-method 800 proceeds to decision block 830 where it is determined whether a simple command is received”, paragraph 0045); and
determine to initiate initializing the second processing element based at least in part on the type of the command (“If, at decision block 830, it is determined that a simple command is received, the low power operation sub-method 800 proceeds to block 832 where the simple command is executed. In an embodiment, the low power function processing element 210 is operable to execute simple commands received at decision block 830. Following block 832, the method 800 proceeds to decision block 812, discussed above. If, at decision block 830, it is determined that a simple command has not been received, the low power operation sub-method 800 proceeds to block 834 where the full function flag is cleared and power is enabled to all functions (e.g., because a command has been received that cannot be executed or journaled in the lower power mode.)”, paragraph 0045)
“which allows major portions of the storage system to be powered down” (paragraph 0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Iyengar with Sauber such that the power management unit is further configured to:
determine a type of the command based at least in part on analyzing the command; and
determine to initiate initializing the second processing element based at least in part on the type of the command
“which allows major portions of the storage system to be powered down” (id.).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 9, 12-14, 17, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15, 16, 22, 22, 1, and 2 of U.S. Patent No. 12,229,444. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the limitations of this application’s claims are also in the patent’s claims.
Claims 10 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 1 of U.S. Patent No. 12,229,444 in view of Iyengar et al. (US 2019/0095220).
In regards to claims 10 and 18, claims 15 and 1 of U.S. Patent No. 12,229,444 teach claims 9 and 17. Claims 15 and 1 of U.S. Patent No. 12,229,444 fail to teach that the processing circuitry is further configured to cause the memory system to:
load a code from a buffer manager based at least in part on reception of the command, wherein initializing the first processing element is based at least in part on loading the code.
Iyengar teaches that the processing circuitry is further configured to cause the memory system to:
load a code from a buffer manager based at least in part on reception of the command, wherein initializing the first processing element is based at least in part on loading the code (“For example, in certain aspects, the use of multiple CPU cores may be enabled at the loading of the BL3 firmware image.”, paragraph 0039; “In particular, as part of execution of BL3, each of APs 112, 121, and 122 executes AK, which as will be discussed further enables the APs to request services from the BSP 111.”, paragraph 0044)
which “may reduce boot time for booting the SoC” (paragraph 0044).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claims 15 and 1 of U.S. Patent No. 12,229,444 with Iyengar such that the processing circuitry is further configured to cause the memory system to:
load a code from a buffer manager based at least in part on reception of the command, wherein initializing the first processing element is based at least in part on loading the code
which “may reduce boot time for booting the SoC” (id.).
Claims 11 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 1 of U.S. Patent No. 12,229,444 in view of Benisty (US 10,387,078).
In regards to claims 11 and 19, claims 15 and 1 of U.S. Patent No. 12,229,444 teach claims 9 and 17. Claims 15 and 1 of U.S. Patent No. 12,229,444 fail to teach that the processing circuitry is further configured to cause the memory system to:
set a depth of a queue of a host interface to a first value based at least in part on initializing the first processing element; and
set the depth of the queue to a second value based at least in part on the first processing element being fully initialized, the second value greater than the first value.
Benisty teaches that the processing circuitry is further configured to cause the memory system to:
set a depth of a queue of a host interface to a first value based at least in part on initializing the first processing element (“Briefly, at 302, the data storage controller determines an effective (modified) queue depth for a submission queue for use in throttling the submission of new entries into the submission queue by the host to, for example, avoid timeouts in the host (particularly if the data storage controller has reduced its operating speed due to excessive heat or high power usage).”, Col. 8, lines 37-43); and
set the depth of the queue to a second value based at least in part on the first processing element being fully initialized, the second value greater than the first value (“The total combined depth of all submission queues defines a maximum submission queue depth.”, Col. 10, lines 22-23)
“to … avoid timeouts in the host” (Col. 8, lines 40-41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claims 15 and 1 of U.S. Patent No. 12,229,444 with Benisty such that the processing circuitry is further configured to cause the memory system to:
set a depth of a queue of a host interface to a first value based at least in part on initializing the first processing element; and
set the depth of the queue to a second value based at least in part on the first processing element being fully initialized, the second value greater than the first value
“to … avoid timeouts in the host” (id.).
Claims 15 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 1 of U.S. Patent No. 12,229,444 in view of Sauber et al. (US 2014/0129759).
In regards to claim 15, claim 15 of U.S. Patent No. 12,229,444 teaches claim 9. Claim 15 of U.S. Patent No. 12,229,444 fails to teach that, to determine whether to initialize the second processing element, the processing circuitry is further configured to cause the memory system to:
determine to initialize the second processing element based at least in part on the type of command comprising an access command.
Sauber teaches that, to determine whether to initialize the second processing element, the processing circuitry is further configured to cause the memory system to:
determine to initialize the second processing element based at least in part on the type of command comprising an access command (Figure 8 shows how the full function initialization in step 500 is based at least in part on whether a read or write command is received as checked in steps 802 and 804)
“which allows major portions of the storage system to be powered down” (paragraph 0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 15 of U.S. Patent No. 12,229,444 with Sauber such that, to determine whether to initialize the second processing element, the processing circuitry is further configured to cause the memory system to:
determine to initialize the second processing element based at least in part on the type of command comprising an access command
“which allows major portions of the storage system to be powered down” (id.).
In regards to claim 21, claim 1 of U.S. Patent No. 12,229,444 teaches claim 17. Claim 1 of U.S. Patent No. 12,229,444 fails to teach receiving, prior to receiving the command, a second command for the memory system to transition power modes, wherein initializing the first processing element is based at least in part on reception of the second command. Sauber teaches receiving, prior to receiving the command, a second command for the memory system to transition power modes (“The start-up sub-method 400 begins at block 402 where the system is powered on, exits a deep power down state, exits a sleep state, and/or otherwise is instructed to begin operations from a substantially non-operational state.”, paragraph 0027), wherein initializing the first processing element is based at least in part on reception of the second command (“The full function initialization sub-method 500 may be performed following block 412 of the start-up sub-method 400 when the storage system 200 is configured or instructed to enter the full function mode, discussed above, or following block 834 of the low power operation sub-method 800 when the storage system 200 is performing a ‘quick start’ and entering the full function mode from the low power mode, discussed above and in further detail below.”, paragraph 0030) “in order to provide a faster perceived wake time” (paragraph 0046). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 1 of U.S. Patent No. 12,229,444 with Sauber to include receiving, prior to receiving the command, a second command for the memory system to transition power modes, wherein initializing the first processing element is based at least in part on reception of the second command “in order to provide a faster perceived wake time” (id.).
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,229,444 in view of Brief et al. (US 2019/0391761).
In regards to claim 16, claim 15 of U.S. Patent No. 12,229,444 teaches claim 9. Claim 15 of U.S. Patent No. 12,229,444 fails to teach that, to determine whether to initialize the second processing element, the processing circuitry is further configured to cause the memory system to:
determine not to initialize the second processing element based at least in part on the type of command comprising a start-stop unit command.
Brief teaches that, to determine whether to initialize the second processing element, the processing circuitry is further configured to cause the memory system to:
determine not to initialize the second processing element based at least in part on the type of command comprising a start-stop unit command (“In one embodiment, the contingent event or parameter received is a SSU command with a power condition field of sleep or powerdown which causes the storage device to generate a callback response containing a read buffer command.”, paragraph 0033)
“to more quickly or more efficiently return the internal state of the storage device to an active mode from a sleep more or powerdown mode” (paragraph 0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 15 of U.S. Patent No. 12,229,444 with Brief such that, to determine whether to initialize the second processing element, the processing circuitry is further configured to cause the memory system to:
determine not to initialize the second processing element based at least in part on the type of command comprising a start-stop unit command
“to more quickly or more efficiently return the internal state of the storage device to an active mode from a sleep more or powerdown mode” (id.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 6 April 2026
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