Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This responds to Applicant’s Arguments/Remarks filed 12/09/2025. Claims 2, 9, 16 have been amended. Claim 1 has been cancelled. Claims 2-21 are now pending in this Application.
Claim Rejections - 35 USC § 101
Applicant argues that the claims are directed to improve the functioning of a system that implements a memory device. however, the claimed invention is directed to “Claim 1 appears to be directed to an abstract idea without reciting additional limitations that tie it to a practical application or without reciting additional limitations that amount to significantly more than the abstract idea. One can mentally generate graph with nodes for spaces in a building as well as assets that are contained within those spaces. Then one can also mentally associate and classify senor readings and generate relationships between spaces, assets and sensors. The additional limitations are receiving data. These additional limitations are mere data gathering which are insignificant extra solution activities under step 2A prong II and well understood routine and conventional under step 2B (For Berkhiemer See MPEP 2106.05(d)(II) Versata.), which falls within recognized abstract idea group.
The limitation “wherein, in accordance with a data transformation, the processing-in-memory instructions have a first format that is different from a second format of one or more commands received from the host device” describes converting data from one format to another, which is a form of data manipulation, an abstract idea.
The claims do not improve the functioning of a computer or another technology. Instead, they merely use generic computing component (e.g., processor, memory, interface circuitry) as tools to perform the abstract idea.
The additional elements, individually and in combination, do not amount to significantly more than the abstract idea. Therefore, the examiner respectfully maintained the rejection.
Response to Arguments
Applicant’s arguments with respect to claim(s) 2-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiwari (U.S. Pub No. 2016/0062673 A1), and in view of Sobolewski et al (U.S. Pub No. 2012/0159606 A1).
Claim(s) 2-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tiwari (U.S. Pub No. 2016/0062673 A1).
As per claim 2, Tiwari discloses an apparatus, comprising:
a plurality of memory banks, wherein each memory bank of the plurality of memory banks is associated with circuitry configured to perform one or more logical operations using data stored in the plurality of memory banks without transferring the data via an input/output (I/O) interface to a host device (par [0025]); and
a device comprising at least one controller, wherein the at least one controller is coupled with the plurality of memory banks and is configured to transmit processing-in-memory instructions to the circuitry for execution of the processing-in-memory instructions (Par [0025, 0031, 0038-0039]).
Tiwari does not explicitly disclose wherein, in accordance with a data transformation, the processing-in-memory instructions have a first format that is different from a second format of one or more commands received from the host device.
However, Sobolewski discloses wherein, in accordance with a data transformation, the processing-in-memory instructions have a first format that is different from a second format of one or more commands received from the host device (Par [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Sobolewski into the teaching of Tiwari in order to provide successful protection (Par [0018]).
As per claim 3, Tiwari discloses the apparatus of claim 2, wherein each controller of the at least one controller is configured to sequence the one or more logical operations based at least in part on the processing-in-memory instructions and one or more other instructions (Par [0038, 0203]).
As per claim 4, Tiwari discloses the apparatus of claim 2, wherein each controller of the at least one controller is coupled with a respective memory bank of the plurality of memory banks (par [0038, 0203]).
As per claim 5, Tiwari discloses the apparatus of claim 2, wherein the processing-in-memory instructions are associated with the one or more logical operations using the data, wherein the data comprises one or more operands (Par [0133]).
As per claim 6, Tiwari discloses the apparatus of claim 5, wherein the one or more logical operations are based at least in part on the one or more operands comprising vector data (par [0076-0079]).
As per claim 7, Tiwari discloses the apparatus of claim 2, wherein the circuitry is configured to store respective results of the one or more logical operations in one or more memory banks of the plurality of memory banks without transferring the respective results to additional circuitry external to the plurality of memory banks (par [0037]).
As per claim 8, Tiwari discloses the apparatus of claim 2, wherein the plurality of memory banks comprise dynamic random access memory (DRAM) cells (Par [0036]).
As per claim 9, Tiwari discloses a memory system, comprising:
a host; one or more banks of memory cells, wherein each bank of the one or more banks of memory cells is associated with circuitry configured to perform one or more logical operations using data stored in the one or more banks of memory cells without transferring the data via an input/output (I/O) interface to the host (Par [0025]); and
a device coupled with the host and comprising one or more controllers, wherein the one or more controllers are coupled with the one or more banks of memory cells and are configured to transmit processing-in-memory instructions to the circuitry for execution of the processing-in-memory instructions (Par [0025, 0031, 0038-0039]).
Tiwari does not explicitly disclose wherein, in accordance with a data transformation, the processing-in-memory instructions have a first format that is different from a second format of one or more commands received from the host device.
However, Sobolewski discloses wherein, in accordance with a data transformation, the processing-in-memory instructions have a first format that is different from a second format of one or more commands received from the host device (Par [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Sobolewski into the teaching of Tiwari in order to provide successful protection (Par [0018]).
As per claim 10, Tiwari discloses the memory system of claim 9, wherein the one or more controllers are configured to sequence the one or more logical operations based at least in part on the processing-in-memory instructions and one or more other instructions (par [0038, 0203]).
As per claim 11, Tiwari discloses the memory system of claim 9, wherein the one or more controllers are associated with a respective bank of memory cells of the one or more banks of memory cells (Par [0038, 0203]).
As per claim 12, Tiwari discloses the memory system of claim 9, wherein the processing-in-memory instructions are associated with the one or more logical operations using the data, wherein the data comprises one or more operands (par [0133]).
As per claim 13, Tiwari discloses the memory system of claim 12, wherein one or more logical operations are based at least in part on the one or more operands comprising vector data (par [0076-0079]).
As per claim 14, Tiwari discloses the memory system of claim 9, wherein circuitry is configured to store respective results of the one or more logical operations in the one or more banks of memory cells without transferring the respective results to circuitry external to the one or more banks of memory cells (Par [0037]).
As per claim 15, Tiwari discloses the memory system of claim 9, wherein the one or more banks of memory cells comprise dynamic random access memory (DRAM) cells (par [0036]).
As per claim 16, Tiwari discloses a device, comprising:
a plurality of memory banks; a device comprising one or more controllers coupled with the plurality of memory banks, the one or more controllers configured to: transmit processing-in-memory instructions to circuitry associated with the plurality of memory banks (Par [0025]); and
the circuitry associated with the plurality of memory banks, the circuitry configured to: execute the processing-in-memory instructions to perform one or more logical operations using data stored in the plurality of memory banks, wherein respective logical operations of the one or more logical operations are performed without transferring the data via an input/output (I/O) interface to a host (Par [0025, 0031, 0038-0039]).
Tiwari does not explicitly disclose wherein, in accordance with a data transformation, the processing-in-memory instructions have a first format that is different from a second format of one or more commands received from the host device.
However, Sobolewski discloses wherein, in accordance with a data transformation, the processing-in-memory instructions have a first format that is different from a second format of one or more commands received from the host device (Par [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Sobolewski into the teaching of Tiwari in order to provide successful protection (Par [0018]).
As per claim 17, Tiwari discloses the device of claim 16, wherein the one or more controllers are further configured to: sequence the one or more logical operations based at least in part on the processing-in-memory instructions and one or more other instructions from the host (Par [0038, 0203]).
As per claim 18, Tiwari discloses the device of claim 16, wherein the processing-in-memory instructions are associated with the one or more logical operations using the data, wherein the data comprises one or more operands (par [0133]).
As per claim 19, Tiwari discloses the device of claim 18, wherein the one or more logical operations are based at least in part on the one or more operands comprising vector data (par [0076-0079]).
As per claim 20, Tiwari discloses the device of claim 16, wherein the circuitry is further configured to: store respective results of the one or more logical operations in one or more memory banks of the plurality of memory banks without transferring the respective results to additional circuitry external to the plurality of memory banks (Par [0037]).
As per claim 21, Tiwari discloses the device of claim 16, wherein the plurality of memory banks comprise dynamic random access memory (DRAM) cells (Par [0036]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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March 19, 2026
/THU N NGUYEN/Examiner, Art Unit 2154