Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Amendment filed on 6/08/2026.
Claims 2-21 are pending for this examination.
Claim 1 was cancelled.
Claims 2-21 were added.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5-11, and 13-21 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 7,558,890), herein referred to as Li ‘890, in view of Yoshida (US 2012/0079172), herein referred to as Yoshida ‘172, and Chen et al. (US 5,623,635), herein referred to as Chen ‘635.
Referring to claim 2, Li ‘890 teaches a system (see Fig. 2A), comprising:
one or more memory devices (see Fig. 2A, memory 230); and
one or more host devices (see Fig. 2A, single IC die 200 with network processor 210) coupled with the one or more memory devices (see Fig. 2A, single IC die 200 couples with memory 230), the one or more host devices configured to:
determine an order associated with a set of instructions for execution (see Col. 5, lines 52-67, Col. 1, lines 1-2, where in response to a stitch instruction a specific order for the packets fragments to be read from memory 230 is set up, i.e. if packet fragments arrive out of order from memory, they can be rearranged in order by a network processor through one or more stitch instructions) via one or more execution units (see Fig. 2A, execution unit 221) associated with the memory (see Fig. 2A, where execution unit is issuing instructions to memory 230);
generate the set of instructions based at least in part on the order (see Col. 5, lines 52-67, Col. 1, lines 1-2, where the execution unit 221 implements stitch instructions without moving packet fragments 231 in memory 230, i.e. generates and sends instructions to memory 230 to change pointers to the fragments thus reordering the order of packets being read); and
output the set of instructions to at least one controller (see Fig. 2A, traffic manager 220) associated with the one or more execution units (see Col. 18, lines 20-32, where execution unit 221 decodes queuing instructions, slices packet fragments into cells and asks for state information on the queue to stored data from control memory interface 402 and admission control decisions for each cell from admission controller 409 for queuing packets to be written and/or reassembling packets read from memory, see Fig. 4A, i.e. instructions to read out the packets in the specified order).
However, Li ‘890 does not teach the one or more memory devices comprising a plurality of banks of memory cells; and wherein the set of instructions comprises at least one logical operation on data included in the memory, i.e. the reassignment of pointers is not a considered a logical operation on data.
Yoshida ‘172 teaches memory system (see Abstract; see Fig. 1, SSD 220) comprising a NAND memory controller (see Fig. 2, NAND controller 20) having a plurality of memory banks accessible by associated memory bank controllers (see Fig. 2, where there are a plurality of memory banks 2 are coupled to associated memory bank controller 24).
Li ‘890 and Yoshida ‘172 apply as analogous prior art as both pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li ‘890 system as set forth above to have the memory of Li ‘890 be a SSD memory device comprising a plurality of banks of memory, each bank inherently having memory cells, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that SSD storage devices are popularly used in the art as a memory storage device, wherein a person of ordinary skill in the art would be motivated to use a SSD storage device in place of a generic memory as SSD storages are known for having faster performance compared with HDD storage devices.
Chen ‘635 teaches method for transferring data to and from memory (see Abstract) where a CPU executes instruction such as arithmetic or logical operations on data, program flow instructions for ordering the executing of instruction, and memory access commands (see Col. 1, lines 38-46).
Li ‘890, Yoshida ‘172, and Chen ‘635 apply as analogous prior art as all of these prior arts pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Li ‘890 and Yoshida ‘172 system as set forth above to have the instructions being sent to the memory include logical operations, flow control instructions, and memory access commands, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that Li ‘890 is ordering the packet fragments in memory and reassembling packets which would mean a memory access operation is being done which broadly interpreted can be inclusive of different types of operations such as read/write operation, multiply-accumulate operations (logical operations), etc.
As to claim 3, Li ‘890 does not teach the system of claim 2, further comprising: the one or more execution units, wherein each execution unit of the one or more execution units is coupled with one or more banks of memory cells of the plurality of banks of memory cells.
Yoshida ‘172 teaches memory system (see Abstract; see Fig. 1, SSD 220) comprising a NAND memory controller (see Fig. 2, NAND controller 20) having a plurality of memory banks accessible by associated memory bank controllers (see Fig. 2, where there are a plurality of memory banks 2 are coupled to associated memory bank controller 24).
Li ‘890 and Yoshida ‘172 apply as analogous prior art as both pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li ‘890 system as set forth above to have the memory of Li ‘890 be a SSD memory device comprising a plurality of banks of memory, where the execution unit 221 of Li ‘890 couples to at least one bank of memory cells, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that SSD storage devices are popularly used in the art as a memory storage device, wherein a person of ordinary skill in the art would be motivated to use a SSD storage device in place of a generic memory as SSD storages are known for having faster performance compared with HDD storage devices.
As to claim 5, Li ‘890 teaches the system of claim 2, wherein the set of instructions comprises an indication of the order associated with the set of instructions (see Col. 5, lines 52-67, Col. 1, lines 1-2, where in response to a stitch instruction a specific order for the packets fragments to be read from memory 230 is set up, i.e. if packet fragments arrive out of order from memory, they can be rearranged in order by a network processor through one or more stitch instructions).
As to claim 6, Li ‘890 teaches the system of claim 2, wherein the at least one controller is configured to obtain the set of instructions via a register (see Fig. 2A, where write and/or stitch and/or link instructions are transmitted from the ingress FIFO 112 to traffic manager 220, where a FIFO can be a collection of registers).
As to claims 7, the combination Li ‘890 and Yoshida ‘172 do not specifically teach the system of claim 2, wherein the at least one logical operation comprises an accumulation operation, an addition operation, a multiplication operation, or any combination thereof.
Chen ‘635 teaches method for transferring data to and from memory (see Abstract) where a CPU executes instruction such as arithmetic or logical operations on data, program flow instructions for ordering the executing of instruction, and memory access commands (see Col. 1, lines 38-46), where Examiner points out that arithmetic logical operations are inclusive of multiply and addition operations.
Li ‘890, Yoshida ‘172, and Chen ‘635 apply as analogous prior art as all of these prior arts pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Li ‘890 and Yoshida ‘172 system as set forth above to have the instructions being sent to the memory include arithmetic or logical operations, flow control instructions, and memory access commands, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that Li ‘890 is ordering the packet fragments in memory and reassembling packets which would mean a memory access operation is being done which broadly interpreted can be inclusive of different types of operations such as read/write operation, multiply-accumulate operations (logical operations), etc.
As to claim 8, Li ‘890 teaches the system of claim 2, wherein the set of instructions is associated with one or more memory addresses (see Col. 8, lines 60-67).
As to claim 9, Li ‘890 teaches the system of claim 2, wherein the data comprises a set of operands on which the set of instructions is executed for the at least one logical operation (Examiner points out that all read/write instructions, would include operands such as address operands for locating the addresses of data in memory, see Col. 8, lines 60-67).
As to claim 10, Li ‘890 teaches the system of claim 2, wherein the one or more execution units are external to the one or more host devices (see Fig. 2A, where the execution units 221 are a part of traffic manager 220 and external to network processor 210).
Referring to claim 11, Li ‘890 teaches an apparatus (see Fig. 2A), comprising:
one or more memory devices (see Fig. 2A, memory 230); and
at least one controller (see Fig. 2A, traffic manager 220) associated with one or more execution units (see Fig. 2A, execution unit 221), the one or more execution units being coupled with the memory (see Fig. 2A, single IC die 200 with execution unit 221 coupling with memory 230), wherein the at least one controller is configured to:
receive, from a host device (see Fig. 2A, single IC die 200 with network processor 210), a set of instructions for execution via the one or more execution units (see Col. 5, lines 52-67, Col. 1, lines 1-2, where in response to a stitch instruction a specific order for the packets fragments to be read from memory 230 is set up, i.e. if packet fragments arrive out of order from memory, they can be rearranged in order by a network processor through one or more stitch instructions), wherein the set of instructions is based at least in part on an order (see Col. 5, lines 52-67, Col. 1, lines 1-2, where the execution unit 221 implements stitch instructions without moving packet fragments 231 in memory 230, i.e. generates and sends instructions to memory 230 to change pointers to the fragments thus reordering the order of packets being read).
However, Li ‘890 does not teach the one or more memory devices comprising a plurality of banks of memory cells; and wherein the set of instructions comprises at least one logical operation on data included in the memory, i.e. the reassignment of pointers is not a considered a logical operation on data.
Yoshida ‘172 teaches memory system (see Abstract; see Fig. 1, SSD 220) comprising a NAND memory controller (see Fig. 2, NAND controller 20) having a plurality of memory banks accessible by associated memory bank controllers (see Fig. 2, where there are a plurality of memory banks 2 are coupled to associated memory bank controller 24).
Li ‘890 and Yoshida ‘172 apply as analogous prior art as both pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li ‘890 system as set forth above to have the memory of Li ‘890 be a SSD memory device comprising a plurality of banks of memory, each bank inherently having memory cells, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that SSD storage devices are popularly used in the art as a memory storage device, wherein a person of ordinary skill in the art would be motivated to use a SSD storage device in place of a generic memory as SSD storages are known for having faster performance compared with HDD storage devices.
Chen ‘635 teaches method for transferring data to and from memory (see Abstract) where a CPU executes instruction such as arithmetic or logical operations on data, program flow instructions for ordering the executing of instruction, and memory access commands (see Col. 1, lines 38-46).
Li ‘890, Yoshida ‘172, and Chen ‘635 apply as analogous prior art as all of these prior arts pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Li ‘890 and Yoshida ‘172 system as set forth above to have the instructions being sent to the memory include logical operations, flow control instructions, and memory access commands, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that Li ‘890 is ordering the packet fragments in memory and reassembling packets which would mean a memory access operation is being done which broadly interpreted can be inclusive of different types of operations such as read/write operation, multiply-accumulate operations (logical operations), etc.
As to claim 13, Li ‘890 teaches the apparatus of claim 11, wherein the set of instructions comprises an indication of the order associated with the set of instructions (see Col. 5, lines 52-67, Col. 1, lines 1-2, where in response to a stitch instruction a specific order for the packets fragments to be read from memory 230 is set up, i.e. if packet fragments arrive out of order from memory, they can be rearranged in order by a network processor through one or more stitch instructions).
As to claim 14, Li ‘890 teaches the apparatus of claim 11, wherein the at least one controller is configured to obtain the set of instructions via a register (see Fig. 2A, where write and/or stitch and/or link instructions are transmitted from the ingress FIFO 112 to traffic manager 220, where a FIFO can be a collection of registers).
As to claim 15, the combination Li ‘890 and Yoshida ‘172 do not specifically teach apparatus of claim 11, wherein the at least one logical operation comprises an accumulation operation, an addition operation, a multiplication operation, or any combination thereof.
Chen ‘635 teaches method for transferring data to and from memory (see Abstract) where a CPU executes instruction such as arithmetic or logical operations on data, program flow instructions for ordering the executing of instruction, and memory access commands (see Col. 1, lines 38-46), where Examiner points out that arithmetic logical operations are inclusive of multiply and addition operations.
Li ‘890, Yoshida ‘172, and Chen ‘635 apply as analogous prior art as all of these prior arts pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Li ‘890 and Yoshida ‘172 system as set forth above to have the instructions being sent to the memory include arithmetic or logical operations, flow control instructions, and memory access commands, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that Li ‘890 is ordering the packet fragments in memory and reassembling packets which would mean a memory access operation is being done which broadly interpreted can be inclusive of different types of operations such as read/write operation, multiply-accumulate operations (logical operations), etc.
As to claim 16, Li ‘890 teaches the apparatus of claim 11, wherein the data comprises a set of operands on which the set of instructions is executed for the at least one logical operation (Examiner points out that all read/write instructions, would include operands such as address operands for locating the addresses of data in memory, see Col. 8, lines 60-67).
As to claim 17, Li ‘890 teaches the apparatus of claim 11, wherein the one or more execution units are external to the host device (see Fig. 2A, where the execution units 221 are a part of traffic manager 220 and external to network processor 210).
Referring to claim 18, Li ‘890 teaches an apparatus (see Fig. 2A), comprising:
one or more execution units (see Fig. 2A, execution unit 221) coupled with memory (see Fig. 2A, where execution unit 221 couples with memory 230);
one or more controllers (see Fig. 2A, traffic manager 220) associated with the one or more execution units (see Fig. 2A, where execution unit 221 is a part of traffic manager 220); and
one or more host devices (see Fig. 2A, single IC die 200 with network processor 210), the one or more host devices configured to:
generate a set of instructions based at least in part on an order associated with the set of instructions (see Col. 5, lines 52-67, Col. 1, lines 1-2, where the execution unit 221 implements stitch instructions without moving packet fragments 231 in memory 230, i.e. generates and sends instructions to memory 230 to change pointers to the fragments thus reordering the order of packets being read); and
output the set of instructions to the one or more controllers (see Fig. 2A, traffic manager 220), wherein the set of instructions is for execution by the one or more execution units (see Col. 18, lines 20-32, where execution unit 221 decodes queuing instructions, slices packet fragments into cells and asks for state information on the queue to stored data from control memory interface 402 and admission control decisions for each cell from admission controller 409 for queuing packets to be written and/or reassembling packets read from memory, see Fig. 4A, i.e. instructions to read out the packets in the specified order).
However, Li ‘890 does not teach the one or more memory devices comprising a plurality of banks of memory cells; and wherein the set of instructions is for at least one logical operation on data included in the one or more banks of memory cells, i.e. the reassignment of pointers is not a considered a logical operation on data.
Yoshida ‘172 teaches memory system (see Abstract; see Fig. 1, SSD 220) comprising a NAND memory controller (see Fig. 2, NAND controller 20) having a plurality of memory banks accessible by associated memory bank controllers (see Fig. 2, where there are a plurality of memory banks 2 are coupled to associated memory bank controller 24).
Li ‘890 and Yoshida ‘172 apply as analogous prior art as both pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li ‘890 system as set forth above to have the memory of Li ‘890 be a SSD memory device comprising a plurality of banks of memory, each bank inherently having memory cells, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that SSD storage devices are popularly used in the art as a memory storage device, wherein a person of ordinary skill in the art would be motivated to use a SSD storage device in place of a generic memory as SSD storages are known for having faster performance compared with HDD storage devices.
Chen ‘635 teaches method for transferring data to and from memory (see Abstract) where a CPU executes instruction such as arithmetic or logical operations on data, program flow instructions for ordering the executing of instruction, and memory access commands (see Col. 1, lines 38-46).
Li ‘890, Yoshida ‘172, and Chen ‘635 apply as analogous prior art as all of these prior arts pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Li ‘890 and Yoshida ‘172 system as set forth above to have the instructions being sent to the memory include logical operations, flow control instructions, and memory access commands, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that Li ‘890 is ordering the packet fragments in memory and reassembling packets which would mean a memory access operation is being done which broadly interpreted can be inclusive of different types of operations such as read/write operation, multiply-accumulate operations (logical operations), etc.
As to claim 19, Li ‘890 teaches the apparatus of claim 18, wherein the set of instructions comprises an indication of the order associated with the set of instructions (see Col. 5, lines 52-67, Col. 1, lines 1-2, where in response to a stitch instruction a specific order for the packets fragments to be read from memory 230 is set up, i.e. if packet fragments arrive out of order from memory, they can be rearranged in order by a network processor through one or more stitch instructions).
As to claim 20, Li ‘890 teaches the apparatus of claim 18, wherein the one or more controllers are configured to obtain the set of instructions via one or more registers (see Fig. 2A, where write and/or stitch and/or link instructions are transmitted from the ingress FIFO 112 to traffic manager 220, where a FIFO can be a collection of registers).
As to claim 21, Li ‘890 teaches the apparatus of claim 18, wherein the set of instructions is associated with one or more memory addresses (see Col. 8, lines 60-67).
However, the combination Li ‘890 and Yoshida ‘172 do not specifically teach wherein the at least one logical operation comprises an accumulation operation, an addition operation, a multiplication operation, or any combination thereof.
Chen ‘635 teaches method for transferring data to and from memory (see Abstract) where a CPU executes instruction such as arithmetic or logical operations on data, program flow instructions for ordering the executing of instruction, and memory access commands (see Col. 1, lines 38-46), where Examiner points out that arithmetic logical operations are inclusive of multiply and addition operations.
Li ‘890, Yoshida ‘172, and Chen ‘635 apply as analogous prior art as all of these prior arts pertain to the same field of endeavor of using memory to read/write data to.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Li ‘890 and Yoshida ‘172 system as set forth above to have the instructions being sent to the memory include arithmetic or logical operations, flow control instructions, and memory access commands, as taught by Yoshida ‘172, as a person or ordinary skill in the art would recognize that Li ‘890 is ordering the packet fragments in memory and reassembling packets which would mean a memory access operation is being done which broadly interpreted can be inclusive of different types of operations such as read/write operation, multiply-accumulate operations (logical operations), etc.
Allowable Subject Matter
Claims 4 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 4 and 12, Examiner finds that prior art does not specifically teach the independent claim, wherein each execution unit of the one or more execution units is configured to store respective results of the at least one logical operation in one or more banks of the plurality of banks of memory cells without transferring the respective results to input/output (I/O) circuitry.
Response to Arguments
Applicant’s arguments, mailed 6/08/2026, have been fully considered but they are not deemed to be persuasive.
Applicant’s cancellation of claim 1 to address the statutory double patenting rejections set forth in the previous office action (see Page 5) are deemed to be persuasive in overcoming the rejection. However, the newly added claims 2-21 have been rejected in view of new grounds of rejection stated above that were necessitated by Applicant’s amendment.
In summary, Li ‘890, in view of Yoshida ‘172 and Chen ‘635 teaches the claimed invention as set forth above.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dowling (US 6,226,738) teaches a DRAM processor system where embedded DRAM includes a DRAM array and monitor/modify unit that receives instructions and passes selected instructions for execution, i.e. sense circuit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183
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