DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1–10, 11-18, and 19–20 are rejected under 35 U.S.C. 103 as being unpatentable over Aneja (US 2024/0067110 hereinafter “Aneja”) in view of Garg (US 2022/0100247 hereinafter “Garg”).
As to claim 1, Aneja discloses in Figs. 2–3:
a first power domain at a first hierarchy level, the first power domain comprising one or more first hierarchy level sensor hubs (safety domain (SD) 214 and SD PMIC(s) 224 as shown in Fig. 3) (“The MD PMIC power supply rail 242 may be coupled to a sensing input 328 (e.g., an analog-to-digital converter (ADC) channel, remote sense pins, or another circuit configured to measure the voltage of the power supply rail 242) of one or more of the SD PMICs 224”);
a second power domain at a second hierarchy level, the second power domain comprising one or more second hierarchy level sensor hubs (main domain (MD) 212 and MD PMIC(s) 222 as shown in Fig. 3) (“The SD PMIC power supply rail 244 may be coupled to a sensing input 326 (e.g., an analog-to-digital converter (ADC) channel, remote sense pins, or another circuit configured to measure the voltage of the power supply rail 244) of one or more of the MD PMICs 222”); and
wherein the one or more first hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the second power domain (sensing input 328 coupled to MD PMIC power supply rail 242 as shown in Fig. 3) (“the at least one SD PMIC has an input coupled to the MD PMIC power supply rail for monitoring the MD PMIC power supply rail”).
Aneja does not disclose a third power domain at a third hierarchy level, wherein the one or more second hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the third power domain at the third hierarchy level, and wherein the one or more first hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the second power domain at a third hierarchy level.
However, Garg discloses in Figs. 8, 9A–9B:
a third power domain at a third hierarchy level (“FIG. 8 illustrates a multi-level hierarchy of HPM”; “FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”);
wherein the one or more second hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the third power domain at the third hierarchy level (“p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “a p-unit may serve either as a Svor, a Svee, or both a Svor/Svee p-unit”); and
wherein the one or more first hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the second power domain at a third hierarchy level (“the p-units in each die can be configured as a supervisor p-unit 102, supervisee p-unit 103 or with a dual role of supervisor/supervisee 105”; “Power management here is configured and arranged in a hierarchical structure”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and implement a third power domain at a third hierarchy level, connect the one or more second hierarchy level sensor hubs with one or more voltage sensors for monitoring the third power domain at the third hierarchy level, and connect the one or more first hierarchy level sensor hubs with one or more voltage sensors for monitoring the second power domain at a third hierarchy level, as taught by Garg, so that a mid-level domain both monitors a child domain and is itself monitored by a parent domain, reducing direct sense routing to the highest-level domain.
As to claim 2,
The circuit of claim 1 is rejected as set forth above.
Aneja does not disclose wherein the second power domain is at least one hop away from the first power domain and the third power domain is at least two hops away from the first power domain.
However, Garg discloses wherein the second power domain is at least one hop away from the first power domain and the third power domain is at least two hops away from the first power domain (“FIG. 8 illustrates a multi-level hierarchy of HPM”; “p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and place the second power domain at least one hop away from the first power domain and the third power domain at least two hops away from the first power domain, as taught by Garg, because a multi-level hierarchy inherently spaces a mid-level domain one hop from the top-level domain and a grandchild domain two hops from the top-level domain.
As to claim 3,
The circuit of claim 1 is rejected as set forth above.
Aneja discloses sending an indication of a voltage error associated with a monitored domain (“The MD PMIC 222 may report to the MD 212 whether the SD PMIC power supply rail 244 has a voltage outside an acceptable voltage range or below a threshold voltage value and is experiencing a fault”; “when the SD PMIC(s) 224 determine that the MD PMIC power supply rail 242 is in a fault state, the SD PMIC(s) 224 may inform the SD 214 of the SoC 210 that the MD PMIC 222 is experiencing an error (e.g., a functional safety (FuSa) error)”).
Aneja does not disclose wherein the one or more second hierarchy level sensor hubs send an indication of a voltage error associated with the third power domain.
However, Garg discloses sending from a mid-level unit an indication associated with a lower-level domain (“These parameters may then be communicated to supervisee p-units, or directly to controlled or monitored entities”; “second fabric 111 is used for higher priority communication between supervisor p-unit 102 and supervisee p-unit 103. Example of higher priority communication include a message to throttle because of a possible thermal runaway condition, reliability issue, etc.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and have the one or more second hierarchy level sensor hubs send an indication of a voltage error associated with the third power domain, as taught by Garg, so that a fault detected at the child domain is forwarded by the mid-level domain rather than only by the top-level domain.
As to claim 4,
The circuit of claim 1 is rejected as set forth above.
Aneja discloses wherein the one or more first hierarchy level sensor hubs send an indication of a voltage error associated with the second power domain (“when the SD PMIC(s) 224 determine that the MD PMIC power supply rail 242 is in a fault state, the SD PMIC(s) 224 may inform the SD 214 of the SoC 210 that the MD PMIC 222 is experiencing an error (e.g., a functional safety (FuSa) error)”; “The SD PMIC 224 may have an output 374 coupled to an input 375 of the SD 214 and may be used to indicate to the SD 214 whether the MD PMIC power supply rail 242 has a voltage outside an acceptable voltage range or below a threshold voltage value and is experiencing a fault”).
Aneja does not disclose and the one or more second hierarchy level sensor hubs send an indication of a voltage error associated with the third power domain.
However, Garg discloses that a mid-level unit communicates an indication concerning a lower-level domain (“These parameters may then be communicated to supervisee p-units, or directly to controlled or monitored entities”; “second fabric 111 is used for higher priority communication between supervisor p-unit 102 and supervisee p-unit 103. Example of higher priority communication include a message to throttle because of a possible thermal runaway condition, reliability issue, etc.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and have the one or more second hierarchy level sensor hubs send an indication of a voltage error associated with the third power domain, as taught by Garg, so that each hierarchy level reports the voltage error of the domain it monitors.
As to claim 5,
The circuit of claim 1 is rejected as set forth above.
Aneja further discloses wherein the first power domain is compliant with Automotive Safety Integrity Level (ASIL) D and the second power domain is compliant with ASIL B (“the MD 212 and one or more MD PMIC(s) 222 meet the integrity requirements of up to automotive safety integrity level (ASIL) B. The SD 214 and one or more SD PMIC(s) 224 may meet the integrity level of up to ASIL D”).
As to claim 6,
The circuit of claim 1 is rejected as set forth above.
Aneja discloses wherein the first power domain is compliant with Automotive Safety Integrity Level (ASIL) D, the second power domain is compliant with ASIL B (“the MD 212 and one or more MD PMIC(s) 222 meet the integrity requirements of up to automotive safety integrity level (ASIL) B. The SD 214 and one or more SD PMIC(s) 224 may meet the integrity level of up to ASIL D”).
Aneja does not disclose and the third power domain is compliant with ASIL B or lower.
However, Garg discloses a plurality of domains under a hierarchical supervisor/supervisee structure (“FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”; “a domain may be a group of logic units or function units that are controlled by a particular supervisor”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and make the third power domain compliant with ASIL B or lower, as taught by applying Aneja’s ASIL-B main-domain integrity to Garg’s additional lower-level domain, because Aneja already assigns the less stringent ASIL B level to a domain that is monitored by an ASIL D domain.
As to claim 7,
The circuit of claim 1 is rejected as set forth above.
Aneja does not disclose wherein the third power domain is a child power domain of the second power domain and the second power domain is child of the first power domain.
However, Garg discloses wherein the third power domain is a child power domain of the second power domain and the second power domain is child of the first power domain (“p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “a domain may be a group of logic units or function units that are controlled by a particular supervisor”; “FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and make the third power domain a child power domain of the second power domain and the second power domain child of the first power domain, as taught by Garg, to obtain the parent/child tree used in Garg’s multi-level hierarchy.
As to claim 8,
The circuit of claim 1 is rejected as set forth above.
Aneja discloses that additional domains may exist (“the remainder of the disclosure may refer to a MD 212 and an SD 214, but the reader is to understand that there may be more than one MD and/or more than one SD”).
Aneja does not disclose further comprising a fourth power domain, wherein the fourth power domain is a child power domain of the third power domain and the fourth power domain is at a fourth hierarchy level.
However, Garg discloses a fourth power domain that is a child of a third-level domain at a further hierarchy level (“FIG. 8 illustrates a multi-level hierarchy of HPM”; “p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and add a fourth power domain that is a child power domain of the third power domain and is at a fourth hierarchy level, as taught by Garg, to continue the same parent/child hierarchy one additional level.
As to claim 9,
The circuit of claim 1 is rejected as set forth above.
Aneja discloses that additional domains may exist (“there may be more than one MD and/or more than one SD”).
Aneja does not disclose further comprising a fourth power domain, wherein the fourth power domain is a child power domain of the second power domain.
However, Garg discloses multiple child domains under the same mid-level supervisor (“FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”; “a domain may be a group of logic units or function units that are controlled by a particular supervisor”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Aneja and add a fourth power domain that is a child power domain of the second power domain, as taught by Garg, so that one mid-level domain monitors more than one child domain.
As to claim 10,
The circuit of claim 1 is rejected as set forth above.
Aneja further discloses wherein the circuit is integrated into a component of an electric vehicle (“FIG. 1 is a block diagram of an example vehicle 100 with an in-vehicle system”; “the vehicle 100 may include an in-vehicle ADAS/IVI electrical control unit (ECU) 102”; “power supply monitoring in in-vehicle systems, such as advanced driver assistance systems (ADASs), in-vehicle infotainment (IVI) systems, and/or automated driving (AD) systems”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Aneja in view of Garg.
As to claim 11,
Aneja discloses in Figs. 2–3:
receiving, by one or more sensor hubs of a first power domain at a first hierarchy level, one or more first voltage measurements from one or more voltage sensors associated with a second power domain at a second hierarchy level (SD PMIC 224, sensing input 328, MD PMIC power supply rail 242 as shown in Fig. 3) (“The MD PMIC power supply rail 242 may be coupled to a sensing input 328 (e.g., an analog-to-digital converter (ADC) channel, remote sense pins, or another circuit configured to measure the voltage of the power supply rail 242) of one or more of the SD PMICs 224”; “the SD PMIC(s) 224 may monitor the MD PMIC power supply rail 242”).
Aneja does not disclose receiving, by one or more sensor hubs of the second power domain at the second hierarchy level, one or more second voltage measurements from one or more voltage sensors associated with a third power domain at a third hierarchy level; and based on the one or more second voltage measurements, sending from the second power domain an indication of one or more voltage errors associated with the third power domain at the third hierarchy level.
However, Garg discloses in Figs. 8, 9A–9B:
receiving, by one or more sensor hubs of the second power domain at the second hierarchy level, one or more second voltage measurements from one or more voltage sensors associated with a third power domain at a third hierarchy level (“p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “FIG. 8 illustrates a multi-level hierarchy of HPM”; “each instance of p-unit is capable of autonomously managing local dedicated resources and contains structures to aggregate data and communicate between instances”); and
based on the one or more second voltage measurements, sending from the second power domain an indication of one or more voltage errors associated with the third power domain at the third hierarchy level (“These parameters may then be communicated to supervisee p-units, or directly to controlled or monitored entities”; “second fabric 111 is used for higher priority communication between supervisor p-unit 102 and supervisee p-unit 103. Example of higher priority communication include a message to throttle because of a possible thermal runaway condition, reliability issue, etc.”; “power and thermal thresholds are communicated by supervisor p-unit 102 to supervisee p-units 103”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of Aneja and receive, by one or more sensor hubs of the second power domain at the second hierarchy level, one or more second voltage measurements from one or more voltage sensors associated with a third power domain at a third hierarchy level, and based on the one or more second voltage measurements, send from the second power domain an indication of one or more voltage errors associated with the third power domain at the third hierarchy level, as taught by Garg, so that the mid-level domain both measures a child third-level domain and forwards an error indication instead of routing every child sense line to the first-level domain.
As to claim 12,
The method of claim 11 is rejected as set forth above.
Aneja further discloses sending from the first power domain, based on the one or more first voltage measurements, an indication of one or more voltage errors associated with the second power domain at the second hierarchy level (“when the SD PMIC(s) 224 determine that the MD PMIC power supply rail 242 is in a fault state, the SD PMIC(s) 224 may inform the SD 214 of the SoC 210 that the MD PMIC 222 is experiencing an error (e.g., a functional safety (FuSa) error)”; “The SD PMIC 224 may have an output 374 coupled to an input 375 of the SD 214 and may be used to indicate to the SD 214 whether the MD PMIC power supply rail 242 has a voltage outside an acceptable voltage range or below a threshold voltage value and is experiencing a fault”).
As to claim 13,
The method of claim 11 is rejected as set forth above.
Aneja does not disclose wherein the second power domain is at least one hop away from the first power domain and the third power domain is at least two hops away from the first power domain.
However, Garg discloses wherein the second power domain is at least one hop away from the first power domain and the third power domain is at least two hops away from the first power domain (“FIG. 8 illustrates a multi-level hierarchy of HPM”; “p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of Aneja and place the second power domain at least one hop away from the first power domain and the third power domain at least two hops away from the first power domain, as taught by Garg, for the same reason given for claim 2.
As to claim 14,
The method of claim 11 is rejected as set forth above.
Aneja further discloses wherein the first power domain is compliant with Automotive Safety Integrity Level (ASIL) D and the second power domain is compliant with ASIL B (“the MD 212 and one or more MD PMIC(s) 222 meet the integrity requirements of up to automotive safety integrity level (ASIL) B. The SD 214 and one or more SD PMIC(s) 224 may meet the integrity level of up to ASIL D”).
As to claim 15,
The method of claim 11 is rejected as set forth above.
Aneja discloses wherein the first power domain is compliant with Automotive Safety Integrity Level (ASIL) D, the second power domain is compliant with ASIL B (“the MD 212 and one or more MD PMIC(s) 222 meet the integrity requirements of up to automotive safety integrity level (ASIL) B. The SD 214 and one or more SD PMIC(s) 224 may meet the integrity level of up to ASIL D”; para 0026-0027).
Aneja does not disclose and the third power domain is compliant with ASIL B or lower.
However, Garg discloses additional lower-level domains in the hierarchy (“FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of Aneja and make the third power domain compliant with ASIL B or lower, as taught by applying Aneja’s ASIL-B assignment to Garg’s additional lower-level domain, for the same reason given for claim 6.
As to claim 16,
The method of claim 11 is rejected as set forth above.
Aneja does not disclose wherein the third power domain is a child power domain of the second power domain and the second power domain is child of the first power domain.
However, Garg discloses wherein the third power domain is a child power domain of the second power domain and the second power domain is child of the first power domain (“p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “a domain may be a group of logic units or function units that are controlled by a particular supervisor”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of Aneja and make the third power domain a child power domain of the second power domain and the second power domain child of the first power domain, as taught by Garg, for the same reason given for claim 7.
As to claim 17,
The method of claim 11 is rejected as set forth above.
Aneja does not disclose wherein the second power domain is a parent power domain for voltage monitoring of a fourth power domain.
However, Garg discloses wherein the second power domain is a parent power domain for voltage monitoring of a fourth power domain (“p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “FIGS. 9A-B illustrate multiple supervisor power management components that manage a plurality of domains where some supervisor components are supervisee components of another supervisor component”; “a domain may be a group of logic units or function units that are controlled by a particular supervisor”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of Aneja and make the second power domain a parent power domain for voltage monitoring of a fourth power domain, as taught by Garg, so that one mid-level domain parents more than one child domain.
As to claim 18,
The method of claim 11 is rejected as set forth above.
Aneja further discloses wherein the circuit is integrated into a component of an electronic control unit that is used to implement safety critical functions with an electric vehicle (“FIG. 1 is a block diagram of an example vehicle 100 with an in-vehicle system”; “the vehicle 100 may include an in-vehicle ADAS/IVI electrical control unit (ECU) 102”; “since the SoC 210 may be performing safety-critical applications”).
As to claim 19,
Aneja discloses in Figs. 1–3:
a vehicle comprising: (“FIG. 1 is a block diagram of an example vehicle 100 with an in-vehicle system”)
a circuit using hierarchical voltage monitoring, the circuit comprising: (“FIG. 3 is a block diagram of an example ADAS/ IVI ECU 302 with main and safety domain PMIC power supply rail monitoring”)
a first power domain at a first hierarchy level, the first power domain comprising one or more first hierarchy level sensor hubs (SD 214 and SD PMIC(s) 224 as shown in Fig. 3) (“The MD PMIC power supply rail 242 may be coupled to a sensing input 328 … of one or more of the SD PMICs 224”);
a second power domain at a second hierarchy level, the second power domain comprising one or more second hierarchy level sensor hubs (MD 212 and MD PMIC(s) 222 as shown in Fig. 3) (“The SD PMIC power supply rail 244 may be coupled to a sensing input 326 … of one or more of the MD PMICs 222”); and
wherein the one or more first hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the second power domain (“the at least one SD PMIC has an input coupled to the MD PMIC power supply rail for monitoring the MD PMIC power supply rail”).
Aneja does not disclose a third power domain at a third hierarchy level, wherein the one or more second hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the third power domain at the third hierarchy level, and wherein the one or more first hierarchy level sensor hubs are connected with one or more voltage sensors for monitoring the second power domain at a third hierarchy level.
However, Garg discloses those limitations as mapped under claim 1 (“FIG. 8 illustrates a multi-level hierarchy of HPM”; “p-unit 108 is a supervisee p-unit for supervisor 102 while p-unit 108 is a supervisor p-unit for supervisee 109”; “the p-units in each die can be configured as a supervisor p-unit 102, supervisee p-unit 103 or with a dual role of supervisor/supervisee 105”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the vehicle of Aneja and implement a third power domain at a third hierarchy level, connect the one or more second hierarchy level sensor hubs with one or more voltage sensors for monitoring the third power domain at the third hierarchy level, and connect the one or more first hierarchy level sensor hubs with one or more voltage sensors for monitoring the second power domain at a third hierarchy level, as taught by Garg, for the same reason given for claim 1.
As to claim 20,
The vehicle of claim 19 is rejected as set forth above.
Aneja further discloses wherein the first power domain is compliant with Automotive Safety Integrity Level (ASIL) D and the second power domain is compliant with ASIL B (“the MD 212 and one or more MD PMIC(s) 222 meet the integrity requirements of up to automotive safety integrity level (ASIL) B. The SD 214 and one or more SD PMIC(s) 224 may meet the integrity level of up to ASIL D”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUNG X NGUYEN whose telephone number is (571)272-1967. The examiner can normally be reached 10:30am-6:30pm M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 9/5/26
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