Prosecution Insights
Last updated: August 17, 2026
Application No. 19/026,120

POWER SUPPLY CIRCUIT HAVING POSITIVE AND NEGATIVE OUTPUT VOLTAGES

Non-Final OA §102§103
Filed
Jan 16, 2025
Priority
Nov 05, 2024 — CN 202411562763.5
Examiner
MOODY, KYLE J
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lite-On Technology Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
506 granted / 559 resolved
+22.5% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
15 currently pending
Career history
572
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
32.7%
-7.3% vs TC avg
§102
35.2%
-4.8% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 559 resolved cases

Office Action

§102 §103
DETAILED ACTION This office action is in response to the application filed on 1/16/25. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (CN108390569, see translation presented by Applicant, hereinafter Xu). Regarding Claim 1, Xu discloses a power supply circuit (fig. 4) having positive (U1) and negative (U2) output voltages, comprising: a primary side circuit (Np side) comprising: a resonant converter (31, p.2 ¶2); a transformer (32), wherein the transformer comprises a primary side winding (Np) and a secondary side winding (Ns), and the resonant converter is connected to the primary side winding; and a secondary side circuit comprising: a positive voltage output circuit (Ns, D1, D2, C1) connected to the secondary side winding and configured to output a positive output voltage; and a negative voltage output circuit (Ns, D3, D4, C2) connected to the secondary side winding and configured to output a negative output voltage (p.2, ¶3). Regarding Claim 2, Xu discloses (fig. 4) the secondary side winding of the transformer comprises a first secondary side subwinding (Ns1) and a second secondary side subwinding (Ns2); wherein a first terminal of the first secondary side subwinding is connected to the positive voltage output circuit (U1), and a second terminal of the first secondary side subwinding is connected to ground (GND); wherein a first terminal of the second secondary side subwinding is connected to ground (GND), and a second terminal of the second secondary side subwinding is connected to the positive voltage output circuit (via D2) and the negative voltage output circuit (via D4). Regarding Claim 3, Xu discloses (fig. 4) the negative voltage output circuit (Ns, D3, D4, C2) comprises: a first inverter diode (D4); and an inverter capacitor (C2); wherein a cathode of the first inverter diode is connected to the second terminal of the second secondary side subwinding, (Ns2) an anode of the first inverter diode is connected to a first terminal of the inverter capacitor (C2), and a second terminal of the inverter capacitor is connected to ground (+ to GND). Regarding Claim 4, Xu discloses (fig. 4) a voltage of the inverter capacitor is the negative output voltage (U2, GND). Regarding Claim 5, Xu discloses (fig. 4) the negative voltage output circuit (Ns, D3, D4, C2) further comprises: a second inverter diode (D3), wherein a cathode of the second inverter diode is connected to the first terminal of the first secondary side subwinding (Ns1), and an anode of the second inverter diode is connected to the first terminal of the inverter capacitor (C2). Regarding Claim 9, Xu discloses (fig. 4) the positive voltage output circuit (Ns, D1, D2, C1) comprises: a first diode (D1); and an output capacitor (C1); wherein an anode of the first diode is connected to the first terminal of the first secondary side subwinding (Ns1), a cathode of the first diode is connected to a first terminal of the output capacitor (C1 +), a second terminal of the output capacitor is connected to ground (GND), and a voltage of the output capacitor is the positive output voltage (U1, GND). Regarding Claim 10, Xu discloses (fig. 4) the positive voltage output circuit (Ns, D1, D2, C1) further comprises: a second diode (D2), wherein an anode of the second diode is connected to the second terminal of the second secondary side subwinding (Ns2), and a cathode of the second diode is connected to the first terminal of the output capacitor (C1 +). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6-8 are rejected under 35 U.S.C. 103(a) as being unpatentable over Xu in view of Goto et al. (US20240006989, hereinafter Goto). Regarding Claim 6, Xu discloses (fig. 4) the negative voltage output circuit (Ns, D3, D4, C2) comprises: a first diode (D4); and an inverter capacitor (C2); wherein a first terminal of the first diode is connected to the second terminal of the second secondary side subwinding, (Ns2) a second terminal of the first diode is connected to a first terminal of the inverter capacitor (C2), and a second terminal of the inverter capacitor is connected to ground (+ to GND). Xu does not disclose the first diode is a first transistor. Goto discloses (fig. 5) the first diode (D2) is a first transistor (¶24). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xu to substitute transistors for diodes as disclosed in Goto to implement control and improve efficiency of the circuit. Regarding Claim 7, Xu discloses (fig. 4) a voltage of the inverter capacitor is the negative output voltage (U2, GND). Regarding Claim 8, Xu discloses (fig. 4) the negative voltage output circuit (Ns, D3, D4, C2) further comprises: a second diode (D3), wherein a first terminal of the second diode is connected to the first terminal of the first secondary side subwinding (Ns1), a second terminal of the second diode is connected to the first terminal of the inverter capacitor (C2). Xu does not disclose the second diode is a second transistor. Goto discloses (fig. 5) the second diode (D1) is a second transistor (¶24). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xu to substitute transistors for diodes as disclosed in Goto to implement control and improve efficiency of the circuit. Claim 11 is rejected under 35 U.S.C. 103(a) as being unpatentable over Xu in view of Wu (US20170079099) further in view of Nishino et al. (US20100109571, hereinafter Nishino). Regarding Claim 11, Xu does not disclose the power supply circuit further comprises a feedback circuit, a coupling circuit, a resonant control circuit, a protection circuit and a correction control circuit, and the primary side circuit further comprises a filter circuit, a bridge rectifier and a power factor correction circuit; wherein the feedback circuit is configured to output a feedback signal according to the positive output voltage or the negative output voltage; wherein the resonant control circuit is configured to receive the feedback signal from the feedback circuit through the coupling circuit and receive a voltage threshold from the protection circuit, and configured to compare the feedback signal with the voltage threshold to control the resonant control circuit; wherein the filter circuit is configured to filter an alternating current input voltage to form a filtered voltage, the bridge rectifier rectifies the filtered voltage to output a rectified voltage, and the power factor correction circuit is configured to output a direct current input voltage to the resonant control circuit according to the rectified voltage. Wu discloses a power supply circuit (fig. 1) comprising a feedback circuit (IL1, IL2, Vo1, Vo2 to 60 to (32, 34), a coupling circuit (coupling at 60), a control circuit (60), a protection circuit (circuit providing a preset target value, S140 of fig. 3, ¶57) and a correction control circuit (60), and the primary side circuit further comprises a bridge rectifier (10, ¶27) and a power factor correction circuit (20); wherein the feedback circuit is configured to output a feedback signal according to the positive output voltage or the negative output voltage (Vo1 or Vo2); wherein the resonant control circuit is configured to receive the feedback signal from the feedback circuit through the coupling circuit and receive a voltage threshold from the protection circuit (¶57), and configured to compare the feedback signal with the voltage threshold to control the resonant control circuit (¶58); an alternating current input voltage (AC), the bridge rectifier rectifies the filtered voltage to output a rectified voltage, and the power factor correction circuit is configured to output a direct current input voltage to the resonant control circuit according to the rectified voltage (20 output). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xu to include control system as disclosed in Wu to minimize switching loss of the resonant converter and improve the efficiency of the system. Nishino discloses (fig. 1a primary circuit comprises a filter circuit (34) wherein the filter circuit is configured to filter an alternating current input voltage (32) to form a filtered voltage (to DB). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xu to include an AC filter as disclosed in Nishino to smooth the input current from high frequency components thus improving efficiency and quality of resonant system. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20030090247, Patel, Amrit P. discloses a leading-edge modulator for post regulation of multiple output voltage power supplies. US 20060170288, Usui; Hiroshi discloses a resonant DC-DC converter of multi-output type. US 20140268930, MENDENHALL E discloses an apparatus for providing power supply for half bridge class D amplifier, controls transfer of charge through rectifiers of power supply circuit to compensate off side charging of capacitors on positive and negative supply voltages. US 20160006361, Park; Sang Gab et al. discloses a multi-output power supply apparatus and output circuit thereof. US 20160079872, RYU; Dong Kyun et al. discloses a power converter. US 20240223088, XU; Kuiwei discloses a circuit, fan system, and transformer for power conversion. US 6317337 Yasumura; Masayuki discloses a switching power supply circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYLE J MOODY/ Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jan 16, 2025
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+7.8%)
2y 0m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 559 resolved cases by this examiner. Grant probability derived from career allowance rate.

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