DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is accepted.
Drawings
The formal drawings are accepted.
Conclusion
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitation “a test controller configured to generate a test sequence to the interface circuit to control the device and enable a simulation performed by a simulator having a design associated with the device; wherein the test sequence includes identifying a mismatch pattern between a final scan pattern from a final scandump and a simulation pattern from the simulation, the mismatch pattern corresponding to a fault”. It does not particularly point out how the test sequence generated by the test controller to control the device and further enable a simulation performed by a simulator. Are both operations (scanning to identify a fault and enabling simulations) performed simultaneously (in parallel) or one at a time? Interconnections between the test controller, the device and the simulator are confusing and for the most part not detailed or mentioned in the claim. It is difficult to translate the claim and follow what processes are taking place. Further, it is not clear if the scan pattern and simulation pattern are compared to identify the mismatch pattern corresponding to a fault? Or what type of operation is made to identify the mismatch pattern. Clarification is required. Independent claims 11 and 20 are rejected for similar reasons. Dependent claims are rejected based on dependency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 9-11, 13, 19, and 20 are rejected under 35 U.S.C. 102(a) (2) as being anticipated by Deng et al. “herein Deng” (U.S. PN: 12,211,570).
As per claim 1, 11, and 20:
Deng substantially teaches a system, a semiconductor device, and a test circuit (see col. 3, lines 53-57 and col. 4, lines 28-36) comprising: an interface circuit (see figure 2, “test interface 260” and col. 3, 62-67) configured to communicate with a device under test (see “a chip under test, 210” and col. 3, lines 54-67) to obtain a test scandump from a scandump storage (“a dump controller”) corresponding to an internal circuit of the device (see col. 4, lines 37-45) and a test controller (see figure 3, “test circuit may comprise a control module 310”) configured to generate a test sequence to the interface circuit to control the device and enable a simulation performed by a simulator (see figure 2, “a circuit simulator 255”) having a design associated with the device (see col. 4, lines 37-53); wherein the test sequence includes identifying a mismatch pattern between a final scan pattern from a final scandump and a simulation pattern from the simulation, the mismatch pattern corresponding to a fault (see col. 2. lines 58-67 to col. 3, lines 1-11, col. 3, lines and col. 4, lines 54-67 to col. 5, lines 1-16).
As per claims 3 and 13:
Deng in view of the above rejection teaches a scandump circuit located internally to the device and configured to provide timing and control signals to match with functionalities of the simulator (see col. 2. lines 58-67 to col. 3, lines 1-11, col. 5, lines 57-67 to col. 6, lines 1-67).
As per claims 9:
Deng in view of the above rejection teaches wherein the device is a semiconductor device (see col. 2, lines 53-63).
As per claims 10 and 19:
Deng in view of the above rejection teaches wherein the simulator is one of a register transfer language (RTL) simulator, a netlist simulator, and a gate-level simulator (see figure 2 element 255).
Allowable subject matter
Claims 2, 4-8, 12, and 14-18 are objected to as being dependent upon a rejected base claim but would be allowable if the base claims rewritten independent from including all of the limitation of the base claim and any intervening claim and overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Below are Examiner's reasons for indication of allowable subject matter:
The claimed invention (claims 2 and 12) comprises “wherein the test sequence further comprises: activating the device to run N cycles; stopping the device after N cycles to obtain a first scandump containing a first scan pattern from the device; performing a first simulation using the first scan pattern for M cycles to obtain the simulation pattern; activating the device to run M cycles; stopping the device after M cycles to obtain a second scandump containing the final scan pattern from the device; and comparing the final scan pattern with the simulation pattern” which the prior art do not teach or render obvious. Claims depend upon one of claims 4 and 14 and, therefore, also comprise allowable subject matter.
The claimed invention (claims 4 and 14) comprises “a clock control circuit configured to control a clock signal that provides the timing signals to the internal circuit; a counter configured to assert a stop signal when a count is reached, the counter being clocked by the clock signal; an input gating circuit configured to capture activities at inputs of the internal circuit in an input enable mode and disable the inputs in an input disable mode; an event capture circuit configured to capture an event related to the simulation; and a transfer circuit configured to transfer outputs of the internal circuit to the scandump storage” which the prior art do not teach or render obvious. Claims depend upon one of claims 4 and 14 and, therefore, also comprise allowable subject matter.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ahsan et al. “herein Ahsan” US 2024/0289241 teaches in yet another technique, and in known scan dumps, a scan chain includes all the flip-flops in an integrated circuit (IC) design. If there is any failure, especially a hang case, all the flip-flop values can be dumped at a particular steady state time using the scan feature. This involves analysis of a very high number of flip-flops in the design and a very slow process. Another technique is to reproduce an issue in a simulation model. Here, a test in silicon first needs to be converted into a simulation friendly test, and then run in the simulation or emulation model ([0027-0028]).
Abdel-Hafez et al. (7,210,082) teach Automatic test pattern generation (ATPG) in conjunction to fault simulation are used to generate the scan data patterns to test faults in the scan-based integrated circuit, and to measure the fault coverage of the scan data patterns during scan-test. Fault simulation is also used independently to measure the fault coverage of pseudorandom stimuli during self-test. Faults tested include stuck-at faults, transition faults either launched from shift or launched from capture, path-delay faults either launched from shift or launched from capture, IDDQ (IDD quiescent current) faults, and bridging faults. In order to simplify the ATPG and fault simulation process, a cycle-based logic simulator, as opposed to a full timing logic simulator, is embedded within the ATPG and fault simulation engine, which is used to perform the logic simulation of the capture operation during scan-test or self-test. Since the clock skew between different clock domains can vary greatly, it makes it unfeasible to try to apply the clocks of different clock domains simultaneously during the capture operation, since the clock skew between the different clock domains would result in incorrect values being simulated by the cycle-based simulator when compared to results in the actual scan-based integrated circuit.
Huang et al. (U.S. PN: 7,788,561) teach in a method act 440, one or more faulty scan cell suspects are identified. For example, in some embodiments, a failure log file for the scan test is read. With compressed scan test patterns, the method acts 120, 130 of the method 100, described above for non-compressed patterns, can be performed for the compressed test patterns by performing fault simulation of the faulty scan chain(s) against the transformed circuit. The compacted simulation results can be compared with the compacted failure data collected from the tester. The best matching scan cell(s) can be reported as suspect(s).
Gorti et al. (U.S. PN: 8,633,725) describe Each scan cell of the scan chain serves as both a control and an observation point for Automatic Test Pattern Generation (ATPG) testing and fault simulation. ATPG tools automatically generate test patterns for use in the scan chains. Automatic Test Equipment (ATE) shifts these test patterns into the scan chains and supplies, or causes to be supplied, one or more clock pulses to the core logic. The responses to the test patterns are captured within the scan cells and the results are shifted out of the scan chain. ATE then compares the results with expected results to determine if a fault is present.
Birmiwal et al. (U.S. PN: 7,386,775) teach Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (`DUT`), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain. In FIG. 5 sets forth a flow chart illustrating an exemplary method for verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain according to embodiments of the present invention that includes identifying (501) expected values (502) of the beginning of a scan chain for a test pattern (503); scanning (504) the test pattern through the scan inputs into the beginning of the scan chain; and comparing (508) the expected values with the contents of the beginning of the scan chain after scanning in the test pattern. In silicon, comparing values anywhere in a scan chain with expected values requires scanning the values in the scan chain sequentially all the way through the scan chain to its output. In a simulation environment, however, the values of scan cells anywhere in the scan chain may be read directly in the environment. In the simulation environment, it is possible to scan a test pattern sequentially into the beginning of the scan chain and then directly compare the values in the beginning of the scan chain with expected values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
Prosecution Insights