DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 1 is objected to because of the following informalities: The examiner suggest amending the claim to include a colon after the word “comprising” in line 1 to separate the preamble and the limitations of the claims. Appropriate correction is required.
Claim 1 is objected to because of the following informalities: The claims recite the acronyms “PUF” and “NMOS” without spelling out the acronym at its first occurrence. The Examiner suggest the acronym to be spelled out to recite “Physically unclonable function” and “N-type Metal-Oxide- Semiconductor” as disclosed in paragraphs [0003 & 0006] of Applicant’s specification. Appropriate correction is required.
Claim 5 is objected to because of the following informalities: The claims recite the acronym “PMOS” without spelling out the acronym at its first occurrence. The Examiner suggest the acronym to be spelled out to recite “P-type Metal-Oxide-Semiconductor” as disclosed in paragraph [0011] of Applicant’s specification. Appropriate correction is required.
Claims 2-9 are objected to because of the following informalities: The examiner suggest amending the limitation where the claims in which it depends upon starts with a lower case (“claim 1,”). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitations "the k-th transmission gate" and “the k-th selection terminal” in lines 6-7. There are insufficient antecedent basis for these limitations in the claim.
Allowable Subject Matter
Claims 1-9 would be allowable if rewritten or amended to overcome the claim objections and rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Examiner’s Statement of Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: After a fully conducted search and consideration, the prior art either taken alone or in combination neither anticipates nor render obvious to the claimed subject matter of the instant application. The closest prior art LU et al. (US Pub No. 2023/0388135) discloses a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature. (LU, Abstract), which is equivalent to independent claim limitations “a current mode weak-PUF circuit with rich challenge-response pairs, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays, two transmission gate arrays and one shared head, wherein each PUF array comprises 2'I column units, q is an integer greater than 1, each column unit comprises 2P NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS transistor, the two PUF arrays are designated a first PUF array and a second PUF array respectively, and the two transmission gate arrays are designated a first transmission gate array and a second transmission gate array respectively; generate one response and output the one response to the first transmission gate array, the first PUF array generates and outputs 2q responses to the first transmission gate array; the second decoder is used to access second p challenge signals in one set, decode the second p challenge signals into another 2P row selection signals and output the to generate another one response and output the another one response to the second transmission gate array, the second PUF array generates and outputs another 2n responses to the second transmission gate array”; other relevant prior art Bhunia et al. (US Pub No. 2026/0039485) discloses an apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage. (Bhunia, Abstract), WANG et al. (US Pub No. 2019/0058602) discloses multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1.sup.st inverter, a 2.sup.nd inverter, a 3.sup.rd inverter, a 4.sup.th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The m.sup.th output terminal of the row decoder is connected to the m.sup.th row selective signal input terminals of the 32 PUF arrays. The j.sup.th output terminal of the column decoder is connected to the j.sup.th selective signal input terminals of the 32 PUF arrays. The 1.sup.st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2.sup.nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance. (WANG, Abstract), Raghavan et al. (US Patent No. 11,881,258) discloses an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier. (Raghavan, Abstract), Li et al. (US Pub No. 2019/0342106) discloses Physically unclonable function (PUF) circuits employing multiple PUF memories to decouple a PUF challenge input from a PUF response output for enhanced security. The PUF circuit includes a PUF challenge memory and a PUF response memory. In response to a read operation, the PUF challenge memory uses a received PUF challenge input data word to address PUF challenge memory arrays therein to generate a plurality of intermediate PUF challenge output data words. The PUF response memory is configured to generate a second, final PUF response output data word in response to intermediate PUF challenge output data words. In this manner, it is more difficult to learn the challenge-response behavior of the PUF circuit, because the PUF challenge input data word does not directly address a memory array that stores memory states representing final logic values in the PUF response output data word. (Li, Abstract), and Wang et al. (US Patent No. 10,432,198) discloses a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed. (Wang, Abstract), however, the prior art taken alone or in combination fails to teach or suggest “the third decoder is used to access first q challenge signals in one set and decode the first q challenge signals into 2 selection signals and output the 2q selection signals to the first transmission gate array; the fourth decoder is used to access second q challenge signals and decode the second q challenge signals into another 2 selection signals and output the another 2 selection signals to the second transmission gate array; the first transmission gate array is controlled by the 2n selection signals output by the third decoder, the first transmission gate array is used to select one of the 2'I responses output by the first PUF array and output the one of the 2' responses to the shared header; the second transmission gate array is controlled by the 21 selection signals output by the fourth decoder, the second transmission gate array is used to select one of the another 2 1 responses output by the second PUF array and output the one of the another 21 responses to the shared header; the shared header is used to compare the one of the 2n responses output by the first transmission gate array with the one of the another 2 responses output by the second transmission gate array, and generate and output a final PUF response according to a comparison result” (as recited in claim 1). Claims are allowed in light of the above claim limitations when in combination with the remaining claim limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAQUEAL D WADE whose telephone number is (571)270-0357. The examiner can normally be reached M-F 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Thiaw can be reached at 571-270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAQUEAL D WADE-WRIGHT/Primary Examiner, Art Unit 2407
Prosecution Insights