DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This initial written action is responding to the communication dated on 01/17/2025.
Claims 1-2 are submitted for examination.
Claims 1-2 are pending.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
This application filed on January 17, 2025 claims priority of Foreign application CN202411330169.3 filed on September 24, 2024.
Information Disclosure Statement
The following Information Disclosure Statements in the instant application submitted in compliance with the provisions of 37 CFR 1.97, and thus, have been fully considered:
IDS filed on 17 January 2025.
Claim Objections
Claim 1 objected to because of the following informalities:
Claim 1 recites a limitation, “…A method for improving an ability of a strong PUF (physically unclonable function) to resist machine learning attacks…”. The claim should recite “physical unclonable function (PUF)”.
Claim 1 recites a limitation, “….when a strong PUF need to generate a PUF response sequence..”. The claim should recite, “…when the strong PUF need to generate a PUF response sequence..”.
Claim 1 recites a limitation, “…if the PUF response generated currently is the first PUF response of the PUF response sequence..”. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites a limitation, “…if the PUF response generated currently is not the first PUF response of the PUF response sequence..”. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites a limitation, “…before generating a PUF response for the PUF response sequence each time..”. Examiner suggest changing “before” to “prior to”.
Claim 1 recites a limitation, “…..before generating a PUF response for the PUF response sequence each time, obfuscating a current challenge of the strong PUF to generate a cryptographic challenge, so that the strong PUF generates the PUF response under an action of cryptographic challenge…”. Examiner suggest rewriting the limitation as “…..prior to generating a PUF response for the PUF response sequence each time, obfuscating a current challenge of the strong PUF to generate a cryptographic challenge, in order for the strong PUF to generate the PUF response under an action of cryptographic challenge…”.
Claim 1 recites a limitation, “…performing conversion on a Rubik's cube matrix on a basis of the current challenge to generate a cryptographic matrix..”. Examiner suggest replacing the limitation as “…performing conversion on a Rubik's cube matrix based on the current challenge to generate a cryptographic matrix..”
Claim 1 recites a limitation, “…wherein if the PUF response generated currently is the first PUF response of the PUF response sequence, the Rubik's cube matrix that generates the cryptographic challenge in the current obfuscation is randomly generated..”. Examiner suggest replacing “if” with “when”.
Claim 1 recites a limitation, “….if the PUF response generated currently is not the first PUF response of the PUF response sequence, the Rubik's cube matrix that generates the cryptographic challenge in the current obfuscation is a cryptographic matrix generated by a previous obfuscation”. Examiner suggest replacing “if” with “when”.
Claim 1 recites words, “firstly”, “then”, “finally, “currently”. Examiner suggest removing these words from the claim.
Appropriate correction is required.
Claim 2 objected to because of the following informalities:
Claim 2 recites “if” multiple times. Examiner suggest replacing “if” with “when”.
Claim 2 recites a limitation, “..firstly generating six 8*8 Rubik's cube matrices for challenge obfuscation on a computer side..”. Examiner suggest removing “firstly” from the claim limitation.
Claim 2 recites a limitation, “…and then returning to step 2 for next challenge obfuscation until the strong PUF produces a desired PUF response sequence..”. Examiner suggest removing “then” from the claim limitation.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites a limitation, “….when the strong PUF needs to generate the PUF response sequence, firstly generating six 8*8 Rubik's cube matrices for challenge obfuscation on a computer side…”. The claim recites on a computer side, however it is not clear how many devices are participating in a challenge response.
Claims 1-2: Objected
Claims 1-2 are objected to as being allowable if the 35 U.S.C 112 rejection and Claim objections are overcome. The following is an examiner’s statement of reason for allowance.
Chung et al. (US PGPUB. # US 2023/0013730) discloses, a device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor. (Abstract). In operation 810, in FIG. 1, the physical unclonable function (PUF) generator 100 receives the challenge input 101. In operation 820, as shown in FIG. 2, the bit cell BC in the PUF cell array 110 is accessed for the read operation or the write operation in response to a word line address associated with the challenge input 101. Accessing the bit cell BC further includes operations of in the read operation comparing by the sense amplifier 141 the voltage, for example, the voltage at the terminal, coupled to the first data line BL11, of the memory cell 310 in FIG. 4A with the voltage, for example, the voltage at the terminal, coupled to the second data line BL22, of the memory cell 320 to generate the output signal OUT shown in FIG. 5. The other terminals of the memory cells 310-320 are coupled together to receive the read voltage V.sub.READ applied on the source line SL. Accessing the bit cell BC further includes operations of in the read operation, transmitting the read voltage from the source line SL to the other terminals of the memory cells 310-320 by the transistor Tr coupled between the source line SL and the other terminals of the memory cell 310-320. Accessing the bit cell BC further includes operations of in the read operation, charging the first data line, for example, BL11 coupled to the terminal of the memory cell 310 to have the voltage level of the voltage V1 from a voltage level of, for example, 0 Volts, by a signal, for example, the current I.sub.L from the memory cell 310. Accessing the bit cell BC further includes operations of in the read operation charging the second data line, for example, BL21 coupled to the terminal of the memory cell 320 to have the voltage level of the voltage V2 from a voltage level of, for example, 0 Volts, by a signal, for example, the current I.sub.R from the memory cell 320. accessing the bit cell BC further includes operations of in the read operation turning the transistor Tr by applying the word line voltage, for example, the voltage VDD, at the control terminal of the transistor Tr. Accessing the bit cell BC further includes operations of in the read operation applying the read voltage V.sub.READ on the source line SL. In some embodiments, the read voltage V.sub.READ is smaller than the voltage (e.g., the voltage VDD) applied on the word line and is greater than 0 Volts. in the read operation, the memory cell 310 has the resistance state, and the memory cell 320 has the other resistance state different from that of the memory cell 310, as shown in FIGS. Accessing the bit cell BC further includes operations of in the write operation applying a voltage, for example, the voltage VDD at the terminals, coupled to the first data line BL11 and the second data line BL22, of the memory cells 310 and 320 and applying the voltage, for example, a grounded voltage smaller than the voltage VDD, on the source line SL. In some embodiments, the voltage VDD is different from the voltages V1 and V2. As discussed in the write operation above, specifically, the resistance state of one of the memory cells 310-320, for example, the memory cell 310 of FIG. 4A, is altered to the parallel resistance state, from the anti-parallel resistance state, of the magnetic tunneling junction. The resistance state of the other one of the memory cells 310-320, for example, the memory cell 310 is still the anti-parallel state. (Fig. 8, ¶56-¶63).
Li et al. (CN PGPUB. # CN 117675197A) discloses, a strong PUF circuit for resisting modeling attack, belonging to the technical field of basic electronic circuits. The strong PUF circuit is an input 1 output circuit comprising: the input confusion component, the inserted bit generation component and the strong PUF component are used for applying bit excitation to the input end of the input confusion component, the bit output of the confusion component is subjected to exclusive OR operation to generate an inserted bit, the inserted bit and the output of the confusion component jointly form the bit excitation to be applied to the strong PUF component, the strong PUF component generates a bit output, and the aim of resisting the existing strong modeling attack is fulfilled on the basis of keeping the weight. (Abstract).
The invention aims to overcome the defects of the background technology, provide a modeling attack resistant strong PUF circuit, add a confusion unit at a stimulus input level to enable confusion stimulus not to be classified linearly, generate additional stimulus by using an exclusive-OR gate and add the additional stimulus to the confusion stimulus, finally apply the confusion stimulus to a strong PUF component to generate final response, and realize the aim of resisting the existing strong modeling attack on the basis of keeping the weight, thereby solving the technical problems that the existing modeling attack resistant PUF structure has the risk of being easily broken
and improves the hardware security at the cost of increasing the hardware cost.
The invention adopts the following technical scheme for realizing the purposes of the invention:
a strong PUF circuit that resists modeling attacks, being an n-input single-output circuit, comprising: a obfuscation component, an insertion bit generation component, a strong PUF component; first, n-bit input stimulus C i Applied to the input of the obfuscating component, which excites C with respect to the n-bit input i Nonlinear classification processing is carried out to output n-bit confusion excitation C i 'A'; then, the
input end of the insert bit generating component receives the n-bit confusion excitation, and carries out bitwise logic operation on the n-bit confusion excitation to generate a one-bit result, namely insert bit C split The method comprises the steps of carrying out a first treatment on the surface of the Finally, the n-bit mixed excitation output by the mixed component and the insertion bit output by the insertion bit generation component are combined to form n+1-bit excitation, the n+1-bit excitation is applied to the input end of the strong PUF component, and finally the strong PUF component generates one-bit output, namely an excitation response. (Page – 5, Lines 26-40).
Wang et al. (US PGPUB. # US 2023/0091469) discloses, an ML attack resisting method for a strong PUF. Response signals generated by applying multiple sets of different challenge signals to a strong PUF are used as information to be encrypted, and are put in order to form a plaintext matrix. Then a matrix multiplication operation is performed on two plaintext matrixes to generate a ciphertext matrix. Next, elements in a transform matrix obtained by performing binary transformation on the ciphertext matrix are used as final responses, which are in one-to-one correspondence with original challenge signals and are used as final CRPs of the matrix-encrypted strong PUF. (Abstract). Embodiment: an ML attack resisting method for a strong PUF comprises the following steps: tep 1, n.sup.2 CRPs of a strong PUF are collected, wherein n is any positive integer that is not less than 2; a challenge signal of an x.sup.th CRP of the strong PUF is denoted as C.sub.x, wherein, x=1, 2, . . . , n.sup.2, the challenge signal C.sub.x is a b-bit binary number and is expressed as c.sub.x.sup.1c.sub.x.sup.2c.sub.x.sup.3 . . . c.sub.x.sup.b, c.sub.x.sup.a represents a signal value of an a.sup.th bit of the challenge signal of the x.sup.th CRP, a=1, 2, . . . , b, the signal value c.sub.x.sup.a represents a low level when its value is 0, and represents a high level when its value is 1; a response signal of the x.sup.th CRP of the strong PUF is denoted as R.sub.x, wherein the response signal R.sub.x is a 1-bit binary number, the response signal R.sub.x represents a low level when its value is 0, and represents a high level when its value is 1, a one-to-one corresponding relationship exits in each CRP of the strong PUF, that is, the challenge signal C.sub.x passes through the strong PUF to obtain the response signal R.sub.x, and the corresponding relationship in the n.sup.2 CRPs of the strong PUF is {C.sub.1.fwdarw.R.sub.1; C.sub.2.fwdarw.R.sub.2; . . . ; C.sub.n.sub.2 .fwdarw.R.sub.n.sub.2}; Step 2, the response signals R.sub.1, R.sub.2, . . . , R.sub.n.sub.2 of the collected n.sup.2 CRPs of the strong PUF are put in order to form an n-order plaintext matrix, wherein the n-order plaintext matrix is denoted as M which is expressed by formula (1): Wherein, m.sub.ij is an element in the i.sup.th row and j.sup.th column of the plaintext matrix M, i =1,2, . . . , n, j=1,2, . . . , n, m.sub.11=R.sub.1, m.sub.12=R.sub.2, . . . , m.sub.ij=R.sub.(i−1)×n+j, . . . , and m.sub.nn=R.sub.n.sub.2; Step 3, the n-order plaintext matrix M is multiplied by itself to obtain a ciphertext matrix, wherein the ciphertext matrix is denoted as S, which is expressed by formula (2): Wherein, s.sub.ij is an element in the i.sup.th row and j.sup.th column of the ciphertext matrix S, i=1,2, . . . , n, j=1,2, . . . , n, s.sub.ij=Σ.sub.k=1.sup.nm.sub.ikm.sub.kj, and k=1,2, . . . , n; Step 4, binary transform is performed on the ciphertext matrix S to obtain a transform matrix S′, and an element in the i.sup.th row and j.sup.th column of transform matrix is denoted as s′.sub.ij, specifically: whether the element s.sub.ij is an odd number or an even number is determined; if the element s.sub.ij is an odd number, the element s′.sub.ij=1 ; or, if the element s.sub.ij is an even number, the element s′.sub.ij=0; Step 5, elements in the transform matrix S′ are sequentially used as final response signals r.sub.1˜r.sub.n.sub.2 of the strong PUF, wherein r.sub.1=s′.sub.11, r.sub.2=s′.sub.12, . . . , r.sub.(i−1)×n+j=s′.sub.ij, r.sub.n.sub.2=s′.sub.nn, at this moment, a one-to-one corresponding relationship still exists in each CRP of the strong PUF, the challenge signal C.sub.x passes through the strong PUF to obtain a final response signal r.sub.x, the challenge signal C.sub.x corresponds to the final response signal r.sub.x, and a final corresponding relationship of the n.sup.2 CRPs of the strong PUF is {C.sub.1.fwdarw.r.sub.1; C.sub.2.fwdarw.r.sub.2; . . . ; C.sub.n.sub.2.fwdarw.r.sub.n.sub.2}; and Step 6, Step 2 to Step 5 are repeated until the number of CRPs reaches a preset required value. (¶26-¶33).
However, none of the art teaches, “……..performing conversion on a Rubik's cube matrix on a basis of the current challenge to generate a cryptographic matrix, and constructing a challenge matrix based on the current challenge; then, determining a matrix multiplication pattern of the cryptographic matrix and the challenge matrix on the basis of the cryptographic matrix, multiplying the cryptographic matrix by the challenge matrix to obtain an obfuscation matrix, converting elements in the obfuscation matrix to 0 or 1 according to a parity of the elements to obtain a cryptographic challenge matrix; and finally extracting the elements in the cryptographic challenge matrix to form the cryptographic challenge, wherein if the PUF response generated currently is the first PUF response of the PUF response sequence, the Rubik's cube matrix that generates the cryptographic challenge in the current obfuscation is randomly generated; if the PUF response generated currently is not the first PUF response of the PUF response sequence, the Rubik's cube matrix that generates the cryptographic challenge in the current obfuscation is a cryptographic matrix generated by a previous obfuscation..”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Refer to PTO-892, Notice of References Cited for a listing of analogous art.
Ganji et al. (US PGPUB. # US 2023/0179434) discloses, Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.
Suresh et al. (US PGPUB. # US 2021/0110067) discloses, a method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.
Das et al. (US PGPUB. # US 2021/0103681) discloses, a reconfigurable and machine learning resilient on-chip cryptography for graphene-based devices can be configured to utilize inherent disorders associated with the carrier transport in grain boundary dominated graphene field effect transistors (GFETs). For instance, a method can be configured to model a GFET as one or more physically unclonable functions (PUFs). A GFET PUF can also be reconfigured in a way that does not involve any physical intervention and/or integration of additional hardware components. A GFET PUF can be designed to operate with ultra-low power and can be configured to be robust and reliable against variation in temperature and supply voltage in some embodiments.
Sachdev et al. (US PGPUB. # US 2019/0044739) discloses, a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARSHAN I DHRUV whose telephone number is (571)272-4316. The examiner can normally be reached M-F 9:00 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yin-Chen Shaw can be reached at 571-272-8878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DARSHAN I DHRUV/Primary Examiner, Art Unit 2498
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