DETAILED ACTION
This action is in response to the response filed on January 18, 2025. Claims 1-6 are pending. Of such, claims 1-6 represent a device directed to a self-filtering monostable PUF circuit based on hysteresis effect.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because
The abstract discloses the acronym “PUF”. As it is the first time used in the Abstract, it should be expanded upon to describe the full terms of the acronym.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
In ¶ 17, the disclosure states “FIG. 6 is a layout of a PUF units of the self-filtering monostable PUF circuit based on hysteresis effect according to the present disclosure”. The terms “a PUF units” should be corrected to either “a PUF unit” or “the PUF units”.
In ¶ 37, the disclosure states “Embodiment 6…in this embodiment, as shown in FIG. 4”. Embodiment 5 referenced FIG 4. Embodiment 6 should reference FIG 5 (the circuit diagram of a Schmitt trigger).
Appropriate correction is required.
Claim Objections
Claims 1, 3, and 4 are objected to because of the following informalities:
Claim 1 discloses “PUF ” As it is the first time used, it should be expanded to describe the full terms of the acronym.
Claim 3 discloses “characterized in that further comprising an input register” is grammatically incorrect.
Claim 3 discloses “wherein only one bit in the n-bit row selection signals is a high-level signal, and the other are low- level signals” is grammatically incorrect. The term “other” should be plural.
Claim 4 discloses the acronym “MOS”. As it is the first time used, it should be expanded to describe the full terms of the acronym. Further a person of known skill in the art would disclose “MOS transistor” or “MOSFET” rather than just MOS as that is the known terminology.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “efficiently” in claim 1 is a relative term which renders the claim indefinite. The term “efficiently” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim 1 discloses “To improve the overall stability” which is a statement of intended result. A claim limitation must define structure or function performed, not the outcome of the function. This is indefinite.
Claim 1 discloses “by adding a filter unit” which is a process based limitation inside an apparatus claim which renders the limitation indefinite. The claim in its entirety incorporates functional operations into the apparatus claim. This renders the claim indefinite as it is mixing structural elements with steps of a method.
Claim 2 discloses the term “a Schmitt trigger” which was previously disclosed in claim 1. It is unclear if this is the same Schmitt trigger as the trigger introduced in claim 1.
Claim 2 discloses the term “a filter unit” which was previously disclosed in claim 1. It is unclear if this is the same filter unit as the filter unit introduced in claim 1.
Claims 3-6 are rejected due to their dependency on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 117544320), hereinafter referred to as Chen, in view of Li et al. (NPL: A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization), hereinafter referred to as Li.
Regarding Claim 1, Chen discloses:
A self-filtering monostable PUF circuit based on hysteresis effect (On page 2, Chen discloses “The embodiment of the invention claims a physical unclonable function circuit based on Schmidt inverter” and further discloses on page 12 “the monostable structure and the cross coupling structure to design the stable conversion structure,”), the self-filtering monostable PUF circuit is characterized in that by adding a filter unit based on a Schmitt trigger (On page 5, Chen discloses “The steady-state conversion unit P comprises two Schmidt-triggered inverters S, a first gating MOS transistor X1, a second gating MOS transistor X2 and a third gating MOS transistor X3;”), utilizing the hysteresis effect of the Schmitt trigger (On page 8, Chen discloses “The Schmidt trigger type inverter S can realize the choking effect without the additional bias voltage generated by the bias circuit or the external bias voltage directly connected to the external connecting sheet, and the anti-interference capability is stronger than the external bias type choking inverter.”) to efficiently self-filter the PUF units with unstable outputs to improve the overall stability of the PUF circuit (On page 12, Chen discloses “The steady-state conversion structure provided by the application makes the PUF unit select the single-steady-state and double-steady-state structure at different times when working, which not only ensures the reliability of the evaluation stage”).
However, Chen does not explicitly disclose a PUF unit array.
Li discloses:
comprising a PUF unit array formed by n x m PUF units distributed in n rows and m columns the basic unit array is used for generating binary output signal; wherein n and m are integers greater than or equal to 1, (On page 4, Li discloses “A 32 by 128 array is implemented.” Figure 5a further discloses a PUF array with the n and m integers greater than 1)
One in ordinary skill in the art of cryptography would have been motivated, before the effective filing date of the claimed invention to modify Chen’s approach by utilizing Li’s approach of using a PUF array as the motivation would be the SRAM-style peripheral are integrated to allow for parallel and high-speed readout rather than using a linear cascade which allows for higher throughput (See Li, Page 4).
Claims 2-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 117544320), hereinafter referred to as Chen, in view of Li et al. (NPL: A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization), hereinafter referred to as Li, in further view of Goel et al. (US 6794906), hereinafter referred to as Goel.
Regarding Claim 2, the combination of Chen and Li disclose:
The self-filtering monostable PUF circuit based on the hysteresis effect according to Claim 1 (On page 2, Chen discloses “The embodiment of the invention claims a physical unclonable function circuit based on Schmidt inverter” and further discloses on page 12 “the monostable structure and the cross coupling structure to design the stable conversion structure,”), characterized in that the filter unit comprises a first inverter, a second inverter, a third inverter, and a Schmitt trigger (On page 5, Chen discloses “a first gating MOS transistor X1, a second gating MOS transistor X2 and a third gating MOS transistor X3;”), wherein each of the first inverter, the second inverter and the third inverter has an input terminal and an output terminal (On page 8, Chen discloses “are connected at the same time, and the connection point is used as the input end of the Schmidt trigger type inverter S…. and the connection point is used as the output end of the Schmidt trigger type inverter S;”); the Schmitt trigger has an input terminal and an output terminal (On page 8, Chen discloses “VIN is the input end of the Schmidt trigger type inverter S, VOUT is the output end of the Schmidt trigger type inverter S,”); the input terminal of the first inverter is connected to the second input terminal of the 2-to-1 data selector, and a connection terminal thereof serves as an input terminal of the filter unit (On page 5, Chen discloses “the first connecting end of the first gating MOS tube X1 is used as the input end of the stable conversion unit P, the second connecting end of the first gating MOS tube X1 is connected with the input end of one Schmidt trigger type inverter S at the same time, the first connection end of the second gating MOS tube X2 is connected with the first connection end of the third gating MOS tube X3”); the input terminal of the filter unit is configured to receive output responses generated by the PUF units (On page 12, Chen discloses “the stable conversion unit is connected end to end, the output end of each stable conversion unit is connected with one corresponding input end of the multi-path selector;”); the output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the third inverter (On page 10, Chen discloses “four Schmitt trigger type inverters included in the four-stage inverter cascade unit structure are connected end to end in turn,”), the output terminal of the third inverter is connected to the first input terminal of the 2-to-1 data selector (On page 3, Chen discloses “the output end of one Schmidt trigger type inverter in the steady state conversion unit is connected with the input end of the other Schmidt trigger type inverter, and the connecting point is connected with the second connecting end of the second gating MOS tube;”); the output terminal of the Schmitt trigger serves as an output terminal of the filter unit and the output terminal of the filter unit is configured to output a filter result (On page 5, Chen discloses “the second connection end of the third gating MOS tube X3 is connected with the output end of the other Schmidt trigger type inverter S, and the connection point is used as the output end of the steady state conversion unit P.”); the timing control terminal of the 2-to-1 data selector serves as a timing control terminal of the filter unit to receive a high-level or low-level timing control signal (On page 6, Chen discloses “The strobe signal shift register is responsible for updating the strobe signal of each state conversion and outputting it to the PUF unit array, so the clock signal is introduced to control the conversion between states more orderly.”).
However, Chen does not explicitly disclose the use of a 2-to-1 selector.
Goel discloses:
a 2-to-1 data selector (In Col 1, Lines 55-57, Goel discloses “in which a single transmission gate enables an active input from the previous stage to its output”) the 2-to-1 data selector has two input terminals respectively referred as a first input terminal and a second input terminal, an output terminal and a timing control terminal (In Col 1, Lines 59-65, Goel discloses “The TGM is an arrangement of transmission gates in row and column form with the gates of all transmission gates in the same column connected together to a single output from a first decoder from the previous stage, while the inputs of all transmission gates in the same row are connected together to a single output of the second decode”) the output terminal of the 2-to-1 data selector is connected to the input terminal of the Schmitt trigger (In Col 1, Lines 55-57, Goel discloses “Transmission Gate Matrix (TGM) in which a single transmission gate enables an active input from the previous stage to its output, thereby resulting in reduced area requirements when implemented as an integrated circuit”)
One in ordinary skill in the art of cryptography would have been motivated, before the effective filing date of the claimed invention to modify Chen’s approach by utilizing Goel’s approach of using a 2-to-1 selector as the motivation would be rather than utilizing multiple transistors to create a selector, implementing a 2-to-1 selector would reduce the area while generating a predictable result (See Goel, Col 1).
Regarding Claim 3, the combination of Chen, Li, and Goel disclose:
The self-filtering monostable PUF circuit based on the hysteresis effect according to Claim 2 (On page 2, Chen discloses “The embodiment of the invention claims a physical unclonable function circuit based on Schmidt inverter” and further discloses on page 12 “the monostable structure and the cross coupling structure to design the stable conversion structure,”), characterized in that further comprising an input register (On page 7, Chen discloses “SR_In is the data input signal of the gating signal configuration shift register,”), a timing controller, a row decoder, a column decoder and a transmission gate array, wherein the input register is configured to pre-store required row address data and column address data (On page 7, Chen discloses “SR_In is the data input signal of the gating signal configuration shift register,”); the timing controller has an output terminal and is configured to generate a high-level timing control signal or a low-level timing control signal and output the signal via the output terminal thereof (On page 7, Chen discloses “set is the synchronous set signal of the gating signal configuration shift register”); the output terminal of the timing controller is connected to the timing control terminal of the filter unit (On page 12, Chen discloses “the control input end of each stable conversion unit is connected with the corresponding control output end in the shift register.”); each of the PUF units has an output terminal for outputting the output response thereof (On page 5, Chen discloses “the 256 stable conversion units P are cascaded and the cascade point is taken as the output, the gating signals of the front and back units are configured, the same unit is time-sharing multiplexed to generate 1bit random output;”);
However, Chen does not explicitly disclose a row and column decoder.
Goel discloses:
the row decoder has an input terminal and n-bit output terminals; the input terminal of the row decoder is connected to the input register to receive the row address data; the row decoder is configured to convert the row address data received by the input terminal thereof into n-bit row selection signals and output the n-bit row selection signals via the n-bit output terminals thereof in a one-to-one correspondence, wherein only one bit in the n-bit row selection signals is a high-level signal, and the other are low- level signals (In Col 3, Lines 5-9, Goel discloses “one output line of the horizontal decoder will go low and others will be high and one output line of the vertical decoder will be high while the others will be low.” Further Figure 1 and 2 disclose active low outputs and active high outputs); the column decoder has an input terminal and m-bit output terminals, the input terminal of the column decoder is connected to the input register, the column address data is input in the input terminal of the column decoder, and the column decoder is configured to convert the column address data received by the input terminal thereof into m-bit column selection signals and output the m-bit column selection signals via the m-bit output terminals thereof in a one-to- one correspondence, wherein only one bit in the m-bit column selection signals is a high-level signal, and the other are low-level signals (In Col 3, Lines 5-9, Goel discloses “one output line of the horizontal decoder will go low and others will be high and one output line of the vertical decoder will be high while the others will be low.” Wherein Goel discloses the second set of decoders following the same polarity choices); the transmission gate array is formed by (n+1) x m transmission gates distributed in n+ rows and in columns, each of the transmission gates has an input terminal, an output terminal and a control terminal (In Col 1, Lines 59-65, Goel discloses “The TGM is an arrangement of transmission gates in row and column form with the gates of all transmission gates in the same column connected together to a single output from a first decoder from the previous stage, while the inputs of all transmission gates in the same row are connected together to a single output of the second decoder from the previous stage.”), and under the control of a control signal received by the control terminal of the transmission gate, the input terminal and output terminal thereof are turned on or off (In Col 1, Lines 55-57, Goel discloses “Transmission Gate Matrix (TGM) in which a single transmission gate enables an active input from the previous stage to its output” and further discloses “Pass gates 305, 309, and 313 are OFF so only gate 301 (which is at the cross-point of the H0 and V0) will pass logic high to its output.”); the kth bit output terminal of the row decoder is connected to the control terminal of in transmission gates located in row k, k=1, 2, ..., n (In the Summary of the Invention, Goel discloses “the gates of all transmission gates in the same column connected together to a single output from a first decoder from the previous stage” and further discloses in Col 3, Lines 9-12 “The gates of the transmission gate in each column of the matrix (301) to (304), (305) to (308), (309) to (312), and (313) to (316) are connected with the output signals and the compliment of the output signals from the horizontal decoder.”), the j th bit output terminal of the column decoder is connected to the control terminal of the transmission gate located in row n+1 and column j, j=1, 2, ..., in (In the Summary of the Invention, Goel discloses “The gates of the transmission gate in each column of the matrix (301) to (304), (305) to (308), (309) to (312), and (313) to (316) are connected with the output signals and the compliment of the output signals from the horizontal decoder.” and further discloses in Col 3, Lines 15-17 “the inputs of transmission gates (301), (305), (309), and (313) are joined and connected to the first output V0 of the vertical decoder”), the output terminal of the PUF unit located in row k and column j is connected to the input terminal of the transmission gate located in row k and column j, the output terminals of the n transmission gates located in rows 1 to n and column j are all connected to the input terminal of the transmission gate located in row n+1 and column j, and the output terminals of in transmission gates located in row n+ are all connected to the input terminal of the filter unit (In Col 4, Lines 30-34, Goel discloses “In the final stage, the outputs from the 6x64 TGM (9.6) and 4x16 TGM (9.5) are connected to a 10x1024 TGM (9.8) with associated charge matrix/discharge matrix (not shown).” Which discloses a cascade of transmission gate stages connected and outputting a single output
One in ordinary skill in the art of cryptography would have been motivated, before the effective filing date of the claimed invention to modify Chen’s approach by utilizing Goel’s approach of using a 2-to-1 selector and row and column decoders as the motivation would be rather than utilizing multiple transistors to create a selector, implementing a 2-to-1 selector as well as the decoders would reduce the area of a silicon while generating a predictable result (See Goel, Col 1).
Regarding Claim 4, the combination of Chen, Li, and Goel disclose:
The self-filtering monostable PUF circuit based on the hysteresis effect according to Claim 3 (On page 2, Chen discloses “The embodiment of the invention claims a physical unclonable function circuit based on Schmidt inverter” and further discloses on page 12 “the monostable structure and the cross coupling structure to design the stable conversion structure,”), the drain of the third MOS is connected to the drain of the fourth MOS, and a connection terminal thereof is the output terminal of the PUF unit (On page 5, Chen discloses “the 256 stable conversion units P are cascaded and the cascade point is taken as the output, the gating signals of the front and back units are configured, the same unit is time-sharing multiplexed to generate 1bit random output;”);
However, Chen does not explicitly disclose the four transistor characterization.
Li discloses:
characterized in that each of the PUF units comprises a first MOS, a second MOS, a third MOS and a fourth MOS (On page 2, Li discloses “the proposed PUF cell employs a 4-stage subthreshold inverter chain”), wherein the first MOS and the third MOS are PMOSs; the second MOS and the fourth MOS are NMOSs (On page 4, Li discloses in Figure 8(b) each stage is a CMOS inverter (PMOS + NMOS)); the source of the first MOS and the source of the third MOS are connected to a power voltage (VDD) (On page 4, Li discloses in Figure 8(b) a Volage supply feeding the PMOS); the drain and gate of the first MOS, the drain and gate of the second MOS, the gate of the third MOS and the gate of the fourth MOS are connected (On page 4, Li discloses in Figure 8(b) the four transistors connected); the source of the second MOS and the source of the fourth MOS are grounded (On page 4, Li discloses on Figure 8(b) the NMOS sources connected to ground); the first MOS and the second MOS constitute a first-stage inverter, and the third MOS and the fourth MOS constitute a second-stage inverter (On page 4, Li discloses on Figure 8 a two sage CMOS inverter chain).
One in ordinary skill in the art of cryptography would have been motivated, before the effective filing date of the claimed invention to modify Chen’s approach by utilizing Li’s approach of using a inverter-chain cell as it is built from two CMOS transistors which results in the same cascading technology but within a smaller footprint and the motivation would be lower power and a smaller footprint as compared to using multiple transistors to generate the same result (See Li, Page 8, Section F)
Regarding Claim 6, the combination of Chen, Li, and Goel disclose:
The self-filtering monostable PUF circuit based on the hysteresis effect according to Claim 3, characterized in that the Schmitt trigger comprises a ninth MOS, a tenth MOS, an eleventh MOS, a twelfth MOS, a thirteenth MOS and a fourteenth MOS (On page 8, Chen discloses “the Schmidt trigger inverter S comprises a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MP3, a fourth MOS transistor MN2, a fifth MOS transistor MN1 and a sixth MOS transistor MN3”), wherein the ninth MOS, the tenth MOS and the thirteenth MOS are PMOSs; the eleventh MOS, the twelfth MOS and the fourteenth MOS are NMOSs (On page 8, Chen discloses “the first MOS tube MP1, the second MOS tube MP2 and the third MOS tube MP3 are all P-type MOS tubes; wherein the fourth MOS transistor MN2, the fifth MOS transistor MN1 and the sixth MOS transistor MN3 are all N-type MOS transistors.”); the source of the ninth MOS is connected to the power voltage (VDD) (On page 8, Chen discloses “the source electrode of the first MOS tube MP1 and the drain electrode of the sixth MOS tube MN3 are connected with the power supply voltage;”); the gate of the ninth MOS, the gate of the tenth MOS, the gate of the eleventh MOS and the gate of the twelfth MOS are connected, and a connection terminal thereof is the input terminal of the Schmitt trigger (On page 8, Chen discloses “the gate of the first MOS tube MP1, the gate of the second MOS tube MP2, the gate of the fourth MOS tube MN2 and the gate of the fifth MOS tube MN1 are connected at the same time, and the connection point is used as the input end of the Schmidt trigger”); the drain of the ninth MOS, the source of the tenth MOS and the source of the thirteenth MOS are connected; the drain of the thirteenth MOS is grounded (On page 8, Chen discloses “the drain electrode of the first MOS tube MP1 is connected with the source electrode of the second MOS tube MP2 and the source electrode of the third MOS tube MP3; the drain electrode of the second MOS tube MP2 is connected with the drain electrode of the fifth MOS tube MN1,”); the drain of the tenth MOS, the drain of the eleventh MOS, the gate of the thirteenth MOS and the gate of the fourteenth MOS are connected, and a connection terminal thereof is the output terminal of the Schmitt trigger (On page 8, Chen discloses “the drain electrode of the second MOS tube MP2 is connected with the drain electrode of the fifth MOS tube MN1, the gate electrode of the third MOS tube MP3 and the gate electrode of the sixth MOS tube MN3, and the connection point is used as the output end of the Schmidt trigger type inverter S;”); the source of the eleventh MOS, the drain of the twelfth MOS and the source of the fourteenth MOS are connected (On page 8, Chen discloses “the source electrode of the fifth MOS tube MN1 is connected with the drain electrode of the fourth MOS tube MN2”); the source of the twelfth MOS is grounded (On page 8, Chen discloses “the source electrode of the fourth MOS tube MN2 and the drain electrode of the third MOS tube MP3 are grounded.”); the drain of the fourteenth MOS is connected to the power voltage (VDD) (On page 8, Chen discloses “the source electrode of the first MOS tube MP1 and the drain electrode of the sixth MOS tube MN3 are connected with the power supply voltage;”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 117544320), hereinafter referred to as Chen, in view of Li et al. (NPL: A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization), hereinafter referred to as Li, in further view of Goel et al. (US 6794906), hereinafter referred to as Goel, in further view of Hirai, Jun (US 5332916), hereinafter referred to as Hirai.
Regarding Claim 5, the combination of Chen, Li, and Goel disclose the limitations of Claim 3.
However, Chen does not explicitly disclose a conventional 4 transistor CMOS transmission gate.
Hirai discloses:
characterized in that each of the transmission gates comprises a fifth MOS, a sixth MOS, a seventh MOS and an eighth MOS (In Col 1, Lines 32-35, Hirai discloses “FIG. 7 shows a fundamental constitution of a conventional transmission gate, wherein 1 is an NMOS transistor and 2 is a PMOS transistor. These transistors connected in parallel perform a switching function… its inverted signal is obtained by supplying the control signal via an inverter as illustrated in the drawing.” Total of Four MOS), wherein the fifth MOS and the seventh MOS are PMOSs; the sixth MOS and the eighth MOS are NMOSs (See Figure 7 representing a PMOS and NMOS transistor with a inverter which consists of another PMOS and NMOS); the source of the fifth MOS is connected to the source of the sixth MOS, and a connection terminal thereof is the input terminal of the transmission gate (See Figure 7 representing the PMOS and NMOS transistors connected in parallel between the input and output); the drain of the fifth MOS is connected to the drain of the sixth MOS and a connection terminal thereof is the output terminal of the transmission gate (See Figure 7 representing the inverter and parallel transistors providing an output f.); the gate of the fifth MOS, the drain of the seventh MOS and the drain of the eighth MOS are connected (In Col 1, Lines 50-52, Hirai discloses “its inverted signal is obtained by supplying the control signal via an inverter as illustrated in the drawing.” See Figure 7); the gate of the sixth MOS, the gate of the seventh MOS and the gate of the eighth MOS are connected, and a connection terminal thereof is the control terminal of the transmission gate (In Col 1, Lines 40-42, Hirai discloses “When the gate receives a control signal C and its inverted signal *C, the both transistors 1 and 2 are rendered to an "ON" (conductive) state.”); the source of the eighth MOS is grounded; the source of the seventh MOS is connected to the power voltage (VDD) (See Figure 7 displaying Vcc and Vee wherein the examiner interprets as power voltage and ground)
One in ordinary skill in the art of cryptography would have been motivated, before the effective filing date of the claimed invention to modify Chen’s approach by utilizing Hirai’s approach of using his CMOS configuration as the motivation would be using an NMOS transistor and PMOS transistor, they exhibit a resistance value of opposing characteristics with respect to the voltage signal thereby linearity effected by the composite resistance value of these transistors is improved in comparison with that by the single element of a transistor (See Hirai, Col 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhao et al. (CN 112687307) discloses a physical unclonable function circuit based on cross-coupling Schmidt trigger type inverters.
Zhao et al. (CN 113946882) discloses a physical non-cloneable function circuit base don a Schmitt trigger consisting of a line decoder, basic unit array, power supply and multiple additional triggers in series.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHADI H KOBROSLI whose telephone number is (571)272-1952. The examiner can normally be reached M-F 9am-5pm ET.
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/SHADI H KOBROSLI/Examiner, Art Unit 2492 /RUPAL DHARIA/Supervisory Patent Examiner, Art Unit 2492
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