DETAILED ACTION
This office action is responsive to communication filed on September 18, 2026.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The double patenting rejection of claim 1 is hereby removed in view of the amendment filed September 18, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 7 recites “the first semiconductor includes a third photoelectric converter that converts light into charge and is arranged between the first photoelectric converter and the second photoelectric converter in the row direction”. Figure 3 shows two photoelectric converters (PD) arranged in the row direction. However, the Examiner has been unable to find support for a third photoelectric converter arranged between the first photoelectric converter and the second photoelectric converter in the row direction, in combination with the other elements recited in claim 7 and parent claims 6, 5 and 1, in figure 3 or elsewhere in the original disclosure. As such, claim 7 contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 8 depends from claim 7 and thus contains the same new matter as claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wakabayashi (US 2015/0163403) in view of Manabe et al. (US 2018/0302579).
Consider claim 1, Wakabayashi teaches:
An imaging element (figures 1 and 11) comprising:
a first semiconductor (first chip, 20, paragraphs 0072 and 0159) including:
a first photoelectric converter (i.e. the photodiode (41) of the left pixel in figure 11) that photoelectrically converts light to generate electric charge (paragraph 0083);
a second photoelectric converter (i.e. the photodiode (41) of the right pixel in figure 11) that photoelectrically converts light to generate electric charge (paragraph 0083) and is arranged side-by-side with the first photoelectric converter (41) in a row direction (see figure 11);
a first gate of a first transfer transistor (“a gate electrode of the transfer transistor 42” paragraph 0085) for transferring charge converted by the first photoelectric converter (41) to a first floating diffusion (floating diffusion, 46, figure 11, paragraphs 0086 and 0087); and
a second semiconductor (second chip, 30) stacked with the first semiconductor (“a first chip (semiconductor substrate) 20 and a second chip 30 having a structure such that the first chip 20 serving as an upper-side chip and the second chip 30 serving as a lower-side chip are layered” paragraph 0072, see figure 1);
a third gate of a first selection transistor (i.e. the selection transistor (45) of the left pixel in figure 11, paragraph 0083) electrically connected to a first amplification transistor (i.e. the amplification transistor (44) of the left pixel in figure 11, paragraph 0083) for outputting a first signal based on the charge transferred to the first floating diffusion (44, see figure 11, paragraph 0089);
a fourth gate of a second selection transistor (i.e. the selection transistor (45) of the right pixel in figure 11, paragraph 0083) electrically connected to a second amplification transistor (i.e. the amplification transistor (44) of the right pixel in figure 11, paragraph 0083) for outputting a second signal based on the charge transferred to the second floating diffusion (44, see figure 11, paragraph 0089).
a fifth gate of a third selection transistor (i.e. the selection transistor (47) of the left pixel in figure 11, paragraph 0160) for electrically connecting the first selection transistor (45) and a first signal line (see figure 11, paragraphs 0160 and 0161); and
a sixth gate of a fourth selection transistor (i.e. the selection transistor (47) of the right pixel in figure 11, paragraph 0160) for electrically connecting the second selection transistor (45) and the first signal line (see figure 11, paragraphs 0160 and 0161).
Wakabayashi teaches that the row selection unit (25) and column selection unit (27) may be provided on the second chip (“It should be noted while FIG. 11 exemplary illustrates the case of adopting a configuration in which the row selection unit 25 and the column selection unit 27 are provided on the first chip 20 side, it is possible to adopt a configuration in which they are provided as peripheral circuitry (HSEL, VSEL) on the second chip 30 side, as illustrated in the exemplary layout of FIG. 14.” paragraph 0175). However, Wakabayashi does not explicitly teach that the first through fourth selection transistors are included on the second chip.
Manabe et al. similarly teaches an imaging element (figure 1) including an array of pixels (image sensor pixel circuits, 132, paragraph 0015), a first semiconductor (first semiconductor wafer, 110, paragraph 0018) and a second semiconductor (second semiconductor wafer, 112, paragraph 0018), wherein the pixels include selection transistors (row selection transistor, 228, figure 2) connected to a first signal line (output bitline, 230, figure 2, paragraph 0023).
However, Manabe et al. additionally teaches that the selection transistors (228) are included on the second semiconductor (“Continuing with the example depicted in FIG. 2, a row select transistor 228 disposed in the second semiconductor wafer 212, and is coupled to the amplifier transistor 222 in the first semiconductor wafer 210 to selectively couple, in response to a row select signal RS, the output signal of the pixel circuit 232 from amplifier transistor 222 through a via 236 to an output bitline 230 in the second semiconductor wafer 212.” paragraph 0023).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through fourth selection transistors taught by Wakabayashi be included in the second semiconductor as taught by Manabe et al. for the benefit of enabling HDR imaging with high resolution and low noise (see paragraphs 0011, 0003 and the title of Manable et al.).
Consider claim 2, and as applied to claim 1 above, Wakabayashi further teaches that the second semiconductor (30) includes a first converter for converting the first signal output to the first signal line into a digital signal (See the “pixel AD unit” on the second semiconductor (30) in figures 14 and 16, paragraphs 0141, 0145, 0147 and 0174.).
Consider claim 3, and as applied to claim 2 above, Wakabayashi further teaches that the first converter converts the second signal output to the first signal line into a digital signal (“ The signal processing unit includes an AD (analog-digital) converter which digitizes an analog pixel signal read from each pixel of the pixel array unit to the signal line” paragraph 0057).
Consider claim 4, and as applied to claim 2 above, Wakabayashi further teaches that the second semiconductor includes (30) a first current source (current source, 35, figure 12) that supplies current to the first signal line (see figures 11 and 12, paragraph 0095).
Consider claim 5, and as applied to claim 1 above, Wakabayashi further teaches that the third gate (45) is electrically connected to a first control line through which a first control signal (VSEL) for controlling the first selection transistor (45) is output (see figure 11, paragraph 0160), and the fourth gate (45) is electrically connected to a second control line through which a second control signal (VSEL) for controlling the second selection transistor (45) is output (see figure 11, paragraph 0160).
Consider claim 6, and as applied to claim 5 above, Wakabayashi further teaches that the fifth gate (47) is electrically connected to a third control line through which a third control signal (HSEL) for controlling the third selection transistor (47) is output (see figure 11, paragraph 0160), and the sixth gate (47) is electrically connected to a fourth control line through which a fourth control signal (HSEL) for controlling the fourth selection transistor (47) is output (see figure 11, paragraph 0160).
Consider claim 13, and as applied to claim 1 above, the combination of Wakabayashi and Manabe et al. does not explicitly teach a first filter having a first spectral characteristic; and a second filter having a second spectral characteristic different from the first spectral characteristic, wherein the first photoelectric converter converts light transmitted through the first filter into charge, and the second photoelectric converter converts light transmitted through the second filter into charge.
However, Official Notice (MPEP § 2144.03) is taken that both the concepts and advantages of transmitting light to photoelectric converters through color filters are well known and expected in the art. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include first and second color filters for transmitting light respectively to the first and second photoelectric converters taught the combination of Wakabayashi and Manabe et al. for the benefit enabling a color image to be captured.
Consider claim 14, Wakabayashi teaches an imaging apparatus (imaging device, figure 19, paragraphs 0208-0213) comprising the imaging element according to claim 1 (imaging element, 102, figure 19, see claim 1 rationale).
Consider claim 15, and as applied to claim 14 above, Wakabayashi further teaches a lens included in an optical system (“an optical system including a lens group 101”, figure 19, paragraph 0209) that emits light to the imaging element (102, see paragraph 0210).
Wakabayashi does not explicitly teach a lens moving portion that moves the lens.
However, Official Notice (MPEP § 2144.03) is taken that both the concepts and advantages of moving a lens with a lens moving portion are well known and expected in the art. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to move the lens taught by the combination of Wakabayashi and Manabe et al. via a lens moving portion for the benefit of enabling a focused image to be captured.
Consider claim 16, and as applied to claim 15 above, Wakabayashi further teaches the optical system (“an optical system including a lens group 101”, figure 19, paragraph 0209).
Consider claim 17, and as applied to claim 14 above, Wakabayashi further teaches a control portion (operation system, 107, figure 19) electrically connected to the imaging element (102, see figure 19) and configured to generate image data (i.e. by issuing commands to the imaging device (100), paragraph 0212).
Allowable Subject Matter
Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 9, the prior art of record does not teach nor reasonably suggest that the first semiconductor includes a third photoelectric converter that converts light into charge and is arranged side-by-side with the first photoelectric converter in a column direction, and a seventh gate of a third transfer transistor for transferring charge converted by the third photoelectric converter to a third floating diffusion portion, the second semiconductor includes an eighth gate of a fifth selection transistor electrically connected to a third amplification transistor for outputting a third signal based on the charge transferred to the third floating diffusion, and the third gate and the eighth gate are electrically connected to the first control line through which the first control signal for controlling the first selection transistor and the fifth selection transistor is output, in combination with the other elements recited in parent claims 1, 5 and 6.
Claims 10-12 contain allowable subject matter as depending from claim 9.
Prior Art
Consider claim 7, the prior art of record does not teach nor reasonably suggest that the first semiconductor includes a third photoelectric converter that converts light into charge and is arranged between the first photoelectric converter and the second photoelectric converter in the row direction, and a seventh gate of a third transfer transistor for transferring charge converted by the third photoelectric converter to a third floating diffusion, and the second semiconductor includes an eighth gate of a fifth selection transistor electrically connected to a third amplification transistor for outputting a third signal based on the charge transferred to the third floating diffusion, the eighth gate being electrically connected to a fifth control line through which a fifth control signal for controlling the fifth selection transistor is output, in combination with the other elements recited in parent claims 6, 5 and 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakamura (US 2019/0149758) teaches “In another illustrative example, pixel array 32 may be formed using two substrates, with at least the photodiodes in a first substrate and at least the row select transistor in a second substrate.” paragraph 0044.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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