DETAILED ACTION
This office action is responsive to communication filed on September 18, 2026.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
The Double Patenting rejection of claim 1 is hereby removed in view of Applicant’s response.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed April 23, 2026 was received and has been considered by the Examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 12, 16, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsukuda et al. (US 2018/0376093).
Consider claim 1, Tsukuda et al. teaches:
An imaging element (see figure 2) comprising:
a first substrate (pixel substrate, 10, paragraph 0019) that includes:
a first pixel (There are a plurality of pixel blocks (11) of NxM pixels formed in the pixel substrate (10), paragraph 0021, figure 1. The Examiner interprets a bottom right pixel of the top left pixel block of figure 1 to be the first pixel. The pixel structure is shown in figure 2.) including a first photoelectric converter that converts light into an electric charge (a photoelectric conversion element (PD, 11), paragraphs 0023 and 0024, see figure 2) and that outputs, to a first signal line (Each pixel block (11) is associated with a corresponding read circuit (33) to which it is connected via a corresponding vertical signal line (VSL, 23) to which a signal based on the electric charge generated by a photoelectric conversion unit (11) is output paragraphs 0021, 0024-0027 and 0029, see figure 2. The Examiner interprets the vertical signal line (23) of the top left pixel block in figure 1 to be the first signal line.), a first signal based on the charge converted by the first photoelectric converter (PD, 11, see paragraphs 0024-0027, figure 2);
a second pixel (The Examiner interprets a bottom left pixel of the pixel block (11) to the right of the top left pixel block in figure 1 to be the second pixel.) including a second photoelectric converter (11, figure 2) that converts light into an electric charge (see paragraphs 0023 and 0024), is arranged alongside the first photoelectric converter (11) in a first direction (i.e. the row direction in figure 1), and outputs, to a second signal line (i.e. the signal line (23, figure 2) of the pixel block (11) to the right of the top left pixel block in figure 1), a second signal based on the charge converted by the second photoelectric converter (see paragraphs 0024-0027, figure 2); and
a third pixel (The Examiner interprets a top right pixel of the pixel block (11) directly below the top left pixel block in figure 1 to be the third pixel.) including a third photoelectric converter (11, see figure 2) that converts light into an electric charge (see paragraphs 0023 and 0024), is arranged alongside the first photoelectric converter (PD, 11) in a second direction (i.e. column direction) intersecting the first direction (i.e. row direction, see figure 1), and outputs, to a third signal line (i.e. the signal line (23, figure 2) of the pixel block (11) directly below the top left pixel block (11) in figure 1), a third signal based on the charge converted by the third photoelectric converter (see paragraphs 0024-0027, figure 2); and
a second substrate (logic substrate, 30, paragraph 0019) that is stacked together with the first substrate (10, see figure 2), the second substrate (30) including:
a first supply unit (e.g. a clamp circuit (31, figure 2) of the upper left pixel block in figure 1) that supplies a first voltage to the first signal line (As shown in figure 1, the pixel blocks (11) and accompanying read circuits (33) are arranged two dimensionally. As such, the plurality of supply units (31) associated with the pixel blocks (11) and read circuits (33, see figure 2) are also arranged two dimensionally (i.e. in both row and column directions). Paragraph 0030 of Tsukuda et al. teaches, “The transistor 31 is a source follower of the logic substrate 30 and operates as a clamp circuit which prevents the VSL 23 from having too low a potential.” As detailed in paragraph 0022 of Tsukuda et al., “FIG. 2 is a circuit diagram showing a first configuration example of the solid-state image pickup element. In the pixel substrate 10 in the figure, a circuit configuration of only one pixel is shown and, in a logic substrate 30, a circuit configuration corresponding to the pixel block 11 on the pixel substrate 10 is shown.” Based upon this recitation, it is clear that a single supply unit (31) of figure 2 is provided for each pixel block, and thus a first supply unit is associated with the first signal line.);
a second supply unit (e.g. a clamp circuit (31, figure 2) of the pixel block (11) to the right of the upper left pixel block in figure 1) that supplies a second voltage to the second signal line (As shown in figure 1, the pixel blocks (11) and accompanying read circuits (33) are arranged two dimensionally. As such, the plurality of supply units (31) associated with the pixel blocks (11) and read circuits (33, see figure 2) are also arranged two dimensionally (i.e. in both row and column directions). Paragraph 0030 of Tsukuda et al. teaches, “The transistor 31 is a source follower of the logic substrate 30 and operates as a clamp circuit which prevents the VSL 23 from having too low a potential.” As detailed in paragraph 0022 of Tsukuda et al., “FIG. 2 is a circuit diagram showing a first configuration example of the solid-state image pickup element. In the pixel substrate 10 in the figure, a circuit configuration of only one pixel is shown and, in a logic substrate 30, a circuit configuration corresponding to the pixel block 11 on the pixel substrate 10 is shown.” Based upon this recitation, it is clear that a single supply unit (31) of figure 2 is provided for each pixel block, and thus a second supply unit is associated with the second signal line.);
a third supply unit (e.g. a clamp circuit (31, figure 2) of the pixel block (11) directly beneath the upper left pixel block in figure 1) that supplies a third voltage to the third signal line (As shown in figure 1, the pixel blocks (11) and accompanying read circuits (33) are arranged two dimensionally. As such, the plurality of supply units (31) associated with the pixel blocks (11) and read circuits (33, see figure 2) are also arranged two dimensionally (i.e. in both row and column directions). Paragraph 0030 of Tsukuda et al. teaches, “The transistor 31 is a source follower of the logic substrate 30 and operates as a clamp circuit which prevents the VSL 23 from having too low a potential.” As detailed in paragraph 0022 of Tsukuda et al., “FIG. 2 is a circuit diagram showing a first configuration example of the solid-state image pickup element. In the pixel substrate 10 in the figure, a circuit configuration of only one pixel is shown and, in a logic substrate 30, a circuit configuration corresponding to the pixel block 11 on the pixel substrate 10 is shown.” Based upon this recitation, it is clear that a single supply unit (31) of figure 2 is provided for each pixel block, and thus a third supply unit is associated with the third signal line.);
a first current source (e.g. a VSL driving current power source (32, figure 2) of the upper left pixel block (11) in figure 1) that supplies current, via the first signal line (VSL, 23), to at least one of the first pixel and the first supply unit (see figure 2, paragraph 0029);
a second current source (e.g. a VSL driving current power source (32, figure 2) of the pixel block (11) to the right of the upper left pixel block in figure 1) that supplies current, via the second signal line (VSL, 23), to at least one of the second pixel and the second supply unit (see figure 2, paragraph 0029); and
a third current source (e.g. a VSL driving current power source (32, figure 2) of the pixel block (11) directly below the upper left pixel block in figure 1) that supplies current, via the third signal line (VSL, 23), to at least one of the third pixel and the third supply unit (see figure 2, paragraph 0029).
Consider claim 2, and as applied to claim 1 above, Tsukuda et al. further teaches:
the first pixel (see figure 2) includes a first amplification transistor (AMP transistor, 14) for outputting the first signal (see paragraph 0026);
the second pixel (see figure 2) includes a second amplification transistor (AMP transistor, 14) for outputting the second signal (see paragraph 0026);
the third pixel (see figure 2) includes a third amplification transistor (AMP transistor, 14) for outputting the third signal (see paragraph 0026);
the first supply unit (31) includes a first transistor (transistor, 31) for supplying the first voltage (see figure 2, paragraph 0030);
the second supply unit (31) includes a second transistor (transistor, 31) for supplying the second voltage (see figure 2, paragraph 0030);
the third supply unit (31) includes a third transistor (transistor, 31) for supplying the third voltage (see figure 2, paragraph 0030);
the first current source (32) supplies current, via the first signal line (VSL, 23), to at least one of the first amplification transistor (14) and the first transistor (31, see figure 2);
the second current source (32) supplies current, via the second signal line (VSL, 23), to at least one of the second amplification transistor (14) and the second transistor (31, see figure 2); and
the third current source (32) supplies current, via the third signal line (VSL, 23), to at least one of the third amplification transistor (14) and the third transistor (31, see figure 2).
Consider claim 3, and as applied to claim 2 above, Tsukuda et al. further teaches that the first amplification transistor (14), the second amplification transistor (14), the third amplification transistor (14), the first transistor (31), the second transistor (31), and the third transistor (31) are electrically connected to a wiring to which a predetermined voltage (VDD) is supplied (see figure 2).
Consider claim 4, and as applied to claim 3 above, Tsukuda et al. further teaches a wiring layer (The wiring layer includes at least he Cu-Cu bonding portion (20) in figure 2, paragraphs 0019 and 0032.) including the wiring (see figure 2), wherein the wiring layer (20) is disposed between the first substrate (10) and the second substrate (30) in a stacking direction in which the first substrate (10) and the second substrate (30) are stacked (see figure 2).
Consider claim 6, and as applied to claim 4 above, Tsukuda et al. further teaches that the wiring layer includes the first signal line (VSL, 23, see figure 2), the second signal line (VSL, 23, see figure 2), and the third signal line (VSL, 23, see figure 2).
Consider claim 12, and as applied to claim 1 above, Tsukuda et al. further teaches that the second substrate (30) includes: a first supply control unit (i.e. the transistor connected to the top of transistor 31 in figure 2) that outputs a first supply control signal for controlling operation of the first supply unit (31, see figure 2); a second supply control unit (i.e. the transistor connected to the top of transistor 31 in figure 2) that outputs a second supply control signal for controlling operation of the second supply unit (31, see figure 2); and a third supply control unit (i.e. the transistor connected to the top of transistor 31 in figure 2) that outputs a third supply control signal for controlling operation of the third supply unit (31, see figure 2).
Consider claim 16, and as applied to claim 1 above, Tsukuda et al. further teaches that the second substrate (30) includes: a first processing unit (read circuit, 33, figure 2) that performs signal processing on the first signal output to the first signal line (VSL, 23, see figure 2, paragraph 0031); a second processing unit (33) that performs signal processing on the second signal output to the second signal line (VSL, 23, see figure 2, paragraph 0031); and a third processing unit (33) that performs signal processing on the third signal output to the third signal line (VSL, 23, see figure 2, paragraph 0031).
Consider claim 17, and as applied to claim 16 above, Tsukuda et al. further teaches that the first processing unit (33) includes a first conversion unit that converts the first signal output to the first signal line into a digital signal (“The read circuit 33 is arranged immediately below a Cu—Cu bonding portion 20-4 and is connected to the VSL 23, reads an electric signal also as a pixel signal from the pixel substrate 10 to conduct AD conversion thereof, and outputs a result thereof to a subsequent stage.” paragraph 0031); the second processing unit (33) includes a second conversion unit that converts the second signal output to the second signal line into a digital signal (“The read circuit 33 is arranged immediately below a Cu—Cu bonding portion 20-4 and is connected to the VSL 23, reads an electric signal also as a pixel signal from the pixel substrate 10 to conduct AD conversion thereof, and outputs a result thereof to a subsequent stage.” paragraph 0031); and the third processing unit (33) includes a third conversion unit that converts the third signal output to the third signal line into a digital signal (“The read circuit 33 is arranged immediately below a Cu—Cu bonding portion 20-4 and is connected to the VSL 23, reads an electric signal also as a pixel signal from the pixel substrate 10 to conduct AD conversion thereof, and outputs a result thereof to a subsequent stage.” paragraph 0031).
Consider claim 20, Tsukuda et al. teaches an imaging apparatus comprising the imaging element according to claim 1 (“a digital camera, a portable equipment with a camera function, and the like”, paragraph 0068, figure 1, see claim 1 rationale).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 7, 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Tsukuda et al. (US 2018/0376093).
Consider claim 5, and as applied to claim 4 above, Tsukuda et al. further teaches that the Cu-Cu bonding portion (20-1) is provided in the first substrate (10), electrically connected to the wiring (see figure 2), and supplied with a power supply voltage (i.e. predetermined voltage, VDD, see figure 2).
Tsukuda et al. alternatively teaches, “The laminated pixel substrate and logic substrate are electrically connected by bringing into contact micro-bumps made of a conductive material which are formed on both the substrates or by forming TCV (silicon through electrode) passing through both the substrates, so that a pixel signal and the like are communicated through the micro-bumps or the TCV.” Paragraph 0004.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the Cu-Cu bonding portions taught by Tsukuda et al. be replaced with silicon through electrode (TCV) structures as taught by Tsukuda et al. as this only involves a simple substitution of one known element for another to obtain predictable results such as enabling communication of electrical signals (Tsukuda et al., paragraph 0004).
Consider claim 7, and as applied to claim 1 above, Tsukuda et al. does not explicitly teach in the embodiment of figure 2, that the second substrate includes: a first pixel control unit that outputs a first pixel control signal for controlling operation of the first pixel; a second pixel control unit that outputs a second pixel control signal for controlling operation of the second pixel; and a third pixel control unit that outputs a third pixel control signal for controlling operation of the third pixel.
However, Tsukuda et al. teaches in the embodiment of figure 3, that the second substrate (30) includes: a first pixel control unit (arbitrary function circuit, 41) that outputs a first pixel control signal for controlling operation of the first pixel (“To the arbitrary function circuit 41, the pixel control wire 42 is connected to, for example, generate a pixel control signal which controls exposure timing of each pixel and supply the same to the gate of the TG transistor 12 via the pixel control wire 42.” paragraph 0044); a second pixel control unit (41) that outputs a second pixel control signal for controlling operation of the second pixel (“To the arbitrary function circuit 41, the pixel control wire 42 is connected to, for example, generate a pixel control signal which controls exposure timing of each pixel and supply the same to the gate of the TG transistor 12 via the pixel control wire 42.” paragraph 0044); and a third pixel control unit (41) that outputs a third pixel control signal for controlling operation of the third pixel (“To the arbitrary function circuit 41, the pixel control wire 42 is connected to, for example, generate a pixel control signal which controls exposure timing of each pixel and supply the same to the gate of the TG transistor 12 via the pixel control wire 42.” paragraph 0044).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the second substrate taught by Tsukuda et al. include first through third pixel control units as taught by Tsukuda et al. for the benefit of saving on area without causing parasitic capacitance (Tsukuda et al., paragraph 0010).
Consider claim 8, and as applied to claim 7 above, Tsukuda et al. further teaches that the first pixel (figure 2) has a first transfer gate of a first transfer transistor (TG transistor, 12) that transfers the charge converted by the first photoelectric converter (11) to a first floating diffusion (floating diffusion, FD, paragraph 0025); the second pixel (figure 2) has a second transfer gate of a second transfer transistor (TG transistor, 12) that transfers the charge converted by the second photoelectric converter (11) to a second floating diffusion (floating diffusion, FD, paragraph 0025); the third pixel (figure 2) has a third transfer gate of a third transfer transistor (TG transistor, 12) that transfers the charge converted by the third photoelectric converter (11) to a third floating diffusion (floating diffusion, FD, paragraph 0025).
The embodiment shown in figure 3 of Tsukuda et al. shows that the first pixel control unit (41) outputs the first pixel control signal to the first transfer gate (12, paragraph 0044); the second pixel control unit (41) outputs the second pixel control signal to the second transfer gate (12, paragraph 0044); and the third pixel control unit (41) outputs the third pixel control signal to the third transfer gate (12, paragraph 0044).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third transfer gates taught by Tsukuda et al. be controlled by first through third pixel control units as taught by Tsukuda et al. for the benefit of saving on area without causing parasitic capacitance (Tsukuda et al., paragraph 0010).
Consider claim 21, and as applied to claim 20 above, Tsukuda et al. does not explicitly teach an optical system that emits light to the imaging element.
However, Official Notice (MPEP § 2144.03) is taken that both the concepts and advantages of including an optical system for emitting light to an imaging element are well known and expected in the art. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the imaging apparatus taught by Tsukuda et al. include an optical system that emits light to the imaging element for the benefit of improving image quality by enabling a focused image to be captured.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsukuda et al. (US 2018/0376093) in view of Sano et al. (US 2019/0364188).
Consider claim 18, and as applied to claim 17 above, Tsukuda et al. does not explicitly teach that the processing units include amplifiers.
Sano et al. similarly teaches an imager (figure 3) with signal processing units (260, 270) for blocks of pixels (see also figures 6 and 7, paragraphs 0070 and 0076).
However, Sano et al. additionally teaches the first processing unit includes a first amplifier (e.g. 262, figure 6) that amplifies the first signal output to the first signal line (see paragraph 0073); the second processing unit includes a second amplifier (e.g. 262, figure 6) that amplifies the second signal output to the second signal line (see paragraph 0073); the third processing unit includes a third amplifier (e.g. 262, figure 6) that amplifies the third signal output to the third signal line (see paragraph 0073); the first conversion unit (e.g. AD converter, 263) converts the first signal amplified by the first amplifier (262) into a digital signal (see paragraph 0074); the second conversion unit (e.g. AD converter, 263) converts the second signal amplified by the second amplifier (262) into a digital signal (see paragraph 0073); and the third conversion unit (e.g. AD converter, 263) converts the third signal amplified by the third amplifier (262) into a digital signal (see paragraph 0073).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have each of the processing units taught by Tsukuda et al. include an amplifier as taught by Sano et al. for the benefit of enabling imaging with a prolonged exposure time (Sano et al., paragraph 0014).
Consider claim 19, and as applied to claim 16 above, Tsukuda et al. does not explicitly teach that the processing units include amplifiers.
Sano et al. similarly teaches an imager (figure 3) with signal processing units (260, 270) for blocks of pixels (see also figures 6 and 7, paragraphs 0070 and 0076).
However, Sano et al. additionally teaches the first processing unit includes a first amplifier (e.g. 262, figure 6) that amplifies the first signal output to the first signal line (see paragraph 0073); the second processing unit includes a second amplifier (e.g. 262, figure 6) that amplifies the second signal output to the second signal line (see paragraph 0073); the third processing unit includes a third amplifier (e.g. 262, figure 6) that amplifies the third signal output to the third signal line (see paragraph 0073).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have each of the processing units taught by Tsukuda et al. include an amplifier as taught by Sano et al. for the benefit of enabling imaging with a prolonged exposure time (Sano et al., paragraph 0014).
Allowable Subject Matter
Claims 9-11, 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 9, the prior art of record does not teach nor reasonably suggest that the second substrate includes a control unit that controls the first pixel control unit and the second pixel control unit such that a timing at which the first pixel control unit outputs the first pixel control signal to the first transfer gate and a timing at which the second pixel control unit outputs the second pixel control signal to the second transfer gate are different timings, in combination with the other elements recited in parent claims 8, 7 and 1.
Claim 10 contains allowable subject matter as depending from claim 9.
Consider claim 11, the prior art of record does not teach nor reasonably suggest that the second substrate includes a control unit that controls the first pixel control unit and the third pixel control unit such that a timing at which the first pixel control unit outputs the first pixel control signal to the first transfer gate and a timing at which the third pixel control unit outputs the third pixel control signal to the third transfer gate are different timings., in combination with the other elements recited in parent claims 8, 7 and 1.
Consider claim 13, the prior art of record does not teach nor reasonably suggest that the second substrate includes a control unit that controls the first supply control unit and the second supply control unit such that a timing at which the first supply control unit outputs the first supply control signal and a timing at which the second supply control unit outputs the second supply control signal are different timings, in combination with the other elements recited in parent claims 1 and 12.
Claim 14 contains allowable subject matter as depending from claim 13.
Consider claim 15, the prior art of record does not teach nor reasonably suggest that the second substrate includes a control unit that controls the first supply control unit and the third supply control unit such that a timing at which the first supply control unit outputs the first supply control signal and a timing at which the third supply control unit outputs the third supply control signal are different timings, in combination with the other elements recited in parent claims 1 and 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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