CTNF 19/027,193 CTNF 80628 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1 and 7-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sato (US2022/0301191) . Regarding claim 1, Sato discloses a device comprising: a first processing pipeline (Fig. 8: image processing apparatus 1) that includes: first processing circuitry configured to perform a first operation on a set of data (Fig. 8: See Shake Remove Unit 33 and Alignment Unit 34 that perform process on Image(n) ); and second processing circuitry (Fig. 8: Motion Compensation Unit 32) coupled to the first processing circuitry (Fig. 8: See connection of unit 33-34 to input of Motion Compensation Unit 32) and configured to perform a second operation on the set of data (Fig. 8: Motion Compensation Unit 32 also perform motion compensation on the input of image(n)); a second processing pipeline (Fig. 8: image processing apparatus 1) that includes: the first processing circuitry (Fig. 8: image processing apparatus 1); third processing circuitry (Fig. 8: processing unit 16) coupled to the first processing circuitry (Fig. 8: See connection of processing unit 16 between Motion unit 32, Alignment Unit 34 and Video Shake Remove Unit 33) and configured to perform a third operation on the set of data; and a memory circuit (Fig. 8: memory 22) coupled between the first processing circuitry (Fig. 8: Units 33-34) and the third processing circuitry (Fig. 8: Processing Unit 16). Regarding claim 7, Sato discloses the device of claim 1, wherein the set of processing circuitry blocks includes at least one of: a lens distortion correction circuit, a noise filter circuit, a multi-scalar circuit, or a direct memory access circuit ([0022-0028]). Regarding claim 8, Sato discloses the device of claim 1, wherein the first processing circuitry is configured to couple to an image capture device to receive the set of data from the image capture device ([0121]). Regarding, 9. Sato discloses a device comprising: first processing circuitry (Fig. 8: Processing Unit 15) that includes: an input; and an output (Fig. 8: See plurality of input and output of Composition Processing Unit 15); second processing circuitry (Fig. 8: Motion Amount Estimate Unit 31) that includes: an input coupled to the output of the first processing circuitry (Fig. 8: See the input of Motion Amount Estimate Unit 31 that coupled to the output of Processing Unit 15); and an output (Fig 8: See put of the Motion Amount Estimation Unit 31 to the Motion Compensation Unit 32); a memory (Fig. 8: 22) that includes: an input coupled to the output of the first processing circuitry (Fig. 8: See plurality of input of memory 22 coupled to the output of Composition Processing Unit 15); and an output (Fig. 8: See output DNR_image(n-1) of memory 22); third processing circuitry (Fig. 8: Alignment Unit 34) that includes: an input coupled to the output of the memory (Fig. 8: See the input of Alignment Unit 34 that coupled to the output of memory 22); and an output (Fig 8: See output Alignment Unit 34 to Compensation Unit 32) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-4, 6 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 12-151-07 AIA 07-97 12-51-07 Claim s 12-20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding independent claim 2, the prior art of Holland (US10474408) discloses a processing pipeline to instruct a first processing block to output first processed image data to the first circuit connection and a second processing block to output second processed image data to a third circuit connection when the first selectable data path is selected. The prior art of Smirnow (US2018/0315172) discloses a scaler circuit coupled to the second output of the demultiplexer to receive the second frequency data. The prior art of Giduthuri (US10742834) discloses a processor that is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data. The prior art of Choi (US10713993) discloses a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules. The prior art of Holland (US2019/0073176) discloses an image data processing pipeline having three processing blocks. The first block generates first processed image data by performing a first function on input image data. The second block generates second processed image data by performing a second function on the first processed image data. The third block performs a third function on the first processed image data or second processed image data from respective processing blocks. The prior art of Wang (US2017/0352182) discloses a graphics processing unit (GPU) that performs a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene. The prior art of Holland (US9105112) discloses a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. The prior art of Vavintaparthi (US2022/0343455) discloses a camera system having tag pipeline and EN pipeline connected to a memory and mux. The prior art of Ruggiero (US2006/0153475) discloses an image classifier using image processor 1 to image processor n to process input pixels. Thus, while many references teach image processing modules using pipeline processing plurality of processors to process input pixels, none of the references alone or in combination, provide a motivation to teach the device of claim 1 further in combination with : ”wherein the memory circuit is configured to provide a configurable delay to synchronize output data of the second processing circuitry and output data of the third processing circuitry”. Regarding independent claim 3, the prior art of Holland (US10474408) discloses a processing pipeline to instruct a first processing block to output first processed image data to the first circuit connection and a second processing block to output second processed image data to a third circuit connection when the first selectable data path is selected. The prior art of Smirnow (US2018/0315172) discloses a scaler circuit coupled to the second output of the demultiplexer to receive the second frequency data. The prior art of Giduthuri (US10742834) discloses a processor that is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data. The prior art of Choi (US10713993) discloses a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules. The prior art of Holland (US2019/0073176) discloses an image data processing pipeline having three processing blocks. The first block generates first processed image data by performing a first function on input image data. The second block generates second processed image data by performing a second function on the first processed image data. The third block performs a third function on the first processed image data or second processed image data from respective processing blocks. The prior art of Wang (US2017/0352182) discloses a graphics processing unit (GPU) that performs a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene. The prior art of Holland (US9105112) discloses a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. The prior art of Vavintaparthi (US2022/0343455) discloses a camera system having tag pipeline and EN pipeline connected to a memory and mux. The prior art of Ruggiero (US2006/0153475) discloses an image classifier using image processor 1 to image processor n to process input pixels. Thus, while many references teach image processing modules using pipeline processing plurality of processors to process input pixels, none of the references alone or in combination, provide a motivation to teach the device of claim 1 further in combination with : “ wherein the memory circuit is configured to synchronize output data of the second processing circuitry and output data of the third processing circuitry such that a difference between a horizontal delay of the output data of the second processing circuitry and a horizontal delay of the output data of the third processing circuitry is less than or equal to a horizontal blanking period”. Regarding independent claim 4, the prior art of Holland (US10474408) discloses a processing pipeline to instruct a first processing block to output first processed image data to the first circuit connection and a second processing block to output second processed image data to a third circuit connection when the first selectable data path is selected. The prior art of Smirnow (US2018/0315172) discloses a scaler circuit coupled to the second output of the demultiplexer to receive the second frequency data. The prior art of Giduthuri (US10742834) discloses a processor that is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data. The prior art of Choi (US10713993) discloses a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules. The prior art of Holland (US2019/0073176) discloses an image data processing pipeline having three processing blocks. The first block generates first processed image data by performing a first function on input image data. The second block generates second processed image data by performing a second function on the first processed image data. The third block performs a third function on the first processed image data or second processed image data from respective processing blocks. The prior art of Wang (US2017/0352182) discloses a graphics processing unit (GPU) that performs a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene. The prior art of Holland (US9105112) discloses a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. The prior art of Vavintaparthi (US2022/0343455) discloses a camera system having tag pipeline and EN pipeline connected to a memory and mux. The prior art of Ruggiero (US2006/0153475) discloses an image classifier using image processor 1 to image processor n to process input pixels. Thus, while many references teach image processing modules using pipeline processing plurality of processors to process input pixels, none of the references alone or in combination, provide a motivation to teach the device of claim 1 further in combination with : ” wherein: the first processing pipeline includes fourth processing circuitry coupled between the first processing circuitry and the second processing circuitry; and the second processing pipeline includes a multiplexer that includes:a first input coupled to an output of the first processing circuitry; a second input coupled to an output of the fourth processing circuitry; and an output coupled to the memory circuit”. Regarding dependent claim 5, the claims are allowed as being dependent of claim 4, respectively. Regarding independent claim 6, the prior art of Holland (US10474408) discloses a processing pipeline to instruct a first processing block to output first processed image data to the first circuit connection and a second processing block to output second processed image data to a third circuit connection when the first selectable data path is selected. The prior art of Smirnow (US2018/0315172) discloses a scaler circuit coupled to the second output of the demultiplexer to receive the second frequency data. The prior art of Giduthuri (US10742834) discloses a processor that is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data. The prior art of Choi (US10713993) discloses a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules. The prior art of Holland (US2019/0073176) discloses an image data processing pipeline having three processing blocks. The first block generates first processed image data by performing a first function on input image data. The second block generates second processed image data by performing a second function on the first processed image data. The third block performs a third function on the first processed image data or second processed image data from respective processing blocks. The prior art of Wang (US2017/0352182) discloses a graphics processing unit (GPU) that performs a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene. The prior art of Holland (US9105112) discloses a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. The prior art of Vavintaparthi (US2022/0343455) discloses a camera system having tag pipeline and EN pipeline connected to a memory and mux. The prior art of Ruggiero (US2006/0153475) discloses an image classifier using image processor 1 to image processor n to process input pixels. Thus, while many references teach image processing modules using pipeline processing plurality of processors to process input pixels, none of the references alone or in combination, provide a motivation to teach the device of claim 1 further in combination with : ”a buffer coupled to the second processing circuitry and the third processing circuitry; and a set of processing circuitry blocks coupled to the buffer, wherein the buffer is configured to: provide output data of the second processing circuitry to any of the set of processing circuitry blocks; and provide output data of the third processing circuitry to any of the set of processing circuitry blocks”. Regarding independent claim 10, the prior art of Holland (US10474408) discloses a processing pipeline to instruct a first processing block to output first processed image data to the first circuit connection and a second processing block to output second processed image data to a third circuit connection when the first selectable data path is selected. The prior art of Smirnow (US2018/0315172) discloses a scaler circuit coupled to the second output of the demultiplexer to receive the second frequency data. The prior art of Giduthuri (US10742834) discloses a processor that is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data. The prior art of Choi (US10713993) discloses a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules. The prior art of Holland (US2019/0073176) discloses an image data processing pipeline having three processing blocks. The first block generates first processed image data by performing a first function on input image data. The second block generates second processed image data by performing a second function on the first processed image data. The third block performs a third function on the first processed image data or second processed image data from respective processing blocks. The prior art of Wang (US2017/0352182) discloses a graphics processing unit (GPU) that performs a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene. The prior art of Holland (US9105112) discloses a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. The prior art of Vavintaparthi (US2022/0343455) discloses a camera system having tag pipeline and EN pipeline connected to a memory and mux. The prior art of Ruggiero (US2006/0153475) discloses an image classifier using image processor 1 to image processor n to process input pixels. Thus, while many references teach image processing modules using pipeline processing plurality of processors to process input pixels, none of the references alone or in combination, provide a motivation to teach the device of claim 9 further in combination with : ” wherein the memory is configured to provide a configurable delay such that output data of the second processing circuitry is synchronized to output data of the third processing circuitry”. Regarding independent claim 11, the prior art of Holland (US10474408) discloses a processing pipeline to instruct a first processing block to output first processed image data to the first circuit connection and a second processing block to output second processed image data to a third circuit connection when the first selectable data path is selected. The prior art of Smirnow (US2018/0315172) discloses a scaler circuit coupled to the second output of the demultiplexer to receive the second frequency data. The prior art of Giduthuri (US10742834) discloses a processor that is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data. The prior art of Choi (US10713993) discloses a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules. The prior art of Holland (US2019/0073176) discloses an image data processing pipeline having three processing blocks. The first block generates first processed image data by performing a first function on input image data. The second block generates second processed image data by performing a second function on the first processed image data. The third block performs a third function on the first processed image data or second processed image data from respective processing blocks. The prior art of Wang (US2017/0352182) discloses a graphics processing unit (GPU) that performs a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene. The prior art of Holland (US9105112) discloses a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. The prior art of Vavintaparthi (US2022/0343455) discloses a camera system having tag pipeline and EN pipeline connected to a memory and mux. The prior art of Ruggiero (US2006/0153475) discloses an image classifier using image processor 1 to image processor n to process input pixels. Thus, while many references teach image processing modules using pipeline processing plurality of processors to process input pixels, none of the references alone or in combination, provide a motivation to teach the device of claim 9 further in combination with : “ wherein the memory is configured to synchronize output data of the second processing circuitry and output data of the third processing circuitry such that a difference between a horizontal delay of the output data of the second processing circuitry and a horizontal delay of the output data of the third processing circuitry is less than or equal to a horizontal blanking period”. Regarding independent claim 12, the prior art of Holland (US10474408) discloses a processing pipeline to instruct a first processing block to output first processed image data to the first circuit connection and a second processing block to output second processed image data to a third circuit connection when the first selectable data path is selected. The prior art of Smirnow (US2018/0315172) discloses a scaler circuit coupled to the second output of the demultiplexer to receive the second frequency data. The prior art of Giduthuri (US10742834) discloses a processor that is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data. The prior art of Choi (US10713993) discloses a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules. The prior art of Holland (US2019/0073176) discloses an image data processing pipeline having three processing blocks. The first block generates first processed image data by performing a first function on input image data. The second block generates second processed image data by performing a second function on the first processed image data. The third block performs a third function on the first processed image data or second processed image data from respective processing blocks. The prior art of Wang (US2017/0352182) discloses a graphics processing unit (GPU) that performs a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene. The prior art of Holland (US9105112) discloses a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. The prior art of Vavintaparthi (US2022/0343455) discloses a camera system having tag pipeline and EN pipeline connected to a memory and mux. The prior art of Ruggiero (US2006/0153475) discloses an image classifier using image processor 1 to image processor n to process input pixels. Thus, while many references teach image processing modules using pipeline processing plurality of processors to process input pixels, none of the references provide a motivation to teach: “an interface configured to couple to an image capture device; a set of image processing circuitry blocks that includes: a first image processing circuitry block that includes: a first processing stage that includes: an input; and an output; a second processing stage that includes: an input; and an output; a set of intermediate processing stages coupled between the output of the first processing stage and the input of the second processing stage; a multiplexer that includes: a first input coupled to the output of the first processing stage; a second input coupled to an output of the set of intermediate processing stages; and an output; a first memory circuit that includes: an input coupled to the output of the multiplexer; and an output; and a third processing stage that includes: an input coupled to the output of the first memory circuit; and an output; and a second memory circuit coupled to each of the set of image processing circuitry blocks, wherein the second memory circuit is coupled to the output of the second processing stage and the output of the third processing stage", in combination with all other limitations of the claim. Regarding dependent claims 13-20, the claims are allowed as being dependent of claim 12, respectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG H LAM whose telephone number is (571)272-7367. The examiner can normally be reached 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TWYLER HASKINS can be reached at (571) 272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG H LAM/Primary Examiner, Art Unit 2639 05/17/26 Application/Control Number: 19/027,193 Page 2 Art Unit: 2639 Application/Control Number: 19/027,193 Page 3 Art Unit: 2639 Application/Control Number: 19/027,193 Page 4 Art Unit: 2639 Application/Control Number: 19/027,193 Page 6 Art Unit: 2639 Application/Control Number: 19/027,193 Page 7 Art Unit: 2639 Application/Control Number: 19/027,193 Page 8 Art Unit: 2639 Application/Control Number: 19/027,193 Page 9 Art Unit: 2639 Application/Control Number: 19/027,193 Page 10 Art Unit: 2639 Application/Control Number: 19/027,193 Page 11 Art Unit: 2639 Application/Control Number: 19/027,193 Page 12 Art Unit: 2639 Application/Control Number: 19/027,193 Page 13 Art Unit: 2639 Application/Control Number: 19/027,193 Page 14 Art Unit: 2639 Application/Control Number: 19/027,193 Page 15 Art Unit: 2639 Application/Control Number: 19/027,193 Page 16 Art Unit: 2639
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