DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 17 January 2025.
Claims 1-20 are pending and have been presented for examination.
Specification
The disclosure is objected to because of the following informalities: foreign language symbol is present in paragraph [00128].
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-9 and 12-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) obtaining a statistical result and making a determination based on the statistical result, which is considered a mental process or mathematical concept.
With respect to claim 1:
Eligibility step 1: Yes, the claim as a whole falls within one or more statutory categories.
Eligibility step 2A (prong one): Yes, the claim recites a judicial exception. An abstract idea is set forth or described in the claim. The limitations of “… obtain a statistical result of a physical page corresponding to a first read voltage…” and “… wherein the statistical result includes at least one of a first number of bits flipped between two read results of the physical page corresponding to the first read voltage and a read voltage having a voltage difference smaller than a preset voltage with the first read voltage, or a second number of bits of the physical page successfully read using the first read voltage, the first read voltage is greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page…” are considered mathematical relationships and/or mathematical calculations. A statistical result is a mathematical concept and is considered an abstract idea. The limitation of “… determine a data retention state of the physical page according to the statistical result…” is a mental process. The limitation is directed to an observation and judgment and can be reasonably performed in the human mind. A mental process is an abstract idea.
Eligibility step 2A (prong two): No, the claim does not recite additional elements that integrate the judicial exception into a practical application. The limitations regarding a memory controller, memory device and processor are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim.
Eligibility step 2B: The limitations regarding a memory controller, memory device and processor are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim. These elements individually, and in combination, do not add significantly more than the judicial exception. The claim as a whole does not amount to significantly more than the exception itself and therefore lacks subject matter eligibility.
With respect to claim 2: the additional limitations of “… determine whether the data retention state of the physical page is inferior according to a relationship between the statistical result and a preset threshold; and perform a data migration operation on the physical page in response to determining that the data retention state of the physical page is inferior.” Integrate the judicial exception into a practical application. The migration operation of physical page data based on the statistical result improves the computer system. Applicant has described the detrimental effect that a background read scrub has on the performance of the system [0091]. By performing a statistical analysis on the bits, the system can determine whether the change in bits are due to read disturb or retention shift [0087]. Migration based on the statistical analysis improves the performance by only needing to check the highest storage state during a read scrub and avoiding unnecessary garbage collection operations [0154], [0181], [0184].
With respect to claim 3: claim 3 is eligible based on the dependency to claim 2.
With respect to claim 4: the additional limitations are directed to data gathering and fail to add significantly more.
With respect to claim 5: the limitations regarding the memory cells are recited at a high level of granularity and generally link the abstract idea to a field of use. These limitations fail to add significantly more. The read mode limitations are directed to data gathering with respect to the bits that are analyzed in the mathematical concepts presented in claim 1. These limitations fail to add significantly more.
With respect to claim 6: the limitations regarding the interface are recited at a high level of granularity and generally link the abstract idea to a field of use. The limitations regarding receiving a statistical result, read results and counting the results are directed to data gathering with respect to the bits that are analyzed in the mathematical concepts presented in claim 1. These limitations fail to add significantly more.
With respect to claim 7: setting of the voltage and threshold are considered insignificant extra solution activity. These limitations alone, or in combination, fail to add significantly more that would integrate the judicial exception into a practical application.
With respect to claim 8: setting of the voltage and threshold are considered insignificant extra solution activity. These limitations alone, or in combination, fail to add significantly more that would integrate the judicial exception into a practical application.
With respect to claim 9:
Eligibility step 1: Yes, the claim as a whole falls within one or more statutory categories.
Eligibility step 2A (prong one): Yes, the claim recites a judicial exception. An abstract idea is set forth or described in the claim. The limitations of “… obtain a statistical result of a physical page corresponding to a first read voltage…” and “… wherein the statistical result includes at least one of a first number of bits flipped between two read results of the physical page corresponding to the first read voltage and a read voltage having a voltage difference smaller than a preset voltage with the first read voltage, or a second number of bits of the physical page successfully read using the first read voltage, the first read voltage is greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page…” are considered mathematical relationships and/or mathematical calculations. A statistical result is a mathematical concept and is considered an abstract idea. The limitation of “… determine a data retention state of the physical page according to the statistical result…” is a mental process. The limitation is directed to an observation and judgment and can be reasonably performed in the human mind. A mental process is an abstract idea.
Eligibility step 2A (prong two): No, the claim does not recite additional elements that integrate the judicial exception into a practical application. The limitations regarding a memory device, plurality of word lines and peripheral circuit are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim.
Eligibility step 2B: The limitations regarding a memory device, plurality of word lines and peripheral circuit are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim. These elements individually, and in combination, do not add significantly more than the judicial exception. The claim as a whole does not amount to significantly more than the exception itself and therefore lacks subject matter eligibility.
With respect to claim 10: the additional limitations of “… determine whether the data retention state of the physical page is inferior according to a relationship between the statistical result and a preset threshold; and perform a data migration operation on the physical page in response to determining that the data retention state of the physical page is inferior.” Integrate the judicial exception into a practical application. The migration operation of physical page data based on the statistical result improves the computer system. Applicant has described the detrimental effect that a background read scrub has on the performance of the system [0091]. By performing a statistical analysis on the bits, the system can determine whether the change in bits are due to read disturb or retention shift [0087]. Migration based on the statistical analysis improves the performance by only needing to check the highest storage state during a read scrub and avoiding unnecessary garbage collection operations [0154], [0181], [0184].
With respect to claim 11: claim 11 is eligible based on the dependency to claim 10.
With respect to claim 12: the limitations regarding the read voltage are considered insignificant extra solution activity and fail to add significantly more.
With respect to claim 13: the limitations regarding the memory cells are recited at a high level of granularity and generally link the abstract idea to a field of use. These limitations fail to add significantly more. The read mode limitations are directed to data gathering with respect to the bits that are analyzed in the mathematical concepts presented in claim 1. These limitations fail to add significantly more.
With respect to claim 14: the limitations regarding the read voltage are considered insignificant extra solution activity and fail to add significantly more.
With respect to claim 15: setting of the voltage and threshold are considered insignificant extra solution activity. These limitations alone, or in combination, fail to add significantly more that would integrate the judicial exception into a practical application.
With respect to claim 16: setting of the voltage and threshold are considered insignificant extra solution activity. These limitations alone, or in combination, fail to add significantly more that would integrate the judicial exception into a practical application.
With respect to claim 17: the use of a peripheral circuit to apply read voltages and float word lines is considered insignificant extra solution activity and fails to add significantly more. These limitations are related to general data gathering to be used inn the mathematical concepts recited in claim 9. The limitation of determining a data retention state is considered a mental process, as discussed above in claim 9.
With respect to claim 18: the use of a peripheral circuit to apply read voltages and adjust read voltages is considered insignificant extra solution activity and fails to add significantly more. The limitations of performing a logical operation, counting bits and obtaining a number is considered a mental process.
With respect to claim 19: the limitations are directed to limitations that apply to a field of use and fail to add significantly more.
With respect to claim 20:
Eligibility step 1: Yes, the claim as a whole falls within one or more statutory categories.
Eligibility step 2A (prong one): Yes, the claim recites a judicial exception. An abstract idea is set forth or described in the claim. The limitations of “… obtain a statistical result of a physical page corresponding to a first read voltage…” and “… wherein the statistical result includes at least one of a first number of bits flipped between two read results of the physical page corresponding to the first read voltage and a read voltage having a voltage difference smaller than a preset voltage with the first read voltage, or a second number of bits of the physical page successfully read using the first read voltage, the first read voltage is greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page…” are considered mathematical relationships and/or mathematical calculations. A statistical result is a mathematical concept and is considered an abstract idea. The limitation of “… determine a data retention state of the physical page according to the statistical result…” is a mental process. The limitation is directed to an observation and judgment and can be reasonably performed in the human mind. A mental process is an abstract idea.
Eligibility step 2A (prong two): No, the claim does not recite additional elements that integrate the judicial exception into a practical application. The limitations regarding a memory device, plurality of word lines, a peripheral circuit and a memory controller are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim.
Eligibility step 2B: The limitations regarding a memory device, plurality of word lines, a peripheral circuit and a memory controller are recited at a high level of granularity and generally link the abstract idea to a field of use. The linking to a field of use does not add significantly more to the claim. These elements individually, and in combination, do not add significantly more than the judicial exception. The claim as a whole does not amount to significantly more than the exception itself and therefore lacks subject matter eligibility.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 6, 7, 9-11, 14, 15 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JUAN (U.S. Patent Application Publication #2024/0201875) in view of DESANTIS (U.S. Patent Application Publication #2020/0152278).
1. JUAN discloses A memory controller (see [0065]: controller 200) coupled to at least one memory device (see [0062]: controller includes device interface pins to send and receive signals to/from semiconductor device), wherein a memory device of the at least one memory device comprises a plurality of word lines, each word line is coupled to a plurality of memory cells that form at least one physical page (see [0053]: memory cells coupled in series to form row word lines, which form pages), the memory controller comprising: a processor (see [0062]: controller includes a processor) configured to: obtain a statistical result of a physical page corresponding to a first read voltage (see [0098]: average number of mismatches; see also DESANTIS below), wherein the statistical result includes at least one of a first number of bits flipped between two read results of the physical page (see [0090]: data is read at multiple different read voltage) corresponding to the first read voltage and a read voltage having a voltage difference smaller than a preset voltage with the first read voltage (see [0092]: data is read at a default voltage, and a second voltage using a voltage step), or a second number of bits of the physical page successfully read using the first read voltage, the first read voltage is greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see DESANTIS below); and determine a data retention state of the physical page according to the statistical result (see [0101]: analysis of results are used to determine whether to perform an error correction process; [0077]-[0078]: the number of errors is used to determine the data retention degradation, which would be the data retention state).
DESANTIS discloses the following limitations that are not disclosed by JUAN: the statistical result includes a second number of bits of the physical page successfully read using the first read voltage, the first read voltage is greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see [0053]: percentage of cells that are activated using an intermediate read voltage). Using the statistical result of the number of cells activated, DESANTIS can determine the data age (see [0054]-[0055]). The data age would then indicate the data retention state (see [0047]). JUAN already discloses that as data is stored for longer periods of time, the number of error bits tends to increase (see [0042]). The teachings of DESANTIS would allow JUAN to more accurately determine data age (see [0046]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JUAN to obtain a statistical result of a second number of bits successfully read, as disclosed by DESANTIS. One of ordinary skill in the art would have been motivated to make such a modification to accurately determine a data age, as taught by DESANTIS. JUAN and DESANTIS are analogous/in the same field of endeavor as both references are directed to managing data retention in memory systems.
2. The memory controller of claim 1, wherein the processor is configured to: determine whether the data retention state of the physical page is inferior according to a relationship between the statistical result and a preset threshold (see JUAN [0100]: number of errors exceeds error threshold); and perform a data migration operation on the physical page in response to determining that the data retention state of the physical page is inferior (see JUAN [0100]: data is read, corrected, and stored to a portion of the memory, this is considered a data migration operation).
3. The memory controller of claim 2, wherein the preset threshold comprises at last one of a first threshold or a second threshold, and wherein the processor is configured to: determine that the data retention state of the physical page is inferior according to at least one of the first number being greater than the first threshold or the second number being greater than the second threshold (see JUAN [0100]: number of errors exceeds error threshold; DESANTIS [0053]: percent of active cells exceeds a threshold).
6. The memory controller of claim 1, wherein the memory controller further comprises an interface coupled to the processor (see [0062]: controller includes device interface pins to send and receive signals to/from semiconductor device) and configure to receive, from the memory device, at least one of: the statistical result of the physical page corresponding to the first read voltage, read results of the physical page corresponding to the first read voltage and a second read voltage respectively (see JUAN [0098]: average number of mismatches between pairs of readout data), or the read results of the physical page corresponding to the first read voltage, and wherein the processor is configured to perform operations and counting on the read results to obtain the statistical result (see [0095]: bitwise XOR to count number of mismatches).
7. The memory controller of claim 2, wherein the processor is configured to: when the memory controller is powered on, obtain the first read voltage and the preset threshold respectively from the memory device, wherein both the first read voltage and the preset threshold are fixed values (see JUAN [0092]: default values configured as part of the manufacturer and stored on the controller).
9. JUAN discloses A memory device, comprising: a plurality of word lines, wherein a word line of the plurality of word lines is coupled to a plurality of memory cells, and the plurality of memory cells form at least one physical page (see [0053]: memory cells coupled in series to form row word lines, which form pages); an a peripheral circuit coupled to the plurality of word lines (see [0134]: multiplexing device that provides an interface between the controller and the word lines of the memory) and configured to: obtain a statistical result of a physical page corresponding to a first read voltage (see [0098]: average number of mismatches; see also DESANTIS below), wherein the statistical result comprises at least one of a first number of bits flipped between two read results of the physical page (see [0090]: data is read at multiple different read voltage) corresponding to the first read voltage and a read voltage having a voltage difference of less than a preset voltage with the first read voltage (see [0092]: data is read at a default voltage, and a second voltage using a voltage step), or a second number of bits of the physical page successfully read using the first read voltage, the first read voltage being greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see DESANTIS below); and determine a data retention state of the physical page according to the statistical result (see [0101]: analysis of results are used to determine whether to perform an error correction process; [0077]-[0078]: the number of errors is used to determine the data retention degradation, which would be the data retention state).
DESANTIS discloses the following limitations that are not disclosed by JUAN: the statistical result includes a second number of bits of the physical page successfully read using the first read voltage, the first read voltage is greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see [0053]: percentage of cells that are activated using an intermediate read voltage). Using the statistical result of the number of cells activated, DESANTIS can determine the data age (see [0054]-[0055]). The data age would then indicate the data retention state (see [0047]). JUAN already discloses that as data is stored for longer periods of time, the number of error bits tends to increase (see [0042]). The teachings of DESANTIS would allow JUAN to more accurately determine data age (see [0046]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JUAN to obtain a statistical result of a second number of bits successfully read, as disclosed by DESANTIS. One of ordinary skill in the art would have been motivated to make such a modification to accurately determine a data age, as taught by DESANTIS. JUAN and DESANTIS are analogous/in the same field of endeavor as both references are directed to managing data retention in memory systems.
10. The memory device of claim 9, wherein the peripheral circuit is further configured to: determine whether the data retention state of the physical page is inferior according to a relationship between the statistical result and a preset threshold (see JUAN [0100]: number of errors exceeds error threshold); and perform a data migration operation on the physical page in response to determining that the data retention state of the physical page is inferior (see JUAN [0100]: data is read, corrected, and stored to a portion of the memory, this is considered a data migration operation).
11. The memory device of claim 10, wherein the preset threshold comprises at least one of a first threshold or a second threshold, and wherein the peripheral circuit is configured to: determine that the data retention state of the physical page is inferior according to at least one of the first number being greater than the first threshold or the second number being greater than the second threshold (see JUAN [0100]: number of errors exceeds error threshold; DESANTIS [0053]: percent of active cells exceeds a threshold).
14. The memory device of claim 10, wherein the peripheral circuit is configured to: obtain the first read voltage and the preset threshold respectively (see JUAN [0092]: default values configured as part of the manufacturer and stored on the controller).
15. The memory device of claim 14, wherein the peripheral circuit is configured to: when the memory device is powered on, obtain the first read voltage and the preset threshold respectively from the memory cell, wherein both the first read voltage and the preset threshold are fixed values (see JUAN [0092]: default values configured as part of the manufacturer and stored on the controller).
18. The memory device of claim 9, wherein the statistical result comprises the first number, and the peripheral circuit is configured to: read the stored data of the physical page using the first read voltage to obtain a first result (see JUAN [0090]: data read at multiple voltages, the first read uses a first voltage); adjust the first read voltage to obtain an adjusted read voltage, and read the stored data of the physical page using the adjusted read voltage to obtain a second result (see JUAN [0092]: the second read uses a second voltage based on a differential from the first voltage); perform a logical operation on the first result and the second result to obtain a third result (see JUAN [0095]: XOR operation); and count the number of bits in the third result that represent that the second result is flipped relative to the first result, to obtain the first number (see JUAN [0095]: results of the XOR operation are used to determine a count of mismatches).
19. The memory device of claim 18, wherein the peripheral circuit comprises a first latch, a second latch, and a third latch, and wherein the first latch is configured to store the first result (see JUAN [0103]: first page buffer), the second latch is configured to store the second result (see JUAN [0103]: second page buffer), and the third latch is configured to store the third result (see JUAN [0104]: circuitry for performing the XOR operations stores the result).
20. JUAN discloses A memory system, including: one or more memory devices (see [0069]: NAND flash memory device), a memory device of the one or more memory devices comprising: a plurality of word lines, wherein a word line of the plurality of word lines is coupled to a plurality of memory cells, and the plurality of memory cells form at least one physical page (see [0053]: memory cells coupled in series to form row word lines, which form pages); a peripheral circuit coupled to the plurality of word lines (see [0134]: multiplexing device that provides an interface between the controller and the word lines of the memory) and configured to: obtain a statistical result of a physical page corresponding to a first read voltage (see [0098]: average number of mismatches; see also DESANTIS below), wherein the statistical result comprises at least one of a first number of bits flipped between two read results of the physical page (see [0090]: data is read at multiple different read voltage) corresponding to the first read voltage and a read voltage having a voltage difference of less than a preset voltage with the first read voltage (see [0092]: data is read at a default voltage, and a second voltage using a voltage step), or a second number of bits of the physical page successfully read using the first read voltage, the first read voltage being greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see DESANTIS below); and determine a data retention state of the physical page according to the statistical result (see [0101]: analysis of results are used to determine whether to perform an error correction process; [0077]-[0078]: the number of errors is used to determine the data retention degradation, which would be the data retention state); and a memory controller coupled to the memory device and configured to control the memory device (see [0065]: memory controller).
DESANTIS discloses the following limitations that are not disclosed by JUAN: the statistical result includes a second number of bits of the physical page successfully read using the first read voltage, the first read voltage is greater than a mean value of a threshold voltage interval corresponding to an intermediate storage state of the physical page (see [0053]: percentage of cells that are activated using an intermediate read voltage). Using the statistical result of the number of cells activated, DESANTIS can determine the data age (see [0054]-[0055]). The data age would then indicate the data retention state (see [0047]). JUAN already discloses that as data is stored for longer periods of time, the number of error bits tends to increase (see [0042]). The teachings of DESANTIS would allow JUAN to more accurately determine data age (see [0046]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JUAN to obtain a statistical result of a second number of bits successfully read, as disclosed by DESANTIS. One of ordinary skill in the art would have been motivated to make such a modification to accurately determine a data age, as taught by DESANTIS. JUAN and DESANTIS are analogous/in the same field of endeavor as both references are directed to managing data retention in memory systems.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over JUAN (U.S. Patent Application Publication #2024/0201875) and DESANTIS (U.S. Patent Application Publication #2020/0152278) as applied to claims 1-3, 6, 7, 9-11, 14, 15 and 18-20 above, and further in view of DESAI (U.S. Patent Application Publication #2023/0114146).
8. The memory controller of claim 7, wherein the processor is configured to: when the memory controller is powered on, obtain an initial value of the first read voltage and an initial value of the preset threshold respectively from the memory device (see JUAN [0092]: default values configured as part of the manufacturer and stored on the controller); and modify, by setting a feature command, at least one of the initial value of the first read voltage or the initial value of the preset threshold to obtain the first read voltage and the preset threshold (see DESAI below).
DESAI discloses the following limitations that are not taught by JUAN: modify, by setting a feature command, at least one of the initial value of the first read voltage or the initial value of the preset threshold to obtain the first read voltage and the preset threshold (see [0031]: set feature command to adjust read voltage). The optimal voltage to read data can be affected by multiple conditions. Using the set feature command allows a voltage setting command to adjust the read voltage value to a new, optimal value, for reading the page (see [0031]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JUAN to use the set feature command, as disclosed by DESAI. One of ordinary skill in the art would have been motivated to make such a modification to adjust a read voltage to the optimal value, as taught by DESAI. JUAN and DESAI are analogous/in the same field of endeavor as both references are directed to reading data from flash memory.
16. The memory device of claim 14, wherein the peripheral circuit is configured to: when the memory device is powered on, obtain an initial value of the first read voltage and an initial value of the preset threshold respectively from the memory cell (see JUAN [0092]: default values configured as part of the manufacturer and stored on the controller); and modify, by setting a feature command, at least one of the initial value of the first read voltage or the initial value of the preset threshold to obtain the first read voltage and the preset threshold (see DESAI below).
DESAI discloses the following limitations that are not taught by JUAN: modify, by setting a feature command, at least one of the initial value of the first read voltage or the initial value of the preset threshold to obtain the first read voltage and the preset threshold (see [0031]: set feature command to adjust read voltage). The optimal voltage to read data can be affected by multiple conditions. Using the set feature command allows a voltage setting command to adjust the read voltage value to a new, optimal value, for reading the page (see [0031]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JUAN to use the set feature command, as disclosed by DESAI. One of ordinary skill in the art would have been motivated to make such a modification to adjust a read voltage to the optimal value, as taught by DESAI. JUAN and DESAI are analogous/in the same field of endeavor as both references are directed to reading data from flash memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LIU [12,579,023] discloses performing a first and second read, counting the number of bit flips, generating a histogram of bit flips, memory cell degradation and data refresh operations. [Columns 2, 4, 7-9, 13, 14]
REDDY [12,443,348] discloses performing a read scrub of a block before errors occur, targeted wordline refresh if the number or errors exceeds a threshold, estimate the number of bit flips based on age and queueing blocks for relocation based on estimated bit flip count. [Columns 6-7]
KWOK [2025/0210127] discloses first and second reading of data, count bits that don’t match between reads to determine error rate, if the error rate is above a threshold a refresh operation is triggered, page is read to a cache, errors corrected, then written back to storage. [0038], [0054]-[0057]
RIJO [11,734,110] discloses counting bit flips during a power on process, error testing and a bit flipped count. [Columns 11 and 13]
BHATIA [2022/0165337] discloses determining an optimal read voltage based on history of fail bit counts. [Abstract]
LU [2020/0117536] discloses multiple reads and counting of flipped bits and calibration of a read voltage level. [0045]-[0049]
SYU [2014/0059405] discloses estimating a data age during power on, data scrubbing to preserve data retention, scrubbing before page hits error rate and maintaining the time since last programming. [0026]-[0036]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain T Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132