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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314).
In re claim 1, U.S. Patent 11,250,991 discloses a multilayer ceramic capacitor comprising:
a stacked body including (Claim 1):
a first main surface and a second main surface opposite to each other in the stacking direction (Claim 1);
a first lateral surface and a second lateral surface opposite to each other in a longitudinal direction orthogonal or substantially orthogonal to the stacking direction (Claim 1); and
a third lateral surface and a fourth lateral surface opposite to each other in a width direction orthogonal or substantially orthogonal to the stacking direction and the longitudinal direction (Claim 1); and
four external electrodes disposed on the stacked body (Claim 1);
wherein
the stacked body includes:
and
an effective layer portion (Claim 1);
the effective layer portion includes:
first internal electrodes exposed at the first lateral surface, the second lateral surface (, the third lateral surface, and the fourth lateral surface (Claim 1); and
second internal electrodes exposed at the first lateral surface, the second lateral surface , the third lateral surface, and the fourth lateral surface (Claim 1);
the four external electrodes include:
a first external electrode covering a portion of each of the first main surface, the first lateral surface, the third lateral surface, and the second main surface (Claim 1);
a second external electrode covering a portion of each of the first main surface, the second lateral surface, and the fourth lateral surface, and the second main surface (Claim 1);
a third external electrode covering a portion of each of the first main surface, the first lateral surface, and the fourth lateral surface and the second main surface (Claim 1),
and a fourth external electrode covering a portion of each of the first main surface, the second lateral surface, and the third lateral surface, and the second main surface (Claim 1);
about 0.85 < W/L about 1, is satisfied, where L denotes a dimension of the multilayer ceramic capacitor in the longitudinal direction, and W denotes a dimension of the multilayer ceramic capacitor in the width direction (Claim 1); and
each of the surface areas A1, A2, A3, and A4 of the respective first, second, third, and fourth external electrodes is not less than about 22500 µm2 and not more than about 62500 µm2 viewed from a first main surface side in the stacking direction (Claim 3).
U.S. Patent No. 11,250,991 does not disclose outer layer portions and the outer layer portions include:
a first outer layer portion located between the first main surface and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes; and
a second outer layer portion located between the second main surface and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes;
Fuji discloses outer layer portions (portion of 10A4 above and below 13 – Figure 27, ¶94) and the outer layer portions include:
a first outer layer portion (portion of 10A4 above 13 – Figure 27) located between the first main surface (M1 – Figure 27) and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27); and
a second outer layer portion (portion of 10A4 below 13 – Figure 27) located between the second main surface (M2 – Figure 27) and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the outer layer portions of Fuji to increase the mechanical strength of the electronic component by protecting it from external impacts.
Claim 2 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Randall et al. (US Publication 2007/0165361).
In re claim 2, U.S. Patent 11,250,991 discloses a multilayer ceramic capacitor comprising:
a stacked body including (Claim 1):
a first main surface and a second main surface opposite to each other in the stacking direction (Claim 1);
a first lateral surface and a second lateral surface opposite to each other in a longitudinal direction orthogonal or substantially orthogonal to the stacking direction (Claim 1); and
a third lateral surface and a fourth lateral surface opposite to each other in a width direction orthogonal or substantially orthogonal to the stacking direction and the longitudinal direction (Claim 1); and
four external electrodes disposed on the stacked body (Claim 1);
wherein
the stacked body includes:
and
an effective layer portion (Claim 1);
the effective layer portion includes:
first internal electrodes exposed at the first lateral surface, the second lateral surface (, the third lateral surface, and the fourth lateral surface (Claim 1); and
second internal electrodes exposed at the first lateral surface, the second lateral surface , the third lateral surface, and the fourth lateral surface (Claim 1);
the four external electrodes include:
a first external electrode covering a portion of each of the first main surface, the first lateral surface, the third lateral surface, and the second main surface (Claim 1);
a second external electrode covering a portion of each of the first main surface, the second lateral surface, and the fourth lateral surface, and the second main surface (Claim 1);
a third external electrode covering a portion of each of the first main surface, the first lateral surface, and the fourth lateral surface and the second main surface (Claim 1),
and a fourth external electrode covering a portion of each of the first main surface, the second lateral surface, and the third lateral surface, and the second main surface (Claim 1);
about 0.85 < W/L about 1, is satisfied, where L denotes a dimension of the multilayer ceramic capacitor in the longitudinal direction, and W denotes a dimension of the multilayer ceramic capacitor in the width direction (Claim 1); and
U.S. Patent No. 11,250,991 does not disclose outer layer portions and the outer layer portions include:
a first outer layer portion located between the first main surface and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes; and
a second outer layer portion located between the second main surface and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes;
Fuji discloses outer layer portions (portion of 10A4 above and below 13 – Figure 27, ¶94) and the outer layer portions include:
a first outer layer portion (portion of 10A4 above 13 – Figure 27) located between the first main surface (M1 – Figure 27) and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27); and
a second outer layer portion (portion of 10A4 below 13 – Figure 27) located between the second main surface (M2 – Figure 27) and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the outer layer portions of Fuji to increase the mechanical strength of the electronic component by protecting it from external impacts.
U.S. Patent No. 11,250,991 does not disclose each of a maximum dimension of the first external electrode in the longitudinal direction, a maximum dimension of the first external electrode in the width direction, a maximum dimension of the second external electrode in the longitudinal direction, a maximum dimension of the second external electrode in the width direction, a maximum dimension of the third external electrode in the longitudinal direction, a maximum dimension of the third external electrode in the width direction, a maximum dimension of the fourth external electrode in the longitudinal direction, a maximum dimension of the fourth external electrode in the width direction is not less than about 150 µm and not more than about 250 µm viewed from a first main surface side in the stacking direction.
Randall discloses that adjusting the surface area of the external electrodes is directly proportional to the current flow and thus, overall inductance of the capacitor (¶42). It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the longitudinal and width dimensions of the eternal electrodes, and, thus, surface area of the external electrode on both main surfaces to balance the inductance of the device with manufacturing costs, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
3. Claim 3 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Take (US Publication 20210225592).
In re claim 3, U.S. Patent 11,250,991 discloses a multilayer ceramic capacitor comprising:
a stacked body including (Claim 1):
a first main surface and a second main surface opposite to each other in the stacking direction (Claim 1);
a first lateral surface and a second lateral surface opposite to each other in a longitudinal direction orthogonal or substantially orthogonal to the stacking direction (Claim 1); and
a third lateral surface and a fourth lateral surface opposite to each other in a width direction orthogonal or substantially orthogonal to the stacking direction and the longitudinal direction (Claim 1); and
four external electrodes disposed on the stacked body (Claim 1);
wherein
the stacked body includes:
and
an effective layer portion (Claim 1);
the effective layer portion includes:
first internal electrodes exposed at the first lateral surface, the second lateral surface (, the third lateral surface, and the fourth lateral surface (Claim 1); and
second internal electrodes exposed at the first lateral surface, the second lateral surface , the third lateral surface, and the fourth lateral surface (Claim 1);
the four external electrodes include:
a first external electrode covering a portion of each of the first main surface, the first lateral surface, the third lateral surface, and the second main surface (Claim 1);
a second external electrode covering a portion of each of the first main surface, the second lateral surface, and the fourth lateral surface, and the second main surface (Claim 1);
a third external electrode covering a portion of each of the first main surface, the first lateral surface, and the fourth lateral surface and the second main surface (Claim 1),
and a fourth external electrode covering a portion of each of the first main surface, the second lateral surface, and the third lateral surface, and the second main surface (Claim 1);
about 0.85 < W/L about 1, is satisfied, where L denotes a dimension of the multilayer ceramic capacitor in the longitudinal direction, and W denotes a dimension of the multilayer ceramic capacitor in the width direction (Claim 1); and
a ratio of min [A1, A2, A3, A4] to max [A1, A2, A3, A4] is not less than about 36% and less than 100%, where Ai, A2, A3, and A4 respectively denote surface areas of the first, second, third, and fourth external electrodes viewed from a first main surface side in the stacking direction (Claim 1).
U.S. Patent No. 11,250,991 does not disclose outer layer portions and the outer layer portions include:
a first outer layer portion located between the first main surface and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes; and
a second outer layer portion located between the second main surface and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes;
Fuji discloses outer layer portions (portion of 10A4 above and below 13 – Figure 27, ¶94) and the outer layer portions include:
a first outer layer portion (portion of 10A4 above 13 – Figure 27) located between the first main surface (M1 – Figure 27) and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27); and
a second outer layer portion (portion of 10A4 below 13 – Figure 27) located between the second main surface (M2 – Figure 27) and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the outer layer portions of Fuji to increase the mechanical strength of the electronic component by protecting it from external impacts.
U.S. Patent No. 11,250,991 does not disclose a configuration of the first external electrode is rectangular or substantially rectangular viewed from a first main surface side in the stacking direction.
Take discloses a configuration of the first external electrode (14 – Figure 1, ¶54) is rectangular or substantially rectangular viewed from a first main surface side in the stacking direction (Figure 6).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the external electrode structure as described by Take to provide for a component having improved ESL characteristics, reliability, and shielding from an external environment (¶75-78: Take).
4. Claims 4 and 7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Kim et al. (US Publication 2014/0185189).
In re claim 4, U.S. Patent No. 11,250,991 in view of Fuji discloses the multilayer ceramic capacitor according to claim 1, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm.
Kim discloses wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm (¶94, Table 2).
It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the dimensions oof the capacitor body as described by Kim to acquire a device having desired capacitance characteristics and miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 7, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Kim discloses the multilayer ceramic capacitor according to claim 4, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein a number of the first internal electrodes and the second internal electrodes is not less than about 20 and not more than about 80. However, it would have been obvious to a person having ordinary skill in the art to use the well-known knowledge of adjusting the number of first and second internal electrodes to achieve a device of desired capacitance, since it has been held that mere duplication of the essential working part of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
5. Claim 5 and 8 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Randall et al. (US Publication 2007/0165361) and in further view of Kim et al. (US Publication 2014/0185189).
In re claim 5, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Randall discloses the multilayer ceramic capacitor according to claim 1, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm.
Kim discloses wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm (¶94, Table 2).
It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the dimensions oof the capacitor body as described by Kim to acquire a device having desired capacitance characteristics and miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 8, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Randall and in further view of Kim discloses the multilayer ceramic capacitor according to claim 5, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein a number of the first internal electrodes and the second internal electrodes is not less than about 20 and not more than about 80. However, it would have been obvious to a person having ordinary skill in the art to use the well-known knowledge of adjusting the number of first and second internal electrodes to achieve a device of desired capacitance, since it has been held that mere duplication of the essential working part of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
6. Claim 6 and 9 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Take (US Publication 20210225592) and in further view of Kim et al. (US Publication 2014/0185189).
In re claim 6, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Take discloses the multilayer ceramic capacitor according to claim 3, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm.
Kim discloses wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm (¶94, Table 2).
It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the dimensions oof the capacitor body as described by Kim to acquire a device having desired capacitance characteristics and miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 9, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Take and in further view of Kim discloses the multilayer ceramic capacitor according to claim 6, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein a number of the first internal electrodes and the second internal electrodes is not less than about 20 and not more than about 80. However, it would have been obvious to a person having ordinary skill in the art to use the well-known knowledge of adjusting the number of first and second internal electrodes to achieve a device of desired capacitance, since it has been held that mere duplication of the essential working part of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
7. Claim 10 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108).
In re claim 10, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Kim discloses the multilayer ceramic capacitor according to claim 7, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein each of the four external electrodes includes an undercoating electrode layer and a plating layer;
the undercoating electrode includes Ni as a primary component;
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes.
Fuji discloses wherein each of the four external electrodes (21, 22, 23, 24 – Figure 26) includes an undercoating electrode layer and a plating layer (¶83);
the undercoating electrode includes Ni as a primary component (¶83);
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes (¶83; Note that the plating layer and the undercoating electrode are both directly and indirectly connected to the internal electrodes.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the plated layers as described by Fuji to provide for improved conductivity and mounting characteristics.
U.S. Patent No. 11,250,991 does not disclose a thickness of the undercoating electrode in the stacking direction is not less than about 1 µm and not more than about 5 µm.
Ikeda discloses adjusting the thickness of the external electrode is correlated with the ESR characteristics of the device (¶80).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the undercoating electrode to achieve a device having a desired balance between ESR characteristics and capacitance per unit of volume, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
8. Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Randall et al. (US Publication 2007/0165361) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108).
In re claim 11, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Randall and in further view of Kim discloses the multilayer ceramic capacitor according to claim 8, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein each of the four external electrodes includes an undercoating electrode layer and a plating layer;
the undercoating electrode includes Ni as a primary component;
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes.
Fuji discloses wherein each of the four external electrodes (21, 22, 23, 24 – Figure 26) includes an undercoating electrode layer and a plating layer (¶83);
the undercoating electrode includes Ni as a primary component (¶83);
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes (¶83; Note that the plating layer and the undercoating electrode are both directly and indirectly connected to the internal electrodes.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the plated layers as described by Fuji to provide for improved conductivity and mounting characteristics.
U.S. Patent No. 11,250,991 does not disclose a thickness of the undercoating electrode in the stacking direction is not less than about 1 µm and not more than about 5 µm.
Ikeda discloses adjusting the thickness of the external electrode is correlated with the ESR characteristics of the device (¶80).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the undercoating electrode to achieve a device having a desired balance between ESR characteristics and capacitance per unit of volume, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
9. Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Take (US Publication 20210225592) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108).
In re claim 12, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Take and in further view of Kim discloses the multilayer ceramic capacitor according to claim 9, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein each of the four external electrodes includes an undercoating electrode layer and a plating layer;
the undercoating electrode includes Ni as a primary component;
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes.
Fuji discloses wherein each of the four external electrodes (21, 22, 23, 24 – Figure 26) includes an undercoating electrode layer and a plating layer (¶83);
the undercoating electrode includes Ni as a primary component (¶83);
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes (¶83; Note that the plating layer and the undercoating electrode are both directly and indirectly connected to the internal electrodes.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the plated layers as described by Fuji to provide for improved conductivity and mounting characteristics.
U.S. Patent No. 11,250,991 does not disclose a thickness of the undercoating electrode in the stacking direction is not less than about 1 µm and not more than about 5 µm.
Ikeda discloses adjusting the thickness of the external electrode is correlated with the ESR characteristics of the device (¶80).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the undercoating electrode to achieve a device having a desired balance between ESR characteristics and capacitance per unit of volume, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
10. Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108) and in further view of Nishisaka et al. (US Publication 2013/0200749).
In re claim 13, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Kim and in further view of Ikeda discloses the multilayer ceramic capacitor according to claim 10, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer.
Nishisaka discloses wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer (¶87).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the multi-layered plating structure of Nishisaka to achieve an external electrode having both improved conductivity and mounting characteristics.
11. Claim 14 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Randall et al. (US Publication 2007/0165361) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108) and in further view of Nishisaka et al. (US Publication 2013/0200749).
In re claim 14, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Randall and in further view of Kim and in further view of Ikeda discloses the multilayer ceramic capacitor according to claim 11, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer.
Nishisaka discloses wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer (¶87).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the multi-layered plating structure of Nishisaka to achieve an external electrode having both improved conductivity and mounting characteristics.
In re claim 17, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Randall and in further view of Kim and in further view of Ikeda and in further view of Nishisaka discloses the multilayer ceramic capacitor according to claim 14, as explained above. U.S. Patent No. 11,250,991 further disclose each of the surface areas A1, A2, A3, and A4 of the respective first, second, third, and fourth external electrodes is not less than about 22500 µm2 and not more than about 62500 µm2 viewed from a first main surface side in the stacking direction (Claim 3).
12. Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Take (US Publication 20210225592) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108) and in further view of Nishisaka et al. (US Publication 2013/0200749).
In re claim 15, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Take and in further view of Kim and in further view of Ikeda discloses the multilayer ceramic capacitor according to claim 12, as explained above. U.S. Patent No. 11,250,991 does not disclose wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer.
Nishisaka discloses wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer (¶87).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the multi-layered plating structure of Nishisaka to achieve an external electrode having both improved conductivity and mounting characteristics.
13. Claim 13 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,250,991 in view of Fuji (US Publication 2016/0240314) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108) and in further view of Nishisaka et al. (US Publication 2013/0200749) and in further view of Randall et al. (US Publication 2007/0165361).
In re claim 16, U.S. Patent No. 11,250,991 in view of Fuji and in further view of Kim and in further view of Ikeda and in further view of Nishisaka discloses the multilayer ceramic capacitor according to claim 13, as explained above.
U.S. Patent No. 11,250,991 does not disclose each of a maximum dimension of the first external electrode in the longitudinal direction, a maximum dimension of the first external electrode in the width direction, a maximum dimension of the second external electrode in the longitudinal direction, a maximum dimension of the second external electrode in the width direction, a maximum dimension of the third external electrode in the longitudinal direction, a maximum dimension of the third external electrode in the width direction, a maximum dimension of the fourth external electrode in the longitudinal direction, a maximum dimension of the fourth external electrode in the width direction is not less than about 150 µm and not more than about 250 µm viewed from a first main surface side in the stacking direction.
Randall discloses that adjusting the surface area of the external electrodes is directly proportional to the current flow and thus, overall inductance of the capacitor (¶42). It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the longitudinal and width dimensions of the eternal electrodes, and, thus, surface area of the external electrode on both main surfaces to balance the inductance of the device with manufacturing costs, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuji (US Publication 2016/0240314) in view of Randall et al. (US Publication 2007/0165361).
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Figure 29 of Fuji with Examiner’s Comments (Figure 29EC)
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Figure 30 of Fuji with Examiner’s Comments (Figure 30EC)
In re claim 1, Fuji discloses a multilayer ceramic capacitor comprising:
a stacked body (10A4 – Figure 26, Figure 27, ¶182) including:
a first main surface (M1 – Figure 27, ¶182) and a second main surface (M2 – Figure 27, ¶182) opposite to each other in the stacking direction (Figure 27);
a first lateral surface (S1 – Figure 26, ¶183) and a second lateral surface (S2 – Figure 26, ¶182) opposite to each other in a longitudinal direction (‘L’ direction – Figure 26) orthogonal or substantially orthogonal to the stacking direction (Figure 26, Figure 27); and
a third lateral surface (S3 – Figure 26, ¶183) and a fourth lateral surface (S4 – Figure 26, ¶182) opposite to each other in a width direction (‘W’ direction – Figure 26) orthogonal or substantially orthogonal to the stacking direction and the longitudinal direction (Figure 26, Figure 27); and
four external electrodes (21, 22, 23, 24 – Figure 26, ¶182) disposed on the stacked body (Figure 26);
wherein
the stacked body includes:
outer layer portions (portion of 10A4 above and below 13 – Figure 27, ¶94) ; and
an effective layer portion (13 – Figure 27);
the effective layer portion includes:
first internal electrodes (12a – Figure 27, ¶95) exposed at the first lateral surface (S1 – Figure 29), the second lateral surface (S2 – Figure 29), the third lateral surface (S3 – Figure 29), and the fourth lateral surface (S4 – Figure 29); and
second internal electrodes (12b – Figure 27, ¶5) exposed at the first lateral surface (S1 – Figure 29), the second lateral surface (S2 – Figure 29), the third lateral surface (S3 – Figure 29), and the fourth lateral surface (S4 – Figure 29);
the four external electrodes include:
a first external electrode (21 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26, Figure 28), the first lateral surface (S1 – Figure 29, Figure 26), the third lateral surface (S3 – Figure 29, Figure 26), and the second main surface (M2 – Figure 28);
a second external electrode (22 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26, Figure 27), the second lateral surface (S2 – Figure 26, Figure 27), and the fourth lateral surface (S4 – Figure 26), and the second main surface (M2 – Figure 28, Figure 27),;
a third external electrode (23 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26), the first lateral surface (S1 – Figure 26), and the fourth lateral surface (S4 – Figure 26); and the second main surface (M2 – Figure 28),
and a fourth external electrode (24 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26), the second lateral surface (S2 – Figure 26, Figure 27, Figure 28), and the third lateral surface (S3 – Figure 26, Figure 27, Figure 28); and the second main surface (M1 – Figure 26, Figure 27, Figure 28);
the outer layer portions include:
a first outer layer portion (portion of 10A4 above 13 – Figure 27) located between the first main surface (M1 – Figure 27) and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27); and
a second outer layer portion (portion of 10A4 below 13 – Figure 27) located between the second main surface (M2 – Figure 27) and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27);
about 0.85 < W/L about 1, is satisfied (See Figure 10, ¶128), where L denotes a dimension of the multilayer ceramic capacitor in the longitudinal direction, and W denotes a dimension of the multilayer ceramic capacitor in the width direction (Figure 26).
Fuji does not disclose each of the surface areas A1, A2, A3, and A4 of the respective first, second, third, and fourth external electrodes is not less than about 22500 µm2 and not more than about 62500 µm2 viewed from a first main surface side in the stacking direction.
Randall discloses that the surface area of the external electrodes is directly proportional to the current flow and thus, overall inductance of the capacitor (¶42). It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the surface area of the external electrode on both main surfaces to balance the inductance of the device with manufacturing costs, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 2, Fuji discloses a multilayer ceramic capacitor comprising:
a stacked body (10A4 – Figure 26, Figure 27, ¶182) including:
a first main surface (M1 – Figure 27, ¶182) and a second main surface (M2 – Figure 27, ¶182) opposite to each other in the stacking direction (Figure 27);
a first lateral surface (S1 – Figure 26, ¶183) and a second lateral surface (S2 – Figure 26, ¶182) opposite to each other in a longitudinal direction (‘L’ direction – Figure 26) orthogonal or substantially orthogonal to the stacking direction (Figure 26, Figure 27); and
a third lateral surface (S3 – Figure 26, ¶183) and a fourth lateral surface (S4 – Figure 26, ¶182) opposite to each other in a width direction (‘W’ direction – Figure 26) orthogonal or substantially orthogonal to the stacking direction and the longitudinal direction (Figure 26, Figure 27); and
four external electrodes (21, 22, 23, 24 – Figure 26, ¶182) disposed on the stacked body (Figure 26);
wherein
the stacked body includes:
outer layer portions (portion of 10A4 above and below 13 – Figure 27, ¶94) ; and
an effective layer portion (13 – Figure 27);
the effective layer portion includes:
first internal electrodes (12a – Figure 27, ¶95) exposed at the first lateral surface (S1 – Figure 29), the second lateral surface (S2 – Figure 29), the third lateral surface (S3 – Figure 29), and the fourth lateral surface (S4 – Figure 29); and
second internal electrodes (12b – Figure 27, ¶5) exposed at the first lateral surface (S1 – Figure 29), the second lateral surface (S2 – Figure 29), the third lateral surface (S3 – Figure 29), and the fourth lateral surface (S4 – Figure 29);
the outer layer portions include:
a first outer layer portion (portion of 10A4 above 13 – Figure 27) located between the first main surface (M1 – Figure 27) and an internal electrode that is closest to the first main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27); and
a second outer layer portion (portion of 10A4 below 13 – Figure 27) located between the second main surface (M2 – Figure 27) and an internal electrode that is closest to the second main surface in the first internal electrodes and the second internal electrodes (12a, 12b – Figure 27);
the four external electrodes include:
a first external electrode (21 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26, Figure 28), the first lateral surface (S1 – Figure 29, Figure 26), the third lateral surface (S3 – Figure 29, Figure 26), and the second main surface (M2 – Figure 28);
a second external electrode (22 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26, Figure 27), the second lateral surface (S2 – Figure 26, Figure 27), and the fourth lateral surface (S4 – Figure 26), and the second main surface (M2 – Figure 28, Figure 27),;
a third external electrode (23 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26), the first lateral surface (S1 – Figure 26), and the fourth lateral surface (S4 – Figure 26); and the second main surface (M2 – Figure 28),
and a fourth external electrode (24 – Figure 26) covering a portion of each of the first main surface (M1 – Figure 26), the second lateral surface (S2 – Figure 26, Figure 27, Figure 28), and the third lateral surface (S3 – Figure 26, Figure 27, Figure 28); and the second main surface (M1 – Figure 26, Figure 27, Figure 28),
about 0.85 < W/L about 1, is satisfied (See Figure 10, ¶128), where L denotes a dimension of the multilayer ceramic capacitor in the longitudinal direction, and W denotes a dimension of the multilayer ceramic capacitor in the width direction (Figure 26).
Fuji does not disclose each of a maximum dimension of the first external electrode in the longitudinal direction, a maximum dimension of the first external electrode in the width direction, a maximum dimension of the second external electrode in the longitudinal direction, a maximum dimension of the second external electrode in the width direction, a maximum dimension of the third external electrode in the longitudinal direction, a maximum dimension of the third external electrode in the width direction, a maximum dimension of the fourth external electrode in the longitudinal direction, a maximum dimension of the fourth external electrode in the width direction is not less than about 150 µm and not more than about 250 µm viewed from a first main surface side in the stacking direction.
Randall discloses that adjusting the surface area of the external electrodes is directly proportional to the current flow and thus, overall inductance of the capacitor (¶42). It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the longitudinal and width dimensions of the eternal electrodes, and, thus, surface area of the external electrode on both main surfaces to balance the inductance of the device with manufacturing costs, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claims 4-5 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuji (US Publication 2016/0240314) in view of Randall et al. (US Publication 2007/0165361) and in further view of Kim et al. (US Publication 2014/0185189).
In re claim 4, Fuji discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji does not disclose wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm.
Kim discloses wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm (¶94, Table 2).
It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the dimensions oof the capacitor body as described by Kim to acquire a device having desired capacitance characteristics and miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 5, Fuji discloses the multilayer ceramic capacitor according to claim 2, as explained above. Fuji does not disclose wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm.
Kim discloses wherein a dimension of the multilayer ceramic capacitor in the stacking direction is not less than about 50 µm and not more than about 110 µm (¶94, Table 2).
It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the dimensions oof the capacitor body as described by Kim to acquire a device having desired capacitance characteristics and miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 7, Fuji in view of Randall and in further view of Kim discloses the multilayer ceramic capacitor according to claim 4, as explained above. Fuji does not explicitly disclose wherein a number of the first internal electrodes and the second internal electrodes is not less than about 20 and not more than about 80. However, it would have been obvious to a person having ordinary skill in the art to use the well-known knowledge of adjusting the number of first and second internal electrodes to achieve a device of desired capacitance, since it has been held that mere duplication of the essential working part of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
In re claim 8, Fuji in view of Randall and in further view of Kim discloses the multilayer ceramic capacitor according to claim 5, as explained above. Fuji does not explicitly disclose wherein a number of the first internal electrodes and the second internal electrodes is not less than about 20 and not more than about 80. However, it would have been obvious to a person having ordinary skill in the art to use the well-known knowledge of adjusting the number of first and second internal electrodes to achieve a device of desired capacitance, since it has been held that mere duplication of the essential working part of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claims 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuji (US Publication 2016/0240314) in view of Randall et al. (US Publication 2007/0165361) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108).
In re claim 10, Fuji in view of Randall and in further view of Kim discloses the multilayer ceramic capacitor according to claim 7, as explained above. Fuji further discloses wherein each of the four external electrodes (21, 22, 23, 24 – Figure 26) includes an undercoating electrode layer and a plating layer (¶83);
the undercoating electrode includes Ni as a primary component (¶83);
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes (¶83; Note that the plating layer and the undercoating electrode are both directly and indirectly connected to the internal electrodes.).
Fuji does not disclose a thickness of the undercoating electrode in the stacking direction is not less than about 1 µm and not more than about 5 µm.
Ikeda discloses adjusting the thickness of the external electrode is correlated with the ESR characteristics of the device (¶80).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the undercoating electrode to achieve a device having a desired balance between ESR characteristics and capacitance per unit of volume, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 11, Fuji in view of Randall and in further view of Kim discloses the multilayer ceramic capacitor according to claim 8, as explained above. Fuji further discloses wherein each of the four external electrodes (21, 22, 23, 24 – Figure 26) includes an undercoating electrode layer and a plating layer (¶83);
the undercoating electrode includes Ni as a primary component (¶83);
and the plating layer is connected to the undercoating electrode and one of the first internal electrodes and the second internal electrodes (¶83; Note that the plating layer and the undercoating electrode are both directly and indirectly connected to the internal electrodes.).
Fuji does not disclose a thickness of the undercoating electrode in the stacking direction is not less than about 1 µm and not more than about 5 µm.
Ikeda discloses adjusting the thickness of the external electrode is correlated with the ESR characteristics of the device (¶80).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the undercoating electrode to achieve a device having a desired balance between ESR characteristics and capacitance per unit of volume, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claims 13-14 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuji (US Publication 2016/0240314) in view of Randall et al. (US Publication 2007/0165361) and in further view of Kim et al. (US Publication 2014/0185189) and in further view of Ikeda et al. (US Publication 2016/0172108) and in further view of Nishisaka et al. (US Publication 2013/0200749).
In re claim 13, Fuji in view of Randall and in further view of Kim and in further view of Ikeda discloses the multilayer ceramic capacitor according to claim 10, as explained above. Fuji does not disclose wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer.
Nishisaka discloses wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer (¶87).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the multi-layered plating structure of Nishisaka to achieve an external electrode having both improved conductivity and mounting characteristics.
In re claim 14, Fuji in view of Randall and in further view of Kim and in further view of Ikeda discloses the multilayer ceramic capacitor according to claim 11, as explained above. Fuji does not disclose wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer.
Nishisaka discloses wherein the plating layer includes a Cu plating layer, a Ni plating and a Sn plating layer; and
an average thickness of the Cu plating layer is more than each of an average thickness of the Ni plating layer and an average thickness of the Sn plating layer (¶87).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the multi-layered plating structure of Nishisaka to achieve an external electrode having both improved conductivity and mounting characteristics.
In re claim 16, Fuji in view of Randall and in further view of Kim and in further view of Ikeda discloses the multilayer ceramic capacitor according to claim 10, as explained above. Fuji does not disclose each of a maximum dimension of the first external electrode in the longitudinal direction, a maximum dimension of the first external electrode in the width direction, a maximum dimension of the second external electrode in the longitudinal direction, a maximum dimension of the second external electrode in the width direction, a maximum dimension of the third external electrode in the longitudinal direction, a maximum dimension of the third external electrode in the width direction, a maximum dimension of the fourth external electrode in the longitudinal direction, a maximum dimension of the fourth external electrode in the width direction is not less than about 150 µm and not more than about 250 µm viewed from a first main surface side in the stacking direction.
Randall discloses that adjusting the surface area of the external electrodes is directly proportional to the current flow and thus, overall inductance of the capacitor (¶42). It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the longitudinal and width dimensions of the eternal electrodes, and, thus, surface area of the external electrode on both main surfaces to balance the inductance of the device with manufacturing costs, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 17, Fuji in view of Randall and in further view of Kim and in further view of Ikeda discloses the multilayer ceramic capacitor according to claim 14, as explained above.
Fuji does not disclose each of the surface areas A1, A2, A3, and A4 of the respective first, second, third, and fourth external electrodes is not less than about 22500 µm2 and not more than about 62500 µm2 viewed from a first main surface side in the stacking direction.
Randall discloses that the surface area of the external electrodes is directly proportional to the current flow and thus, overall inductance of the capacitor (¶42). It would have been obvious to a person having ordinary skill in the art at the effective filing date of the invention to adjust the surface area of the external electrode on both main surfaces to balance the inductance of the device with manufacturing costs, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US Publication 2009/0086406) Figure 1, Figure 4
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/ARUN RAMASWAMY/ Primary Examiner, Art Unit 2848
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