DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 21-40 are pending
Claims 21-40 are rejected under 35 USC § 103
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/17/2025 and 01/21/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-40 are rejected under 35 U.S.C. 103 as being unpatentable over Woo; Su Hae (US 10861577 B2)[Woo]
Regarding claim 21 Woo discloses:
A memory device comprising: a plurality of memory packages (Woo: col4/ln4-col4/ln26, FIG. 1: teaches the memory module 10 includes eighteen memory packages 100 (i.e., first to eighteenth memory packages PKG01˜PKG18)); and a memory repair circuit (Woo: (28), FIG. 6: col5/ln46-col6/ln15: test circuit 403) configured to:
perform a first repair analysis to obtain first fail information for the plurality of memory packages, the first fail information including one or more fail addresses (Woo: (5): col1/ln55-col1/ln67: teaches a test circuit where the test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. Woo: (5): col5/ln46-col6/ln15: teaches the test circuit 403 storing a status of the redundancy regions in the memory medium 30 and addresses of repair target regions in the memory medium 30.) and
a fail bit count for the one or more fail addresses (Woo: (37): col8/ln30-col8/ln64: teaches the BIST circuit 410 transmits the fail information on the memory packages 100 to the URC circuit 421 of the BIRA circuit 420 after the test operation is performed. Woo: (39): col9/ln22-col9/ln59, Fig. 12: teaches the number of bits included in the fail information for each package is determined by the maximum number of failed memory cells in each memory package. The number of failed memory cells is similar to fail bit count),
select a target address from among the one or more fail addresses (Woo: (5): col1/ln55-col1/ln67: teaches the built-in repair analysis (BIRA) circuit receiving the fail information from the BIST circuit and selecting at least one of the plurality of memory packages as a repair target memory package),
lock the target address (Woo: (5): col5/ln46-col6/ln15: teaches test circuit 403 performing a repair operation of the repair target memory package which is selected according to the test result. In addition, the test circuit 403 stores a status of the redundancy regions in the memory medium 30 and addresses of repair target regions in the memory medium 30. Selecting a target memory package and selecting addresses of repair target regions for repair is similar to locking target addresses),
perform a second repair analysis to obtain second fail information for the plurality of memory packages excluding the target address for the one or more fail addresses (Woo: (5): col1/ln55-col1/ln67: The built-in repair analysis (BIRA) circuit receive the fail information from the BIST circuit to select at least one of the plurality of memory packages as a repair target memory package. Woo: (5): col5/ln46-col6/ln15: teaches the test circuit 403 storing a status of the redundancy regions in the memory medium 30 and addresses of repair target regions in the memory medium 30. Woo performs repair analysis of plurality of memory packages which includes performing first/second/third and more repair analysis. Selecting addresses of repair target includes selecting first/second/third and more repair target regions and indicating each address is exclusive which is same as second address excluding first address, third address excluding first and second address and so on), and
output a result of the first repair analysis and the second repair analysis (Woo: (5): col1/ln55-col1/ln67: teaches a test circuit where the test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. Woo: (35): col8/ln1-col8/ln21: teaches the RARFC circuit 423 transmitting information on the repair target memory packages and repair target addresses are output to the RA circuit 422 during the built-in repair analysis (BIRA) operation.
Regarding claim 22 Woo discloses: The memory device of claim 21, wherein the memory repair circuit is further configured to select the target address from among the one or more fail addresses based on the fail bit count (Woo: (54-55), col15/ln51-col16/ln42: teaches selecting a repair target memory package based on the numbers (fcn) of failed memory cells).
Regarding claim 23 Woo discloses: The memory device of claim 21, wherein the memory repair circuit is further configured to select, as the target address, a fail address having a least fail bit count from among the one or more fail addresses (Woo: (54-55), col15/ln51-col16/ln42: teaches memory packages having failed memory cells is selected as the repair target memory packages in order of the updated number (ufcn) of failed memory cells from the memory package having the smallest number (fcn) of failed memory cells.).
Regarding claim 24 Woo discloses: The memory device of claim 21, wherein the memory repair circuit is further configured to select, as the target address, a fail address having the fail bit count less than a threshold from among the one or more fail addresses (Woo: (33), col7/ln18-col7/ln45: teaches the built-in repair analysis (BIRA) operation is performed if the number of all of failed memory cells included in the cell array regions is less than the failure criterion (FC) (similar to threshold)).
Regarding claim 25 Woo discloses: The memory device of claim 21, wherein the memory repair circuit is further configured to repair the target address using an error correction code (ECC) (Woo: (6), col2/ln1-col2/ln17: teaches the module controller including an error correction code (ECC) circuit and a test circuit. The repair target memory package is selected by considering an error correction capability of the error correction code (ECC) circuit.).
Regarding claim 26 Woo discloses: The memory device of claim 21, wherein the memory repair circuit is further configured to repair one or more first fail bits of the one or more fail addresses using an ECC based on the result of the first repair analysis and the second repair analysis (Woo: (28), col5/ln46-col6/ln15: teaches read data being outputted from the memory medium 30 are inputted to the ECC circuit 404, the ECC circuit 404 performing an ECC decoding operation of the read data to correct erroneous bits of the read data and outputing the corrected read data to the host 20 through the front physical layer 401-1. The error correction capability of the ECC circuit 404 is defined as the number of maximum erroneous bits that are able to be corrected by the ECC encoding operation and the ECC decoding operation. Woo: (32), col6/ln62-col7/ln17: teaches the unrepair control (URC) circuit 421 setting a failure criterion (FC) restricted within the range of the error correction capability of the ECC circuit 404 in order to consider the error correction capability of the ECC circuit 404 during operation of the URC circuit 421. So, ECC error correction has a limit of fixing the number of errors and Woo defines failure criterion to determine if the fix should be done using ECC if it is within ECC capability or it should be fixed using availability of usable redundancy regions.).
Regarding claim 27 Woo discloses: The memory device of claim 26, wherein the memory repair circuit is further configured to repair one or more second fail bits of the one or more fail addresses using redundant addresses based on the result of the first repair analysis and the second repair analysis (Woo: (6), col2/ln1-col2/ln17: teaches the repair target memory package being selected by considering an error correction capability of the error correction code (ECC) circuit and usability of redundancy regions included in each of the plurality of memory packages. Woo: (26), col5/ln1-col5/ln30: teaches the cell array region including a data storage region and a redundancy region. The data storage region corresponding to a cell region including main memory cells, and the redundancy region is a cell region including redundant memory cells for replacing failed memory cells among the main memory cells. As shared earlier, ECC error correction has a limit of fixing the number of errors and Woo defines failure criterion to determine if the fix should be done using ECC if it is within ECC capability or it should be fixed using availability of usable redundancy regions).
Regarding claim 28 Woo discloses: A memory device comprising a plurality of memory packages (Woo: col4/ln4-col4/ln26, FIG. 1: teaches the memory module 10 includes eighteen memory packages 100 (i.e., first to eighteenth memory packages PKG01˜PKG18)); and a memory repair circuit (Woo: (28), FIG. 6: col5/ln46-col6/ln15: test circuit 403) configured to:
perform a first repair analysis to obtain first fail information for the plurality of memory packages (Woo: (5): col1/ln55-col1/ln67: teaches a test circuit where the test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information.), the first fail information including: a first set of fail addresses associated with at least one memory package of the plurality of memory packages (Woo: (38), col8/ln65-col9/ln21, FIG. 11: teaches fail information being transmitted from the BIST circuit 410 to the URC circuit 421 of the BIRA circuit 420 includes fail information for each memory package), and
a first set of fail bit counts, each fail bit count of the first set of fail bit counts being associated with one or more fail addresses of the first set of fail addresses (Woo: (37): col8/ln30-col8/ln64: teaches the BIST circuit 410 transmits the fail information on the memory packages 100 to the URC circuit 421 of the BIRA circuit 420 after the test operation is performed. Woo: (39): col9/ln22-col9/ln59, Fig. 12: teaches the number of bits included in the fail information for each package is determined by the maximum number of failed memory cells in each memory package. The number of failed memory cells is similar to fail bit count),
select a target address from among the first set of fail addresses (Woo: (5): col1/ln55-col1/ln67: teaches the built-in repair analysis (BIRA) circuit receiving the fail information from the BIST circuit and selecting at least one of the plurality of memory packages as a repair target memory package),
lock the target address (Woo: (28), col5/ln46-col6/ln15: teaches test circuit 403 performing a repair operation of the repair target memory package which is selected according to the test result. The test circuit 403 stores a status of the redundancy regions in the memory medium 30 and addresses of repair target regions in the memory medium 30. Selecting a target memory package and selecting addresses of repair target regions for repair is similar to locking target addresses),
perform a second repair analysis to obtain second fail information for the plurality of memory packages (Woo: (33), col7/ln17-col7/ln45: If the number of all of failed memory cells included in the cell array regions is less than the failure criterion (FC), the built-in repair analysis (BIRA) operation may be continuously performed which includes performing second/third… repair analysis), the second fail information including: a second set of fail address associated with at least one memory package of the plurality of memory packages excluding the target address from the first set of fail addresses (Woo: (34), col7/ln46-col7/ln67: teaches repair analysis (BIRA) operation continuing with the number of the failed memory cells that remains after subtracting the number of the failed memory cells in the repair target memory package from a total number of the failed memory cells and the updated number of the failed memory cells is less than the failure criterion (FC). So, Woo teaches performing repair analysis (BIRA) continuously (similar to second/third .. analysis) with remaining/unfixed failed cells (similar to excluding previously fixed failed cells)), and
output a result of the first and second repair analyses, the result comprising one or more first fail bits (Woo: (5): col1/ln55-col1/ln67: teaches a test circuit where the test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. Woo: (35): col8/ln1-col8/ln21: teaches the repair address register file control (RARFC) circuit 423 transmitting information on the repair target memory packages and repair target addresses are output to the repair analysis circuit 422 during the built-in repair analysis (BIRA) operation).
Regarding claim 29 Woo discloses: The memory device of claim 28, wherein the one or more first fail bits are bits capable of being repaired using error correction code (ECC) (Woo: (28), col5/ln46-col6/ln15: teaches read data being outputted from the memory medium 30 are inputted to the ECC circuit 404, the ECC circuit 404 performing an ECC decoding operation of the read data to correct erroneous bits of the read data and outputting the corrected read data to the host 20 through the front physical layer 401-1. The error correction capability of the ECC circuit 404 is defined as the number of maximum erroneous bits that are able to be corrected by the ECC encoding operation and the ECC decoding operation.).
Regarding claim 30 Woo discloses: The memory device of claim 29, wherein the memory repair circuit is further configured to repair one or more second fail bits of the one or more fail addresses using redundant addresses (Woo: (32), col6/ln62-col7/ln17: teaches the unrepair control (URC) circuit 421 setting a failure criterion (FC) restricted within the range of the error correction capability of the ECC circuit 404 in order to consider the error correction capability of the ECC circuit 404 during operation of the URC circuit 421. So, ECC error correction has a limit of fixing the number of errors and Woo defines failure criterion to determine if the fix should be done using ECC if it is within ECC capability or it should be fixed using availability of usable redundancy regions.).
Regarding claim 31 Woo discloses: The memory device of claim 28, wherein the target address comprises the one or more first fail bits (Woo: (54-55), col15/ln51-col16/ln42: teaches memory packages having failed memory cells are selected as the repair target memory packages in order of the updated number (ufcn) of failed memory cells from the memory package having the smallest number (fcn) of failed memory cells.).
Regarding claim 32 Woo discloses: The memory device of claim 28, wherein the memory repair circuit is further configured to select the target address from among the one or more fail addresses based on the first set of fail bit counts (Woo: (54-55), col15/ln51-col16/ln42: teaches selecting a repair target memory package based on the numbers (fcn) of failed memory cells. Collecting failed bits and repairing them is a continuous process and the first instance/iteration involves first set of bit counts.).
Regarding claim 33 Woo discloses: The memory device of claim 28, wherein the memory repair circuit is further configured to select, as the target address, a fail address having a least fail bit count from among the one or more fail addresses (Woo: (54-55), col15/ln51-col16/ln42: teaches memory packages having failed memory cells are selected as the repair target memory packages in order of the updated number (ufcn) of failed memory cells from the memory package having the smallest number (fcn) of failed memory cells.).
Regarding claim 34 Woo discloses: The memory device of claim 28, wherein the memory repair circuit is further configured to select, as the target address, a fail address having the fail bit count less than a threshold from among the one or more fail addresses (Woo: (33), col7/ln18-col7/ln45: teaches the built-in repair analysis (BIRA) operation is performed if the number of all of failed memory cells included in the cell array regions is less than the failure criterion (FC) (similar to threshold)).
Regarding claim 35 Woo discloses: An operating method of a memory device comprising a plurality of memory packages (Woo: col4/ln4-col4/ln26, FIG. 1: teaches the memory module 10 including eighteen memory packages 100 (i.e., first to eighteenth memory packages PKG01˜PKG18)), the method comprising: performing a first repair analysis to obtain first fail information for the plurality of memory packages, the first fail information including one or more fail addresses (Woo: (5): col1/ln55-col1/ln67: teaches a test circuit where the test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. Woo: (5): col5/ln46-col6/ln15: teaches the test circuit 403 storing a status of the redundancy regions in the memory medium 30 and addresses of repair target regions in the memory medium 30) and
a fail bit count for the one or more fail addresses (Woo: (37): col8/ln30-col8/ln64: teaches the BIST circuit 410 transmits the fail information on the memory packages 100 to the URC circuit 421 of the BIRA circuit 420 after the test operation is performed. Woo: (39): col9/ln22-col9/ln59, Fig. 12: teaches the number of bits included in the fail information for each package is determined by the maximum number of failed memory cells in each memory package. The number of failed memory cells is similar to fail bit count); selecting a target address from among the one or more fail addresses (Woo: (5): col1/ln55-col1/ln67: teaches the built-in repair analysis (BIRA) circuit receiving the fail information from the BIST circuit and selecting at least one of the plurality of memory packages as a repair target memory package); locking the target address (Woo: (5): col5/ln46-col6/ln15: teaches test circuit 403 performing a repair operation of the repair target memory package which is selected according to the test result. In addition, the test circuit 403 stores a status of the redundancy regions in the memory medium 30 and addresses of repair target regions in the memory medium 30. Selecting a target memory package and selecting addresses of repair target regions for repair is similar to locking target addresses); performing a second repair analysis of obtaining second fail information for the plurality of memory packages excluding the target address in the one or more fail addresses (Woo: (5): col1/ln55-col1/ln67: The built-in repair analysis (BIRA) circuit receive the fail information from the BIST circuit to select at least one of the plurality of memory packages as a repair target memory package. Woo: (5): col5/ln46-col6/ln15: teaches the test circuit 403 storing a status of the redundancy regions in the memory medium 30 and addresses of repair target regions in the memory medium 30. Woo performs repair analysis of plurality of memory packages which includes performing first/second/third and more repair analysis. Selecting addresses of repair target includes selecting first/second/third and more repair target regions and indicating each address is exclusive which is same as second address excluding first address, third address excluding first and second address and so on); and outputting a result of the first repair analysis and the second repair analysis (Woo: (5): col1/ln55-col1/ln67: teaches a test circuit where the test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. Woo: (35): col8/ln1-col8/ln21: teaches the RARFC circuit 423 transmitting information on the repair target memory packages and repair target addresses are output to the RA circuit 422 during the built-in repair analysis (BIRA) operation).
Regarding claim 36 Woo discloses: The method of claim 35, wherein selecting the target address comprises selecting the target address from among the one or more fail addresses based on the fail bit count (Woo: (54-55), col15/ln51-col16/ln42: teaches selecting a repair target memory package based on the numbers (fcn) of failed memory cells).
Regarding claim 37 Woo discloses: The method of claim 35, wherein selecting the target address comprises selecting, as the target address, a fail address having a least fail bit count from among the one or more fail addresses (Woo: (54-55), col15/ln51-col16/ln42: teaches memory packages having failed memory cells is selected as the repair target memory packages in order of the updated number (ufcn) of failed memory cells from the memory package having the smallest number (fcn) of failed memory cells.).
Regarding claim 38 Woo discloses: The method of claim 35, further comprising repairing the target address using an error correction code (ECC) (Woo: (6), col2/ln1-col2/ln17: teaches the module controller including an error correction code (ECC) circuit and a test circuit. The repair target memory package is selected by considering an error correction capability of the error correction code (ECC) circuit).
Regarding claim 39 Woo discloses: The method of claim 35, wherein outputting the result comprises repairing one or more first fail bits of the one or more fail addresses using an ECC (Woo: (28), col5/ln46-col6/ln15: teaches read data being outputted from the memory medium 30 are inputted to the ECC circuit 404 through the back physical layer 401-2 and the bidirectional multiplexer 406 and the ECC circuit 404 performing an ECC decoding operation of the read data to correct erroneous bits of the read data and outputting the corrected read data to the host 20).
Regarding claim 40 Woo discloses: The method of claim 39, wherein outputting the result further comprises repairing one or more second fail bits of the one or more fail addresses using redundant addresses (Woo: (34), col7/ln46-col7/ln67: teaches selecting the repair target memory packages involves the RA circuit 422 receiving address information of the redundancy regions of the memory packages to be repaired from the RARF 450 through the RARFC circuit 423. Woo: (35): col8/ln1-col8/ln21: teaches the RARFC circuit 423 transmitting information on the repair target memory packages and repair target addresses are output to the RA circuit 422 during the built-in repair analysis (BIRA) operation.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is recorded in pe2e_search_note.pdf and is attached as OA.APPENDIX.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD S HASAN whose telephone number is (571)270-1737 and email address is mohammad.hasan@uspto.gov. The examiner can normally be reached on Mon-Fri 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.S.H/Examiner, Art Unit 2138
/SHAWN X GU/
Primary Examiner, AU2138
Prosecution Insights