DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed June 25, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant's amendments to the claims have overcome the U.S.C. 102(a)(1) rejections previously set forth in the Non-Final Office Action mailed April 3, 2026.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,229,449 and U.S. Patent No. 11,762,582 in view of Hanson (US 2017/0109101), Eliash et al. (US 2020/0225856) as discussed in the detail in the Non-Final Rejection mailed April 3, 2026. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are anticipated by at least one claim set of each of the listed patents above.
In the event that any claim is not completely anticipated by at least one claim of a patent
above, the claims would still be rejected on the grounds of obvious nonstatutory double
patenting in further view of the prior art below that teaches or makes obvious that missing part,
and one of ordinary skill in the art could have incorporated such teachings prior to the effective
filings date of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hanson et al. and Eliash et al.
Regarding claim 1, Hanson et al. disclose:
A non-volatile dual in-line memory module (NVDIMM), comprising:
a first memory device configured to receive a command from a host (FIG. 2 step 201 Receive memory commands; FIG. 1 DRAM from-end cache 110; [0032] the memory controller 150 receives memory commands from the host computer 160 via the DRAM memory channel 155 (step 201); [0030] According to one embodiment, memory commands received via the DRAM memory channel 155 include a power-down command, a power-savings mode command, and a self-refresh command, amongst others. These commands can indicate the main controller 150 to perform device-internal maintenance functions and invoke flash-specific overhead-related procedures for the flash devices 141);
a controller coupled to the first memory device (FIG. 1 Main controller 150), wherein the controller comprises a time calculator (FIG. 5 tPD) configured to calculate a period of time for the first memory device to complete execution of the command from the host (FIG. 2 step 202 Low usage state; [0032] Based on the memory commands, the memory controller 150 can determine that the memory module 100 will enter into low usage state (step 202). For example, the memory controller 150 determines a period of inactivity or low usage…based on the receipt of a memory command indicating a future period of inactivity, such as a low-power state command; [0041] FIG. 5 shows an example for initiating SSD background tasks based on a power-down entry command, according to one embodiment. A power-down exit can be issued tPD after a power-down entry. At least during this idle time before the power down time tPD expires, the memory controller knows that no read or write commands are issued to the DRAM rank. The main controller 150 can initiate background SSD operations upon receiving the power-down entry command); and
a second memory device coupled to the controller and the first memory device (FIG. 1 Flash back-end storage 120), wherein the second memory device is configured to…perform the selected number of background operations (FIG. 2 step 203 Perform flash-specific overhead activities; [0032] When the memory controller 150 determines that there is no immediate activities or tasks to perform on the memory module 100, for example, memory reads or writes, the memory controller 150 can instruct the flash controller 140 to perform flash-specific overhead activities (step 203); [0041]).
Hanson et al. do not appear to explicitly teach “select a number of background operations from a plurality of background operations based on the calculated period of time.” However, Eliash et al. disclose:
select a number of background operations from a plurality of background operations based on the calculated period of time ([0044] controller 102 may be configured to determine the number of background management operations that need to be processed based on one or more factors, such as, utilization of the storage system, types of host commands, operational environment factors, voltage events of the storage system)
Hanson et al. and Eliash et al. are analogous art because Hanson et al. and Eliash et al. teach performing background operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanson et al. and Eliash et al. before him/her, to modify the teachings of Hanson et al. with the Eliash et al. teachings of background operations because determining the number of background operations to perform based on the calculated period of time facilitates the overall system power consumption minimization and memory latency reduction (Eliash et al. [0002]; [0014]).
Regarding claim 5, Hanson et al. further disclose:
The NVDIMM of claim 1, wherein the second memory device stops performing the number of background operations in response to the first memory device completing execution of the command ([0032] If DRAM commands are received by the memory controller 150 in step 201, the DRAM inactivity state is determined continuously and either continues to allow the initiation of SSD background tasks, or returns back to a SSD performance mode that deprioritize initiation of SSD background tasks).
Regarding claim 6, Hanson et al. further disclose:
The NVDIMM of claim 1, wherein the number of background operations include garbage collection ([0024] background tasks for the SSD can include, but are not limited to, garbage collection).
Regarding claim 7, Hanson et al. further disclose:
The NVDIMM of claim 6, wherein the garbage collection clears unused data from the second memory device ([0024] Garbage collection refers to a process for erasing garbage blocks with invalid and/or stale data of a flash memory for conversion into a writable state).
Regarding claim 8, Hanson et al. further disclose:
The NVDIMM of claim 1, wherein the second memory device is configured to perform the number of background operations based on the calculated period of time in response to detecting the command from the host (FIG. 2 step 203 Perform flash-specific overhead activities).
Regarding claim 9, Hanson et al. further disclose:
The NVDIMM of claim 1, wherein the second memory device is in an idle state prior to performing the number of background operations based on the calculated period of time ([0017] background tasks of the SSD such as garbage collection, wear leveling, and erase block preparation are performed during a presumed idle state of the memory module [0024] background tasks can take substantial amounts of time, and prevent the use of certain flash resources (reducing performance). Thus, scheduling these background tasks during an idle I/O period improves operational effectiveness; [0039] the memory module 100 has been in an idle state sufficiently long, the main controller 150 can trigger the flash controller 140 to perform background tasks of the flash devices 141).
Regarding claim 10, Hanson et al. disclose:
A non-volatile dual in-line memory module (NVDIMM), comprising:
a first memory device is configured to receive a command from a host (FIG. 2 step 201 Receive memory commands; FIG. 1 DRAM from-end cache 110; [0032] the memory controller 150 receives memory commands from the host computer 160 via the DRAM memory channel 155 (step 201); [0030] According to one embodiment, memory commands received via the DRAM memory channel 155 include a power-down command, a power-savings mode command, and a self-refresh command, amongst others. These commands can indicate the main controller 150 to perform device-internal maintenance functions and invoke flash-specific overhead-related procedures for the flash devices 141);
a controller coupled to the first memory device (FIG. 1 Main controller 150), wherein the controller comprises a time calculator (FIG. 5 tPD) configured to calculate a period of time for the first memory device to complete execution of the command from the host (FIG. 2 step 202 Low usage state; [0032] Based on the memory commands, the memory controller 150 can determine that the memory module 100 will enter into low usage state (step 202). For example, the memory controller 150 determines a period of inactivity or low usage…based on the receipt of a memory command indicating a future period of inactivity, such as a low-power state command; [0041] FIG. 5 shows an example for initiating SSD background tasks based on a power-down entry command, according to one embodiment. A power-down exit can be issued tPD after a power-down entry. At least during this idle time before the power down time tPD expires, the memory controller knows that no read or write commands are issued to the DRAM rank. The main controller 150 can initiate background SSD operations upon receiving the power-down entry command); and
a second memory device coupled to the controller and the first memory device (FIG. 1 Flash back-end storage 120), wherein the second memory device is configured to:
…perform the selected background operation (FIG. 2 step 203 Perform flash-specific overhead activities).
Hanson et al. do not appear to explicitly teach “select which background operation from a plurality of background operations to perform based on the calculated period of time.” However, Eliash et al. disclose:
select which background operation from a plurality of background operations to perform based on the calculated period of time ([0044] controller 102 may be configured to determine the number of background management operations that need to be processed based on one or more factors, such as, utilization of the storage system, types of host commands, operational environment factors, voltage events of the storage system);
The motivation for combining is based on the same rationale presented for rejection of independent claim 1.
Regarding claim 16, Hanson et al. disclose:
A method, comprising:
receiving a command at a first memory device from a host (FIG. 2 step 201 Receive memory commands; FIG. 1 DRAM from-end cache 110; [0032] the memory controller 150 receives memory commands from the host computer 160 via the DRAM memory channel 155 (step 201); [0030] According to one embodiment, memory commands received via the DRAM memory channel 155 include a power-down command, a power-savings mode command, and a self-refresh command, amongst others. These commands can indicate the main controller 150 to perform device-internal maintenance functions and invoke flash-specific overhead-related procedures for the flash devices 141);
calculating, via a time calculator (FIG. 5 tPD) of a controller coupled to the first memory device (FIG. 1 Main controller 150), a period of time for the first memory device to complete execution of the command from the host (FIG. 2 step 202 Low usage state; [0032] Based on the memory commands, the memory controller 150 can determine that the memory module 100 will enter into low usage state (step 202). For example, the memory controller 150 determines a period of inactivity or low usage…based on the receipt of a memory command indicating a future period of inactivity, such as a low-power state command; [0041] FIG. 5 shows an example for initiating SSD background tasks based on a power-down entry command, according to one embodiment. A power-down exit can be issued tPD after a power-down entry. At least during this idle time before the power down time tPD expires, the memory controller knows that no read or write commands are issued to the DRAM rank. The main controller 150 can initiate background SSD operations upon receiving the power-down entry command);
…performing the number of background operations at a second memory device (FIG. 2 step 203 Perform flash-specific overhead activities; [0032] When the memory controller 150 determines that there is no immediate activities or tasks to perform on the memory module 100, for example, memory reads or writes, the memory controller 150 can instruct the flash controller 140 to perform flash-specific overhead activities (step 203); [0041]).
Hanson et al. do not appear to explicitly teach “selecting what number of background operations to perform based on the calculated period of time” However, Eliash et al. disclose:
selecting what number of background operations to perform based on the calculated period of time ([0044] controller 102 may be configured to determine the number of background management operations that need to be processed based on one or more factors, such as, utilization of the storage system, types of host commands, operational environment factors, voltage events of the storage system); and
The motivation for combining is based on the same rationale presented for rejection of independent claim 1.
Regarding claim 17, Eliash et al. further disclose:
The method of claim 16, comprising performing the number of background operations by adjusting threshold voltages ([0037] background management operations include, but are not limited to threshold calibration operations performed to find optimal read voltages for one or more memory blocks of a non-volatile memory device).
Regarding claim 18, Hanson et al. further disclose:
The method of claim 16, comprising performing the number of background operations by performing a reconcile operation ([0024] device-internal maintenance functions and invoke flash-specific overhead-related procedures for the flash devices 141; [0029] device-internal maintenance functions such as garbage collection, wear leveling, and erase block preparation; [0030] device-internal maintenance functions and invoke flash-specific overhead-related procedures for the flash devices 141).
Regarding claim 19, Hanson et al. further disclose:
The method of claim 16, comprising completing execution of the command at the first memory device ([0032] If DRAM commands are received by the memory controller 150 in step 201, the DRAM inactivity state is determined continuously and either continues to allow the initiation of SSD background tasks, or returns back to a SSD performance mode that deprioritize initiation of SSD background tasks).
Regarding claim 20, Hanson et al. further disclose:
The method of claim 19, comprising stopping the number of background operations at the second memory device in response to the first memory device completing execution of the command ([0032] If DRAM commands are received by the memory controller 150 in step 201, the DRAM inactivity state is determined continuously and either continues to allow the initiation of SSD background tasks, or returns back to a SSD performance mode that deprioritize initiation of SSD background tasks).
Claims 2-4 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hanson et al. and Eliash et al. as applied to claim 1 above, and further in view of Kumar et al. (US 2016/0349817).
Regarding claim 2, Hanson et al. and Eliash et al. do not appear to explicitly teach while Kumar et al. disclose:
The NVDIMM of claim 1, further comprising a multiplexor configured to isolate the second memory device from the host ([0022] RDIMMs traditionally use passive multiplexers to isolate the internal bus on the memory devices from the host controller. In one embodiment, an RDIMM can be used for an NVDIMM implementation).
Hanson et al., Eliash et al., and Kumar et al. are analogous art because Hanson et al. and Eliash et al. teach performing background operations; and Kumar et al. teach a multiplexor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanson et al. and Kumar et al. before him/her, to modify the teachings of Hanson et al. with the Kumar et al. teachings of a multiplexor because implementing the multiplexor enables memory devices to be isolated from the host.
Regarding claim 2, Hanson et al. and Eliash et al. do not appear to explicitly teach while Kumar et al. disclose:
The NVDIMM of claim 1, further comprising a multiplexor configured to isolate the second memory device from the host ([0022] RDIMMs traditionally use passive multiplexers to isolate the internal bus on the memory devices from the host controller. In one embodiment, an RDIMM can be used for an NVDIMM implementation).
Regarding claim 3, the combination of Hanson et al., Eliash et al., and Kumar et al. further disclose:
The NVDIMM of claim 2, wherein the multiplexor is configured to isolate the second memory device from the host in response to detecting the command from the host to the first memory device ([0022] RDIMMs traditionally use passive multiplexers to isolate the internal bus on the memory devices from the host controller. In one embodiment, an RDIMM can be used for an NVDIMM implementation; It would be obvious to one skilled in the art before the effective filing date of the claimed invention, to configure the isolation of the second memory device "in response to" detecting the host command because doing so would ensure that the second memory device does not receive host commands while performing background operations).
Regarding claim 4, the combination of Hanson et al., Eliash et al., and Kumar et al. further disclose:
The NVDIMM of claim 2, wherein the second memory device is configured to perform the number of background operations in response to the multiplexor isolating the second memory device from the host ([0022] RDIMMs traditionally use passive multiplexers to isolate the internal bus on the memory devices from the host controller. In one embodiment, an RDIMM can be used for an NVDIMM implementation; It would be obvious to one skilled in the art before the effective filing date of the claimed invention, to configure the performance of the background operations "in response to" the isolation of the second memory device from the host because doing SO would ensure that the second memory device does not receive host commands while performing background operations).
Regarding claim 11, Hanson et al. and Eliash et al. do not appear to explicitly teach while Kumar et al. disclose:
The NVDIMM of claim 10, further comprising a multiplexor configured to isolate the second memory device from the host ([0022] RDIMMs traditionally use passive multiplexers to isolate the internal bus on the memory devices from the host controller. In one embodiment, an RDIMM can be used for an NVDIMM implementation).
The motivation for combining is based on the same rationale presented for rejection of claim 2.
Regarding claim 12, the combination of Hanson et al., Eliash et al., and Kumar et al. further disclose:
The NVDIMM of claim 11, wherein the multiplexor is configured to isolate the second memory device from the host in response to detecting the command from the host to the first memory device ([0022] RDIMMs traditionally use passive multiplexers to isolate the internal bus on the memory devices from the host controller. In one embodiment, an RDIMM can be used for an NVDIMM implementation; It would be obvious to one skilled in the art before the effective filing date of the claimed invention, to configure the isolation of the second memory device "in response to" detecting the host command because doing so would ensure that the second memory device does not receive host commands while performing background operations).
Regarding claim 13, the combination of Hanson et al., Eliash et al., and Kumar et al. further disclose:
The NVDIMM of claim 12, wherein the second memory device is configured to perform the selected background operation in response to the multiplexor isolating the second memory device from the host ([0022] RDIMMs traditionally use passive multiplexers to isolate the internal bus on the memory devices from the host controller. In one embodiment, an RDIMM can be used for an NVDIMM implementation; It would be obvious to one skilled in the art before the effective filing date of the claimed invention, to configure the performance of the background operations "in response to" the isolation of the second memory device from the host because doing SO would ensure that the second memory device does not receive host commands while performing background operations).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hanson et al. and Eliash et al. as applied to claim 11 above, and further in view of Kumar et al., and further in view of Yoon (US 2017/0277463).
Regarding claim 14, the combination of Hanson et al., Eliash et al., and Kumar et al. while Yoon discloses:
The NVDIMM of claim 12, comprising a register clock driver (RCD) coupled to the multiplexor ([0141] The command and the address of the controller 940 outputted from the command/address control logic 1420 are transferred to a register clock driver (RCD) 1440 through a multiplexer 1450. The register clock driver 1440 may buffer a command, an address and a clock provided from the memory controller 9 of the host or the controller 940 of the NVDIMM, and may provide the command, the address and the clock to first and second groups of volatile memory devices 911 to 914 and 921 to 924 through the control bus CMD/ADDR_BUS).
Hanson et al., Eliash et al., Kumar et al., and Yoon are analogous art because Hanson et al. and Eliash et al. teach performing background operations; Kumar et al. teach a multiplexor; and Yoon discloses operating NV-DIMMs.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanson et al., Eliash et al., Kumar et al., and Yoon before him/her, to modify the teachings of Hanson et al., Eliash et al., and Kumar et al. with Yoon's teachings of because a register clock driver (RCD) because implement the RCD coupled to the multiplexor enables buffer a command, an address, and a clock received from the memory controller of the host of the controller of the NVDIMM.
Regarding claim 15, Yoon further discloses:
The NVDIMM of claim 14, wherein the RCD is coupled to the controller ([0141]).
Response to Arguments
Applicant's arguments filed April 3, 2026 have been fully considered but they are not persuasive.
Applicant argues (Remarks pages 3-4) that Hanson et al. do not disclose “a period of time for the first memory device to complete execution of the command from the host” as required by claim 1. However, Hanson et al. teach at paragraph [0041] that the host sends a power-down entry command, which causes the memory controller to be idle for the period tPD. Therefore, the teachings of Hanson et al. disclose the limitation of claim 1.
Applicant further argues (Remarks page 4) that Hanson et al. do not disclose the amended claim 1 limitation “select a number of background operations from a plurality of background operations based on the calculated period of time.” However, as discussed above, this feature is disclosed by Eliash et al. at paragraph [0044].
Applicant further argues (Remarks page 4) that Hanson does not disclose a “first memory device” actively executing a command while a “second memory device” selects background operations based on the execution time of that command, since both the DRAM front-end cache 110 and the Flash back-end storage 120 of Hanson et al. are components of the memory module 100. However, the claimed first memory device and the claimed second memory device are components of the claimed non-volatile dual in-line memory module (NVDIMM) of claim 1. Therefore, Hanson’s teachings of the DRAM front-end cache and the Flash back-end storage, which are components of memory module 100 teach the limitations of the claim.
Applicant further argues that Hanson et al. do not disclose the limitations of claim 5. However, Hanson discloses at paragraph [0032] that the low power state is determined continuously. When the device is no longer in the low power state it stops performing the background tasks.
Applicant further argues that Eliash et al. do not disclose the claim 16 limitation of “selecting what number of background operations to perform based on the calculated period of time.” Eliash et al. disclose at paragraph [0044] that the number of background management operations may be determined based on one or more factors, including utilization of the storage system. The idle period of the memory controller taught by Hanson et al. corresponds to the Eliash et al. teachings of storage system utilization. Therefore, the combination of Hanson et al. in view of Eliash et al., as discussed supra, disclose the limitations of claim 16.
Therefore, the 35 U.S.C. 103 rejection of the claims over Hanson et al. and Eliash et al. is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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