DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities:
As to claim 3, the claim recites “a partially refreshed image”, which appears to be a typographical error. The Examiner suggests changing “a partially refreshed image” to “the partially refreshed image” to maintain antecedent basis with amended independent claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 & 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Amended independent claims 1 & 14 recites “a time sequence gating circuit couped to the time sequence control circuit”, which does not appear to be explicitly support in the as filed detailed specification or drawings.
For purposes of examination, the Examiner will be interpreting amended limitation of “a time sequence gating circuit couped to the time sequence control circuit” as written.
Response to Arguments
Applicant's arguments filed 7/13/2026 have been fully considered but they are not persuasive.
Regarding the rejection of claims 1, 4, & 14, the Applicant argues [Remarks: pg.], that “Lee does not disclose that the enable signal is generated based on a received partially refreshed image, nor that only a scanning signal corresponding to a partially refreshed image is sent to a corresponding pixel circuit for refreshing and display”.
The Office respectfully disagrees.
Refer to figures 3b-3c & 7 of Lee which teaches display frames with screen non-driving part [that does not require refreshing] and moving image reproduction part [that utilizes refreshing]. A gate output enable signal being enable signal via enable signal line 212, which is utilized to select gate lines that are utilized for outputting of scan signals for moving image reproduction part. The scan signal is applied to the corresponding gate line of the moving image reproduction part to refresh the pixel along the corresponding gate line of the moving image reproduction part. The utilization of the gate output enable signal being based on receiving a partially refreshed image [see figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89]. When there is no partially refreshed image, the usage of the gate output enable signal is not required because the entire frame would be refreshed.
Thus, Lee teaches the amended claim limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 & 9-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20170076683).
As to claim 1, Lee discloses a display drive chip [fig. 1 & para. 42] comprising:
a time sequence control circuit (gate control signal gcs, utilizing gate start pulse gsp & gate clock gclk, from timing controller 140) [para. 39 & 42-43] configured to provide a drive signal to a time sequence drive circuit (gate driver 120) [fig. 1 & para. 36] of a display (display device 100) [fig. 1] to enable the time sequence drive circuit to, based on the drive signal, output a scanning signal (scan signal output via plurality of gate lines gl1 to glg) [fig. 1 & para. 36] to a plurality of gate lines (gate lines gl1 to glg) [fig. 1 & para. 36] of the display; and
a time sequence gating circuit coupled to the time sequence control circuit (gate control signal gcs, utilizing gate output enable signal being enable signal via enable signal line 212 from timing controller 140) [fig. 4 para. 43 & 65-70] and configured to:
receive a partially refreshed image (driving area corresponding to moving image reproduction part & screen non-driving part) [figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89];
generate a gating signal (gate output enable signal being enable signal via enable signal line 212) [fig. 4 & para. 65-66 & 69] based on the partially refreshed image;
send the gating signal to a time sequence switch circuit (blocking unit 250) [fig. 4 & para. 65-70] of the display to enable the time sequence switch circuit to, based on the gating signal, connect the time sequence drive circuit to the gate lines (gate output enable signal being enable signal via enable signal line 212) [fig. 4 & para. 65-66 & 69] or disconnect the time sequence drive circuit from the gate lines [fig. 4 & para. 65-70],
wherein only a scanning signal corresponding to the partially refreshed image is sent to a corresponding pixel circuit of the display for refreshing and display [figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89].
As to claim 2, Lee discloses the display drive chip of claim 1, further comprising a channel drive circuit (data driver 130) [fig. 1 & para. 36] configured to separately provide a data signal to a plurality of data lines (data lines dl1 to dld) [fig. 1 & para. 36] of the display.
As to claim 3, Lee discloses the display drive chip of claim 2, wherein the channel drive circuit is further configured to generate the data signal to only drive a partially refreshed image [para. 61-63].
As to claim 4, Lee discloses a display [abstract] comprising:
a time sequence drive circuit (gate driver 120) [fig. 1 & para. 36] configured to provide a scanning signal (scan signal output via plurality of gate lines gl1 to glg) [fig. 1 & para. 36] based on a drive signal (gate control signal gcs, utilizing gate start pulse gsp & gate clock gclk, from timing controller 140) [para. 39 & 42-43];
a plurality of gate lines (gate lines gl1 to glg) [fig. 1 & para. 36]; and
a time sequence switch circuit (blocking unit 250) [fig. 4 & para. 65-70] configured to connect the time sequence drive circuit to the gate lines based on a gating signal (gate output enable signal being enable signal via enable signal line 212) [fig. 4 & para. 65-66 & 69] generated based on a received partially refreshed image (driving area corresponding to moving image reproduction part & screen non-driving part) [figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89] or disconnect the time sequence drive circuit from the gate lines based on the gating signal [fig. 4 & para. 65-70],
wherein only a scanning signal corresponding to the partially refreshed image is sent to a corresponding pixel circuit of the display for refreshing and display [figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89], and
wherein the time sequence switch circuit is connected between the time sequence drive circuit and a first gate line of the plurality of gate lines [fig. 4 & para. 65-70].
As to claim 5, Lee discloses the display of claim 4, wherein the time sequence drive circuit comprises a plurality of cascaded shift registers (shift register 260) [fig. 4 & para. 65], wherein a first cascaded shift register of the plurality of cascaded shift registers is connected to the first gate line (vg_out_1) [fig. 4], wherein the time sequence switch circuit comprises a plurality of switches (transistor t3) [fig. 4 & para. 65-70], and wherein a first switch, of the plurality of switches is connected between the first cascaded shift register and the first gate line (top transistor t3) [fig. 4].
As to claim 6, Lee discloses the display of claim 5, further comprising a gating control line configured to transmit the gating signal, wherein the gating control line is separately connected to control ends of the switches, wherein a first end of the first switch connected to an output end of the first cascaded shift register (transistor t3) [fig. 4 & para. 65-70], and wherein a second end of the first switch connected to the first gate line (transistor t3) [fig. 4 & para. 65-70].
As to claim 7, Lee discloses the display of claim 6, wherein the first switch is a thin-film transistor (TFT) [fig. 4 & para. 39].
As to claim 9, Lee discloses the display of claim 6, wherein the gating control line is configured to simultaneously input the gate signal to a control end of each switch [figs. 3a-3c & 7 & para. 57, 86-89, & 68-70].
As to claim 10, Lee discloses the display of claim 5, wherein the switches are all N-type transistors [fig. 4 & para. 39] or all P-type transistors.
As to claim 11, Lee discloses the display of claim 5, wherein the time sequence switch circuit is integrated into the time sequence drive circuit, or the time sequence switch circuit is located between the time sequence drive circuit and the gate lines [fig. 4 & para. 65-70].
As to claim 12, Lee discloses the display of claim 5, further comprising a plurality of data lines, wherein the data lines and the gate lines are disposed in a cross manner [fig. 1 & para. 8].
As to claim 13, Lee discloses the display of claim 12, further comprising a plurality of pixel circuits (panel 110 formed by active matrix formed by plurality of pixels) [fig. 1 & para. 8 & 36-37], wherein a pixel circuit [para. 8 & 36-37] of the pixel circuits is connected to a gate line [para. 8 & 36-37], of the gate lines, and wherein one column of the pixel circuits is connected to a data line of the data lines [para. 8 & 36-37].
As to claim 14, Lee discloses a display apparatus [abstract] comprising:
a display (display device 100) [fig. 1] comprising:
a time sequence drive circuit (gate driver 120) [fig. 1 & para. 36] configured to provide a scanning signal (scan signal output via plurality of gate lines gl1 to glg) [fig. 1 & para. 36] based on a drive signal (gate control signal gcs, utilizing gate start pulse gsp & gate clock gclk, from timing controller 140) [para. 39 & 42-43];
a plurality of gate lines (gate lines gl1 to glg) [fig. 1 & para. 36]; and
a time sequence switch circuit (blocking unit 250) [fig. 4 & para. 65-70] configured to connect the time sequence drive circuit to the gate lines based on a gating signal (gate output enable signal being enable signal via enable signal line 212) [fig. 4 & para. 65-66 & 69] or disconnect the time sequence drive circuit from the gate lines based on the gating signal [fig. 4 & para. 65-70]; and
a display drive chip (timing controller 140) [fig. 1 & para. 36 & 42] comprising:
a time sequence control circuit (gate control signal gcs, utilizing gate start pulse gsp & gate clock gclk, from timing controller 140) [para. 39 & 42-43] configured to provide the drive signal to the time sequence drive circuit [para. 39 & 42-43]; and
a time sequence gating circuit coupled to the time sequence control circuit (gate control signal gcs, utilizing gate output enable signal being enable signal via enable signal line 212 from timing controller 140) [fig. 4 para. 43 & 65-70] and configured to:
receive a partially refreshed image (driving area corresponding to moving image reproduction part & screen non-driving part) [figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89];
generate the gating signal (gate output enable signal being enable signal via enable signal line 212) [fig. 4 & para. 65-66 & 69] based on the partially refreshed image; and
send the gating signal (gate control signal gcs, utilizing gate output enable signal being enable signal via enable signal line 212 from timing controller 140) [fig. 4 para. 43 & 65-70] to the time sequence switch circuit,
wherein only a scanning signal corresponding to the partially refreshed image is sent to a corresponding pixel circuit of the display for refreshing and display [figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89].
As to claim 15, Lee discloses the display apparatus of claim 14, wherein the display is an organic light-emitting diode (OLED) display [para. 38].
As to claim 16, Lee discloses the display apparatus of claim 15, wherein the OLED display comprises a pixel circuit comprising:
a light-emitting device (LED) (oled) [para. 38]; and
a plurality of transistors configured to drive the LED [para. 38].
As to claim 17, Lee discloses the display apparatus of claim 14, wherein the display is a liquid-crystal diode (LCD) display [para. 37].
As to claim 18, Lee discloses the display apparatus of claim 14, wherein when only a partial refresh of an image is needed, the display is configured to divide the display into a plurality of display areas that refresh at different frame rates [fig. 7].
As to claim 19, Lee discloses the display apparatus of claim 18, wherein a first image in a first frame is refreshed in full screen [para. 56 & fig. 3a].
As to claim 20, Lee discloses the display apparatus of claim 19, wherein the display areas comprise a first display area (area corresponding to moving image reproduction part) [figs. 3a-3c & 7] and a second display area (area corresponding to screen non-driving part) [figs. 3a-3c & 7], wherein, in a second frame [fig. 3b & 7 & para. 57 & 86-89], the display is configured to perform a partial refresh in the first display area (moving image reproduction part) [fig. 3b & 7 & para. 57 & 86-89], and wherein time frequency switch circuit is configured to shield the second display area from being refreshed (non-driving part, enable signal turns on transistor t3 & blocks output of to gate lines) [fig. 3b-4 & 7 & para. 57, 86-89, & 68-70].
As to claim 21, Lee discloses the display drive chip of claim 1, wherein the time sequence gating circuit is further configured to generate a line-level selection signal as the gating signal, using a line of pixel circuits of the display as a unit, to implement line-level partial refresh of the display (number of gate lines can be freely changed corresponding to size of desired driving area) [figs. 3b-3c & 7 & para. 57, 59, 61-63, & 86-89].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
You et al. (US 20130293529).
Wang et al. (US 20160042707).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at (571)-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID TUNG/Primary Examiner, Art Unit 2622
Prosecution Insights