DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are canceled.
Claims 21-40 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-28, 30-33, 36-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,235,757. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the listed claims of the instant application are anticipated by the claims of the patent. For example, as for claim 21, the only difference from the claims of the patent is that the data bits generated by combining the second data bits, which is formed by combining the first data bits and the CABIB, with the parity bits is the third data bits. However, the claims of the patent recite command address signal is generated using first data bits, CABIB and a parity bit. Therefore, the command address signal recited in the patent anticipates the third data bits.
Allowable Subject Matter
Claims 21-40 are allowable if terminally disclaimed to overcome the nonstatutory double patenting rejection set forth in this office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PG Pub. 2023/0,315,573 A1 discloses a method for incorporating a parity bit in a command address bus to detect an error in any of the read and/or write command reaches a dual inline memory module.
PG Pub. 2020/0,111,519 A1 discloses a semiconductor device with an access control circuit that receives an address signal indicating an address of at least one of the memory cells to be accessed and a command signal indicating an access type, and accessing the memory cell array based on the address signal and the command signal. The access control circuit verifies the address signal and the command signal based on a verification signal supplied from outside.
PG Pub. 2017/0,004,035 A1 discloses a method of memory array and link error correction in a low power memory sub-system includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.
PG Pub. 2014/0,089,755 A1 discloses method for detecting/correcting memory errors when receiving a command and an address associated with a data transaction by also receiving parity information associated with the command/address and locking a data array of a memory device in response to detecting a parity error.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAE M KO whose telephone number is (571)270-3886. The examiner can normally be reached M-F 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAE M KO/Primary Examiner, Art Unit 2114
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