Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 21-40 of copending Application No. 18/774305. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following observation.
Instant Application 19/028436
copending Application 18/774,305
21. A system on a chip (SoC), comprising: one or more processors; and secure processor circuitry that includes an internal processor, memory, and a plurality of cryptographic accelerator circuits isolated from the one or more processors, wherein the secure processor circuitry is configured to: receive, from a source external to the secure processor circuitry, a request to provide one of a plurality of secure services implemented by the secure processor circuitry using the cryptographic accelerator circuits; perform an authentication of the external source; and based on the authentication, provide the requested secure service using one or more of the cryptographic accelerator circuits.
21. (New) A system on a chip (SoC), comprising: one or more processors; and a security circuit that includes an internal processor, a read-only memory (ROM), and a cryptographic accelerator circuit isolated from the one or more processors, wherein the security circuit is configured to: boot the security circuit using boot code stored in the ROM and executed by the internal processor; and perform, via the cryptographic accelerator circuit, a public-key cryptographic operation responsive to a service request associated with the one or more processors, wherein performance of the public-key cryptographic operation includes accessing key material stored in an internal memory of the cryptographic accelerator circuit.
22. The SoC of claim 21, wherein one of the cryptographic accelerator circuits includes: a public key accelerator (PKA) circuit configured to perform a public-key cryptographic operation responsive to a service request associated with the one or more processors.
22. (New) The SoC of claim 21, further comprising: a memory controller external to the security circuit and accessible to the one or more processors; and wherein the internal processor is configured to load software from an external memory controlled by the external memory controller.
23. The SoC of claim 22, wherein the public-key cryptographic operation includes an elliptical-curve Diffie-Hellman (ECDH) operation.
23. (New) The SoC of claim 22, wherein the security circuit is configured to verify the software prior to the internal processor executing the software.
24. The SoC of claim 22, wherein the public-key cryptographic operation includes a digital signature operation.
24. (New) The SoC of claim 21, wherein the cryptographic accelerator is circuit configured to perform the cryptographic operation responsive to a request issued by the internal processor.
25. The SoC of claim 22, wherein the public-key cryptographic operation includes an encryption operation or a decryption operation.
25. (New) The SoC of claim 21, wherein the public-key cryptographic operation includes an elliptical-curve Diffie-Hellman (ECDH) operation.
26. The SoC of claim 21, wherein one of the cryptographic accelerator circuits includes: a random number generator (RNG) circuit configured to generate random numbers for the secure processor circuitry.
26. (New) The SoC of claim 21, wherein the public-key cryptographic operation includes a digital signature operation.
27. The SoC of claim 21, wherein one of the cryptographic accelerator circuits includes: a hash circuit configured to implement a secure hash algorithm (SHA).
27. (New) The SoC of claim 21, wherein the public-key cryptographic operation includes an encryption operation or a decryption operation.
28. The SoC of claim 21, wherein one of the cryptographic accelerator circuits is configured to generate one or more cryptographic keys.
28. (New) The SoC of claim 21, wherein the security circuit includes a random number generator (RNG) circuit configured to generate random numbers for the security circuit.
29. The SoC of claim 21, wherein the authentication includes a digital signature verification.
29. (New) The SoC of claim 21, wherein the security circuit includes programable fuses configured to store key material accessible to the cryptographic accelerator circuit.
30. The SoC of claim 21, wherein the memory includes read-only memory (ROM) configured to store key material accessible to one or more of cryptographic accelerator circuits.
30. (New) The SoC of claim 21, wherein the security circuit includes a hash circuit configured to implement a secure hash algorithm (SHA).
31. A device, comprising: an integrated circuit that includes one or more processors and secure processor circuitry having an internal processor, memory, and a plurality of cryptographic acceleration circuits isolated from the one or more processors, wherein the secure processor circuitry is configured to: perform an authentication of an entity external to the secure processor circuitry; receive, from the external entity, a request for one of a plurality of secure services implemented by the secure processor circuitry using the cryptographic accelerator circuits; and based on the authentication, provide a result from performing the requested secure service.
31. (New) A device, comprising: an integrated circuit that includes one or more processors and a security circuit having an internal processor, a read-only memory (ROM), and cryptographic accelerator circuit isolated from the one or more processors, wherein the security circuit is configured to: boot the security circuit via the internal processor executing boot code stored in the ROM; receive a service request associated with the one or more processors; and perform, via the cryptographic accelerator circuit, a public-key cryptographic operation responsive to the service request, wherein performance of the public-key cryptographic operation includes accessing key material stored in an internal memory of the cryptographic accelerator circuit.
32. The device of claim 31, wherein one of the cryptographic accelerator circuits includes: a public key accelerator (PKA) circuit configured to perform a public-key cryptographic operation.
32. (New) The device of claim 31, further comprising: memory external to security circuit and accessible to the one or more processors; and wherein the internal processor is configured to load data from the external memory.
33. The device of claim 32, wherein, to perform the authentication of the external entity, the PKA circuit is configured to verify a digital signature associated with the external entity.
33. (New) The device of claim 32, wherein the loaded data includes program instructions executable by the internal processor.
34. The device of claim 32, wherein the PKA circuit is configured to generate the provided result.
34. (New) The device of claim 33, wherein the security circuit is configured to authenticate the program instructions prior to the internal processor executing the program instructions.
35. The device of claim 32, wherein, to perform a public-key cryptographic operation, the PKA circuit is configured to access key material stored in an internal memory of the PKA circuit.
35. (New) The device of claim 31, wherein the integrated circuit is a system on a chip (SoC).
39. A method, comprising: receiving, at secure processor circuitry in a system on a chip (SoC), a request for one of a plurality of secure services supported by the secure processor circuitry, wherein the secure processor circuitry that includes an internal processor, memory, and a plurality of cryptographic accelerator circuits isolated from one or more processors included in the SoC and external to the secure processor circuitry; performing, by the secure processor circuitry, an authentication of a source of the request, wherein the source is external to the secure processor circuitry; and based on the authentication, providing, by the secure processor circuitry, the requested secure service using one or more of the cryptographic accelerator circuits.
36. (New) One or more non-transitory computer readable media having program instructions stored therein that are executable by a device to perform operations comprising: booting a security circuit of the device, wherein the booting includes an internal processor of the security circuit executing boot code stored in a read-only memory (ROM) included in the security circuit; receiving, by the security circuit and from a processor external to the security circuit, a request for performance of a cryptographic operation; and performing, by a cryptographic accelerator circuit included in the security circuit and isolated from the external processor, the cryptographic operation, wherein performance of the cryptographic operation includes accessing key material stored in an internal memory of the cryptographic accelerator circuit.
37. (New) The computer readable media of claim 36, wherein the computer readable media include the ROM.
38. (New) The computer readable media of claim 36, wherein the computer readable media include a memory external to the security circuit and having program instructions executable by the internal processor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buer et al (2014/0233732) in views of Hartley et al (2014/0164779).
For claim 21. Buer teaches a system on a chip (SoC) (Buer teaches that system-on-a-chip (SoC) in abstract), comprising: one or more processors (Buer teaches that the processing unit of some devices may have multiple processors or processing cores in order to provide higher performance and/or multi-tasking capabilities as Buer teaches in par.15); and secure processor circuitry that includes an internal processor, memory, and a plurality of cryptographic accelerator circuits isolated from the one or more processors (Buer teaches that Designing the SPS of an eSE in accordance with various embodiments may entail completely designing the SPS in a secure facility as a hard macro that includes Cryptographic processing engine(s) 545 meaning more than one which includes accelerators for encryption/cryptographic operations, processors that separated or segregated of different applications and/or tasks running on different processors helps to ensure that one application does not interfere with the execution of another as Buer teaches in par.15 and 79 and figure 5), wherein the secure processor circuitry is configured to: receive, from a source external to the secure processor circuitry, a request to provide one of a plurality of secure services implemented by the secure processor circuitry using the cryptographic accelerator circuits (Buer teaches that the PPS 420 may utilize a processor 225 (e.g., a Cortex-MO processor) (which is external source) for execution of interface driver code in a hardware isolated environment, such as the eSE 404. The processor 425 may request secure services from the hard macro SPS 405 (which is secure processor circuitry), and may be responsible for moving data to/from peripheral interfaces from/to an IO shared memory space in static random access memory (SRAM) of the hard macro SPS 405 as Buer teaches in par.59).
Buer teaches of using seeking secure service which is part of the authentication but Buer fails to explicitly teach perform an authentication of the external source; and based on the authentication, provide the requested secure service using one or more of the cryptographic accelerator circuits.
Hartley teaches, similar system, perform an authentication of the external source; and based on the authentication, provide the requested secure service using one or more of the cryptographic accelerator circuits (Hartley teaches that The secure boot logic 326 can be configured to copy secret values to the private key derivation logic 328 and activate confidentiality protection on copied secret values and the private key register 312, copy chip-unique IDs 348 and the trust anchor 444 to the message tag logic 350 and activate protection on the message tag register 316, and authenticate off-chip software using the trust anchor 444, thereby preventing use of the message signing logic 310 unless the off-chip software is authenticated and contains the correct capability token for authorizing use and capability of the software as Hartley teaches in par.55, and 59-61). It would would have been obvious to one ordinary skill in the art before effective filling date to modify Buer to include perform an authentication of the external source; and based on the authentication, provide the requested secure service using one or more of the cryptographic accelerator circuits as taught and suggested by Hartley for the purpose of enforcing the constraints expressed in the trust anchor's associated data and authenticating the chips and for verifying that the chip's immutable value is in fact the OEM trust anchor (Hartley, par.57).
For claim 22, Buer, as modified by Hartley, further teaches that wherein one of the cryptographic accelerator circuits includes: a public key accelerator (PKA) circuit configured to perform a public-key cryptographic operation responsive to a service request associated with the one or more processors (Buer teaches that cryptographic acceleration using a dedicated public key accelerator (PKA) module as Buer teaches in par.80).
For claim 23, Buer, as modified by Hartley, further teaches that wherein the public-key cryptographic operation includes an elliptical-curve Diffie-Hellman (ECDH) operation (Buer teaches in par.84).
For claim 24, Buer, as modified by Hartley, further teaches that wherein the public-key cryptographic operation includes a digital signature operation (Buer teaches in par.84).
For claim 25, Buer, as modified by Hartley, further teaches that wherein the public-key cryptographic operation includes an encryption operation or a decryption operation (Buer teaches in par.79-80).
For claim 26, Buer, as modified by Hartley, further teaches that wherein one of the cryptographic accelerator circuits includes: a random number generator (RNG) circuit configured to generate random numbers for the secure processor circuitry (Buer teaches in par.77).
For claim 27, Buer, as modified by Hartley, further teaches that wherein one of the cryptographic accelerator circuits includes: a hash circuit configured to implement a secure hash algorithm (SHA) (Buer teaches in par.79).
For claim 28, Buer, as modified by Hartley, further teaches that wherein one of the cryptographic accelerator circuits is configured to generate one or more cryptographic keys (Buer teaches in par.79-80).
For claim 29, Buer, as modified by Hartley, further teaches that wherein the authentication includes a digital signature verification (Buer teaches in par.84).
For claim 30, Buer, as modified by Hartley, further teaches that wherein the memory includes read-only memory (ROM) configured to store key material accessible to one or more of cryptographic accelerator circuits (Buer teaches in par.76).
For claim 31. Buer teaches A device (abstract), comprising: an integrated circuit that includes one or more processors (Buer teaches that the processing unit of some devices may have multiple processors or processing cores in order to provide higher performance and/or multi-tasking capabilities as Buer teaches in par.15) and secure processor circuitry having an internal processor, memory, and a plurality of cryptographic acceleration circuits isolated from the one or more processors (Buer teaches that Designing the SPS of an eSE in accordance with various embodiments may entail completely designing the SPS in a secure facility as a hard macro that includes Cryptographic processing engine(s) 545 meaning more than one which includes accelerators for encryption/cryptographic operations, processors that separated or segregated of different applications and/or tasks running on different processors helps to ensure that one application does not interfere with the execution of another as Buer teaches in par.15 and 79 and figure 5), wherein the secure processor circuitry is configured to: receive, from the external entity, a request for one of a plurality of secure services implemented by the secure processor circuitry using the cryptographic accelerator circuits (Buer teaches that the PPS 420 may utilize a processor 225 (e.g., a Cortex-MO processor) (which is external source) for execution of interface driver code in a hardware isolated environment, such as the eSE 404. The processor 425 may request secure services from the hard macro SPS 405 (which is secure processor circuitry), and may be responsible for moving data to/from peripheral interfaces from/to an IO shared memory space in static random access memory (SRAM) of the hard macro SPS 405 as Buer teaches in par.15 and 59).
Buer teaches of using seeking secure service which is part of the authentication but Buer fails to explicitly teach perform an authentication of an entity external to the secure processor circuitry; and based on the authentication, provide a result from performing the requested secure service.
Hartley teaches, similar system, perform an authentication of an entity external to the secure processor circuitry; and based on the authentication, provide a result from performing the requested secure service (Hartley teaches that The secure boot logic 326 can be configured to copy secret values to the private key derivation logic 328 and activate confidentiality protection on copied secret values and the private key register 312, copy chip-unique IDs 348 and the trust anchor 444 to the message tag logic 350 and activate protection on the message tag register 316, and authenticate off-chip software using the trust anchor 444, thereby preventing use of the message signing logic 310 unless the off-chip software is authenticated and contains the correct capability token for authorizing use and capability of the software as Hartley teaches in par.55, and 59-61). It would would have been obvious to one ordinary skill in the art before effective filling date to modify Buer to include perform an authentication of the external source; and based on the authentication, provide the requested secure service using one or more of the cryptographic accelerator circuits as taught and suggested by Hartley for the purpose of enforcing the constraints expressed in the trust anchor's associated data and authenticating the chips and for verifying that the chip's immutable value is in fact the OEM trust anchor (Hartley, par.57).
For claim 32, Buer, as modified by Hartley, further teaches that wherein one of the cryptographic accelerator circuits includes: a public key accelerator (PKA) circuit configured to perform a public-key cryptographic operation (Buer teaches that cryptographic acceleration using a dedicated public key accelerator (PKA) module as Buer teaches in par.80).
For claim 33, Buer, as modified by Hartley, further teaches that wherein, to perform the authentication of the external entity, the PKA circuit is configured to verify a digital signature associated with the external entity (Buer teaches that cryptographic acceleration using a dedicated public key accelerator (PKA) module as Buer teaches in par.80 and 84).
For claim 34, Buer, as modified by Hartley, further teaches that wherein the PKA circuit is configured to generate the provided result (Buer teaches in par.79-80).
For claim 35, Buer, as modified by Hartley, further teaches that wherein, to perform a public-key cryptographic operation, the PKA circuit is configured to access key material stored in an internal memory of the PKA circuit (Buer teaches in par.76-80).
For claim 36, Buer, as modified by Hartley, further teaches that wherein the integrated circuit further includes: a memory controller external to the secure processor circuitry and accessible to the one or more processors; and wherein the internal processor is configured to load software from an external memory controlled by the external memory controller (Buer teaches in par.75-80).
For claim 37, Buer, as modified by Hartley, further teaches that wherein the security circuit includes programable fuses configured to store key material accessible to one or more of the cryptographic acceleration circuits (Buer teaches in par.75-80).
For claim 38, Buer, as modified by Hartley, further teaches that wherein the integrated circuit is a system on a chip (SoC) (Buer teaches in abstract).
For claim 39. Buer teaches A method (abstract), comprising: receiving, at secure processor circuitry in a system on a chip (SoC) (abstract), a request for one of a plurality of secure services supported by the secure processor circuitry (Buer teaches that the PPS 420 may utilize a processor 225 (e.g., a Cortex-MO processor) (which is external source) for execution of interface driver code in a hardware isolated environment, such as the eSE 404. The processor 425 may request secure services from the hard macro SPS 405 (which is secure processor circuitry), and may be responsible for moving data to/from peripheral interfaces from/to an IO shared memory space in static random access memory (SRAM) of the hard macro SPS 405 as Buer teaches in par.59), wherein the secure processor circuitry that includes an internal processor, memory, and a plurality of cryptographic accelerator circuits isolated from one or more processors included in the SoC and external to the secure processor circuitry (Buer teaches that Designing the SPS of an eSE in accordance with various embodiments may entail completely designing the SPS in a secure facility as a hard macro that includes Cryptographic processing engine(s) 545 meaning more than one which includes accelerators for encryption/cryptographic operations, processors that separated or segregated of different applications and/or tasks running on different processors helps to ensure that one application does not interfere with the execution of another as Buer teaches in par.15 and 79 and figure 5 and abstract); wherein the source is external to the secure processor circuitry (Buer teaches in par.15 and abstract).
Buer teaches of using seeking secure service which is part of the authentication but Buer fails to explicitly teach performing, by the secure processor circuitry, an authentication of a source of the request and based on the authentication, providing, by the secure processor circuitry, the requested secure service using one or more of the cryptographic accelerator circuits.
Hartley teaches, similar system, performing, by the secure processor circuitry, an authentication of a source of the request and based on the authentication, providing, by the secure processor circuitry, the requested secure service using one or more of the cryptographic accelerator circuits (Hartley teaches that The secure boot logic 326 can be configured to copy secret values to the private key derivation logic 328 and activate confidentiality protection on copied secret values and the private key register 312, copy chip-unique IDs 348 and the trust anchor 444 to the message tag logic 350 and activate protection on the message tag register 316, and authenticate off-chip software using the trust anchor 444, thereby preventing use of the message signing logic 310 unless the off-chip software is authenticated and contains the correct capability token for authorizing use and capability of the software as Hartley teaches in par.55, and 59-61). It would would have been obvious to one ordinary skill in the art before effective filling date to modify Buer to include perform an authentication of the external source; and based on the authentication, provide the requested secure service using one or more of the cryptographic accelerator circuits as taught and suggested by Hartley for the purpose of enforcing the constraints expressed in the trust anchor's associated data and authenticating the chips and for verifying that the chip's immutable value is in fact the OEM trust anchor (Hartley, par.57).
For claim 40, Buer, as modified by Hartley, further teaches that wherein the authentication includes verifying a digital signature associated with the source and using one of the cryptographic accelerator circuits (Buer teaches in par.79-80 and 84).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYUB A MAYE whose telephone number is (571)270-5037. The examiner can normally be reached Monday-Friday 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SHEWAYE GELAGAY can be reached at 571-272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AYUB A MAYE/Examiner, Art Unit 2436
/TRONG H NGUYEN/Primary Examiner, Art Unit 2436
Prosecution Insights