DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Information Disclosure Statement
The references cited in the information disclosure statement (IDS) submitted on 1/17/25, 1/23/25, and 02/26/25 have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1- 7, 11-17 are rejected under 35 U.S.C. 102(a)(1)(a)(2) as being anticipated by Ha et. al., U.S Patent Pub No. 20190146911 (hereinafter Ha).
Regarding Claim 1, Ha teaches a memory control device comprising: a controller configured to provide meta data in accordance with normal data being stored in a non-volatile memory device(Fig.1,3,11; Para7-9 "In accordance with an embodiment, a memory system may include a buffer memory storing a plurality of meta-slices constituting meta-data, and a memory controller marking meta-slices being updated, an10ng the plurality of meta-slices stored in the buffer memory, as dirty meta-slices, generating journal data including update information corresponding to the dirty meta-slices, and flushing the journal data together with one of the dirty meta-slices to a nonvolatile memory device" Para33-35) ; and
a buffer memory configured to store multiple slices configuring the meta data (Fig.10-12,19; Para7-9 "In accordance with an embodiment, a method of operating a memory system may include loading a plurality of meta-slices constituting meta-data into a buffer memory" Para102-103), wherein the controller is configured to: update in the buffer memory, or writes in the non-volatile memory device, one or more slices among the multiple slices, and enable updating the one or more slices in the buffer memory while writing the one or more slices in the non-volatile memory device (Fig.14,15; Para8-9 "updating a meta-slice map including information on physical addresses storing dirty meta-slices flushed together with the journal entries, updating a journal replay context including index information on the dirty meta-slices flushed together with the journal entries, and flushing an updated meta-slice map and an updated journal replay context to the non-volatile memory device." Para109-112, 129-130, 134-136).
Regarding claim 2, Ha teaches all the limitations of the base claims as outlined above.
Further, Ha teaches wherein the controller is configured to change state information for the one or more slices based on whether the one or more slices are updated, written, or both updated and written, wherein the state information for one or more slices is stored in the buffer memory(Fig.11-13; Para8-9, 127-130 "The memory controller 1200 may mark the updated meta-slice of the buffer memory device 1300 or the memory buffer 720 as a dirty meta-slice, flush the dirty meta-slice to the non-volatile memory device 1100, and change the dirty meta-slice into a clean meta-slice").
Regarding claim 3, Ha teaches all the limitations of the base claims as outlined above.
Further, Ha teaches wherein the state information indicates one of four states including a clean state, a first dirty state, a second dirty state, and a third dirty state(Fig.11-13; Para8-9, 127-130 "clean meta-slices" "dirty meta-slices").
Regarding claim 4, Ha teaches all the limitations of the base claims as outlined above.
Further, Ha teaches wherein the controller is configured to: change the state information from the clean state to the first dirty state, or from the second dirty state to the third dirty state, when the one or more slices are updated in the buffer memory, and change the state information from the first dirty state to the second dirty state, or from the second dirty state to the clean state, or from the third dirty to the second dirty state, when the one or more slices are written in the non-volatile memory device( Fig.11-13; Para8-9, 127-130 "The memory controller 1200 may mark the updated meta-slice of the buffer memory device 1300 or the memory buffer 720 as a dirty meta-slice, flush the dirty meta-slice to the non-volatile memory device 1100, and change the dirty meta-slice into a clean meta-slice").
Regarding claim 5, Ha teaches all the limitations of the base claims as outlined above.
Further, Ha teaches wherein the state information consist of 2-bit data (Fig.11-13; Para8-9, 127-130).
Regarding claim 6, Ha teaches all the limitations of the base claims as outlined above.
Further, Ha teaches wherein the controller is configured to: generate first journal data comprising updated information on the one or more slices and store the first journal data in the buffer memory, write the one or more slices of first to third dirty state when the one or more slices of first to third dirty state are present in a state in which the first journal data has a size smaller than a set size, flush the first journal data by changing the first journal data into journal retention data when the first journal data has the set size, and generate second journal data comprising update information on the one or more slices after the flushing of the first journal retention data is started, and store the second journal data in the buffer memory (Fig.11-14,17; Para130-132 "First, referring to FIGS. 11 and 14, when journal data are generated to a predetermined size, the memory controller 1200 may generate a journal entry and store the journal entry in the buffer memory device 1300 or the memory buffer 720." Para158-165).
Regarding claim 7, Ha teaches all the limitations of the base claims as outlined above.
Further, Ha teaches wherein the second journal data is stored in a different location in the buffer memory than the location at which the journal retention data is stored in the buffer memory (Fig.11-14; Para130-132 "First, referring to FIGS. 11 and 14, when journal data are generated to a predetermined size, the memory controller 1200 may generate a journal entry and store the journal entry in the buffer memory device 1300 or the memory buffer 720.").
Regarding claims 11-17, Ha teaches these claims according to the reasoning set forth in claim 1-7.
Allowable Subject Matter
Claims 8-10 and 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, including the reference(s) cited below, neither anticipates, nor renders obvious the recited combination as a whole; including at least the limitations of : “wherein the controller writes one or more slices of first to third dirty state in a state in which the first journal data has a size smaller than a set size by: moving the one or more slices of first to third dirty state to a reserved space of the buffer memory, and writing, when flushing the journal retention data, the one or more slices of first to third dirty state moved to the reserved space together with the journal retention data in the non-volatile memory device.”
Conclusion
The prior art made of record , listed on form PTO-892, and not relied upon, if any, is considered pertinent to applicant's disclosure.
Cho et.al. US20190146910 teaches mapping using segmented meta information table.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135