DETAILED ACTION
1. This Office Action is taken in response to Applicants’ application 19/028,547 filed on 1/17/2025.
Claims 1-20 are pending for consideration.
2. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Objections
3. Claims 14-19 are objected to because of the following informalities:
Claim 14 is objected to because line 4 of claim 14 recites “a first memory cell array comprising plurality of first cells …” it should be “a first memory cell array comprising a plurality of first cells …”
Line 10 of claim 14 recites “wherein each of the plurality of second cell is smaller in size than each of the plurality of first cells.” It should be “wherein each of the plurality of second cells is smaller in size than each of the plurality of first cells.”
Appropriate correction is required.
Claims 15-19 are objected to by virtue of their dependency from claim 14.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
4, Claims 14-19 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 14 recites “a number of the plurality of second cells is less than a number of the plurality of first cells,” and “each of the plurality of second cell is smaller in size than each of the plurality of first cells.” Thus, the size of a second cell is smaller than that of a first cell, and the number of second cells is also less than the number of first cells.
However, according to Paragraph [0050] of the Specification of the current Application, a cell of smaller size would result in larger number of cells in a unit area: “Since the SRAM cell includes more transistors than a DRAM cell, it is larger in physical size than a DRAM cell. The second memory cell array MCA2, which includes the SRAM cell larger than the DRAM cell in size, may have less cells per unit area than the first memory cell array MCA1 including the DRAM cell. Since the number of cells in the first memory cell array MCA1 is greater than the number of cells in the second memory cell array MCA2 within the same or similar area, the degree of integration of the first memory cell array MCA1 may be higher than the degree of integration of the second memory cell array MCA2. In other words, more data may be stored in first memory cell array MCA1 than in second memory cell array MCA2.”
Therefore, the two limitations “a number of the plurality of second cells is less than a number of the plurality of first cells,” and “each of the plurality of second cell is smaller in size than each of the plurality of first cells” appear to be contradictory to the descriptions stated in Paragraph [0050] of the Specification of the current Application. As such, they lack the support by the written descriptions of the Specification of the current Application.
Clarifications/corrections are needed.
Claims 15-19 are rejected by virtue of their dependency from claim 14.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claims 14-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 recites “a number of the plurality of second cells is less than a number of the plurality of first cells,” and “each of the plurality of second cell is smaller in size than each of the plurality of first cells.” Thus, the size of a second cell is smaller than that of a first cell, and the number of second cells is also less than the number of first cells.
Therefore, the two limitations “a number of the plurality of second cells is less than a number of the plurality of first cells,” and “each of the plurality of second cell is smaller in size than each of the plurality of first cells,” when combined together, appear to suggest that memory cells of smaller size actually lead to fewer number of memory cells compared with memory cells of larger size, based on the same size of the memory area. This is apparently against physics laws.
Further, claim 15 recites “The semiconductor memory device of claim 14, wherein each of the plurality of first cells comprises a DRAM cell, and wherein each of the plurality of second cells comprises an SRAM cell.”
However, claim 15 depends from claim 14, which recites “wherein each of the plurality of second cell is smaller in size than each of the plurality of first cells.” Thus, when these two limitations are taken into consideration together, it appears to require that the size of SRAM cells to be smaller than that of the DRAM cells. This is contrary to the well-known fact that “the size of SRAM cells to be larger than that of the DRAM cells.”
For example, Paragraph [0050] of the Specification of the current Application states “Since the SRAM cell includes more transistors than a DRAM cell, it is larger in physical size than a DRAM cell. The second memory cell array MCA2, which includes the SRAM cell larger than the DRAM cell in size, may have less cells per unit area than the first memory cell array MCA1 including the DRAM cell. Since the number of cells in the first memory cell array MCA1 is greater than the number of cells in the second memory cell array MCA2 within the same or similar area, the degree of integration of the first memory cell array MCA1 may be higher than the degree of integration of the second memory cell array MCA2. In other words, more data may be stored in first memory cell array MCA1 than in second memory cell array MCA2.”
Thus, there is inconsistency between the “first cells” and “second cells” recited in claim 14, and the “DRAM cell” and “SRAM cell” recited in claim 15 that must be resolved.
Clarifications/corrections are needed.
Claims 15-19 are rejected by virtue of their dependency from claim 14.
Double Patenting – with a Second Reference
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
7. Claims 1-8, and 14-20 are provisionally rejected under the judicially created doctrine of obvious-type double patenting as being unpatentable over independent claims 1-20 of US Patent Application 18/982,194, and in view of Peled et al. (US Patent Application Publication 2015/0215226, hereinafter Peled).
Although not all of the limitations of the conflicting claims are exactly identical, they are extremely similar and are not patentably distinct from each other, as shown in the example below:
19/028,547
18/982,194
1. A semiconductor memory device comprising:
a substrate;
a plurality of banks comprising a first bank comprising a first memory cell array comprising DRAM cells, and
a second bank comprising a second memory cell array comprising SRAM cells, on the substrate;
a peripheral circuit between the plurality of banks; and
a processing unit adjacent to the second memory cell array.
1. A semiconductor memory device comprising:
a substrate;
a plurality of banks on the substrate, the plurality of banks including a first memory cell array of a first size and
a second memory cell array of a second size, the second size being smaller than the first size;
a peripheral circuit between at least two of the plurality of banks; and
a processor adjacent to the second memory cell array.
Claim 1 of 18/982,194 recites all the limitations recited in claim 1 of 19/028,547, except for the “DRAM” and “SRAM” elements.
However, DRAM and SRAM are well known and commonly used components in semiconductor industries.
For example, Peled specifically teaches a memory system having both DRAM and SRAM [A packet processing system, comprising: a processor; first memory having a first latency; second memory, different from the first memory, having a second latency that is higher than the first latency, wherein a first portion of a queue for queuing data units utilized by the processor is disposed in the first memory, and a second portion of the queue is disposed in the second memory; and a queue manager configured to (i) selectively push new data units to the second portion of the queue and generate a linking indication linking a new data unit to an earlier-received data unit in the queue, and (ii) transfer, according to an order, one or more queued data units from the second portion of the queue disposed in the second memory to the first portion of the queue disposed in the first memory prior to popping the queued data unit from the queue, and to update the linking indication (claim 1);
The packet processing system of claim 1, wherein the first memory comprises static random-access memory (SRAM), and wherein the second memory comprises dynamic random-access memory (DRAM) (claim 4)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to have a SRAM and DRAM as the first and second memory, respectively, as specifically demonstrated by Peled, and to incorporate it into the existing scheme disclosed by claim 1 of 18/982,194, in order to support DRAM and SRAM, which represent two of the most commonly used memory types.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claim 20 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Peled et al. (US Patent Application Publication 2015/0215226, hereinafter Peled).
As to claim 20, Peled teaches A memory system [memory system as shown in figure 1, where the memory system includes a first memory (110) and a second memory (112)] comprising:
a semiconductor memory device [semiconductor memory device as shown in figure 4, where the memory device includes a first memory (110) and a second memory (112)] comprising:
a plurality of banks comprising a first bank comprising a first memory cell array comprising a DRAM cell, and a second bank comprising a second memory cell array comprising an SRAM cell [as shown in figure 4, where the first memory (110) is a SRAM, and the second memory (112) is a DRAM; In the packet processing system of FIG. 1, a first portion of the queue is defined in the first memory 110, and a second portion of the queue is defined in the second memory 112. The single queue thus extends across both of the first and second memories 110, 112. In an embodiment, the low latency first memory 110 and the high latency second memory 112 are disposed on separate physical devices and/or are constructed using different microarchitectural design (e.g., the low latency first memory 110 comprises SRAM and the high latency second memory 112 comprises DRAM, in an embodiment) … (¶ 0020)]; and
a processing unit adjacent to the second memory cell array [… Some memory space that is located in relative close proximity to a packet processing core of the packet processing system, is limited in size, is relatively low latency and is comparatively expensive. Conversely, other memory space that is located relatively far away from the packet processing core typically has the potential of being significantly larger than memory space that is located in close proximity to the packet processing system. However, while the other memory space is comparatively less expensive it also exhibits relatively high latency (¶ 0003); … The first memory 110 comprises static random-access memory (SRAM), in an embodiment, or other suitable internal memory configurations. In an example, the first memory 110 is in relative close proximity to processor components of the one or more processors of the packet processing system 100 … (¶ 0016); FIG. 6 is a flow diagram 600 depicting steps of an example method for establishing and managing a queue in the packet processing system 100 of FIGS. 1-4. As described in detail below, when the queue is initially established, space for N data units of the queue is allocated in the first memory 110, which comprises low latency memory (e.g., SRAM) that is disposed in relative close proximity to a processing unit, in an embodiment. When additional space is required for the queue, the additional space is allocated in the first memory 110 on an as-available basis or in the second memory 112. The second memory 112 comprises high latency memory (e.g., DRAM) that is disposed a relatively large distance from the processing unit, in an embodiment (¶ 0052)]; and
a memory controller configured to control operations of the semiconductor memory device [In an example, for each queue, the queue manager 106 monitors a number of data units of the queue that are stored in the first memory 110. Based on a determination that the number of data units is less than a threshold value, the queue manager 106 transfers one or more data units of the queue from the second memory 112 to the first memory 110 … In an example, the data units are read from the second memory 112 and written to the first memory 110 using a direct memory access (DMA) technique (e.g., using a DMA controller of the first memory 110) (¶ 0032)].
9. Claims 1, 3-8, 14-18, and 20 are rejected under 35 102(a)(1) and 102(a)(2) as being anticipated by Matsuo et al. (US Patent 5,663,905, hereinafter Matsuo).
As to claim 14, Matsuo teaches A semiconductor memory device [as shown in figure 2] comprising:
a substrate [A method of manufacturing such semiconductor memory device comprises steps for forming a first insulating film on a semiconductor substrate, forming, on the first insulating film, word lines to form gate electrodes of the first to third access transistors, a first gate wiring to form a gate electrode of the first driver transistor and a second gate wiring to form a gate electrode of the second driver transistor, forming, within the semiconductor substrate, the source/drain regions of the first to third access transistors and first and second driver transistors and forming, on the semiconductor substrate … (c4 L32-48)];
a plurality of banks on the substrate and comprising a first bank comprising a first memory cell array comprising plurality of first cells and a second bank comprising a second memory cell array comprising a plurality of second cells [as shown in figure 5, where there are at least two SRAM memory cell arrays (SA, SA0) and one DRAM memory cell array (DA); also see figure 19; A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs … (abstract)];
a peripheral circuit between the plurality of banks [as shown in figures 5-7, where the row decoders and column decoders represent the corresponding peripheral circuits; as shown in figure 17, where a data exchange circuit (16) is between the SRAM array (SA) and the DRAM array (DA)]; and
a processing unit adjacent to the second memory cell array [as shown in figure 17, where a data exchange circuit (16), which represents the corresponding “processing unit,” is adjacent to the SRAM array (SA); FIG. 15 is a block diagram illustrating a total structure of the semiconductor memory device depending on an embodiment 9 of the present invention. Referring to FIG. 15, this semiconductor memory device further comprises a data exchange circuit 16. The data exchange circuit 16 mutually exchanges the data of SRAM circuit and the data of DRAM circuit … In this embodiment, when the SRAM memory cell SMC is first accessed and subsequently the DRAM memory cell DMC is then accessed, total access rate becomes fast, but when the DRAM memory cell is first accessed, the access rate almost does not change from the existing one. The data exchange circuit 16 exchanges data when the data of low access frequency is stored in the SRAM memory cell array SA and the data of high access frequency is stored in the DRAM memory cell array DA … The data exchange circuit 16 performs data exchange between the SRAM memory cell SMC and the DRAM memory cell DMC conforming to the LRU system … (c19 L31 to c20 L28)], wherein a number of the plurality of second cells is less than a number of the plurality of first cells [As will be obvious from this embodiment 19, the small number Of SRAM memory cells SMC and the large number of DRAM memory cells DMC may be connected in common to one bit line pair (c35 L40-43)], and wherein each of the plurality of second cell is smaller in size than each of the plurality of first cells [As explained above, since the data is latched by the flip-flop circuit in the SRAM memory cell SMC, the refresh operation is unnecessary, but since data is stored in the capacitor Cs in the DRAM memory cell DMC, the refresh operation is necessary. However, since the SRAM memory cell SMC is composed of six elements, it occupies a large area but since the DRAM memory cell DMC is composed of two elements, it occupies a smaller area. In general, the occupation area of the SRAM memory cell SMC is 2 to 4 times that of the DRAM memory cell DMC (c11 L1-10);
it is noted that this limitation introduces inconsistency with claim 15, and clarifications/corrections are need, as explained earlier in the “112(b) rejections” Section previously presented in this Office Action].
As to claim 15, Matsuo teaches The semiconductor memory device of claim 14, wherein each of the plurality of first cells comprises a DRAM cell, and wherein each of the plurality of second cells comprises an SRAM cell [as shown in figure 5, where there are at least two SRAM memory cell arrays (SA, SA0) and one DRAM memory cell array (DA); also see figure 19; A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs … (abstract)].
As to claim 16, Matsuo teaches The semiconductor memory device of claim 14, wherein each of the plurality of banks comprises the first memory cell array and the second memory cell array, wherein the second memory cell array is closer than the first memory cell array to the peripheral circuit [as shown in figure 5, where the SRAM array (SA and SA0) are closer to the row decoders (20 and 21), respectively than the DRAM array (DA)]; and wherein the processing unit is between the second memory cell array and the peripheral circuit [as shown in figure 17, where a data exchange circuit (16) is between the SRAM array (SA) and the DRAM array (DA) and the row decoder (1)].
As to claim 17, Matsuo teaches The semiconductor memory device of claim 14, wherein the first bank comprises the first memory cell array and is free of the second cells; and wherein the second bank comprises the second memory cell array, and is free of the first cells [a SRAM array comprises only SRAM memory cells, and a DRAM array contains only DRAM memory cells -- as shown in figure 5, where there are at least two SRAM memory cell arrays (SA, SA0) and one DRAM memory cell array (DA); also see figure 19; A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs … (abstract)].
As to claim 18, Matsuo teaches The semiconductor memory device of claim 17, wherein the first bank is at a first side of the peripheral circuit and the second bank is at a second side of the peripheral circuit which is opposite of the first side [as shown in figure 5, where the DRAM array (DA) and the SRAM array (SA) are at the opposite sides of the row decoders (20, 21)].
As to claim 20, Matsuo teaches A memory system comprising: a semiconductor memory device [as shown in figures 2, 5, and 19] comprising: a plurality of banks comprising a first bank comprising a first memory cell array comprising a DRAM cell, and a second bank comprising a second memory cell array comprising an SRAM cell [as shown in figure 5, where there are at least two SRAM memory cell arrays (SA, SA0) and one DRAM memory cell array (DA); also see figure 19; A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs … (abstract)]; and a processing unit adjacent to the second memory cell array [as shown in figure 17, where a data exchange circuit (16), which represents the corresponding “processing unit,” is adjacent to the SRAM array (SA); FIG. 15 is a block diagram illustrating a total structure of the semiconductor memory device depending on an embodiment 9 of the present invention. Referring to FIG. 15, this semiconductor memory device further comprises a data exchange circuit 16. The data exchange circuit 16 mutually exchanges the data of SRAM circuit and the data of DRAM circuit … In this embodiment, when the SRAM memory cell SMC is first accessed and subsequently the DRAM memory cell DMC is then accessed, total access rate becomes fast, but when the DRAM memory cell is first accessed, the access r4ate almost does not change from the existing one. The data exchange circuit 16 exchanges data when the data of low access frequency is stored in the SRAM memory cell array SA and the data of high access frequency is stored in the DRAM memory cell array DA … The data exchange circuit 16 performs data exchange between the SRAM memory cell SMC and the DRAM memory cell DMC conforming to the LRU system … (c19 L31 to c20 L28)]; and a memory controller configured to control operations of the semiconductor memory device [Moreover, since the data of high access frequency is almost stored in the SRAM memory cell array SA, this semiconductor memory device has the access rate which is substantially equal to that of SRAM. Therefore, it is now possible to make direct access to this semiconductor memory device from the CPU without particularly providing a cash memory (c20 L65 to c21 L4); As described in regard to the embodiment 13, when a cash memory is provided between CPU and main memory, CPU generally makes access to the cash memory. If cash mistake occurs, the data be accessed is transferred to the cash memory from the main memory. Such data transfer is carried out in every block of the predetermined size (c27 L11-16)].
As to claim 1, it recites substantially the same limitations as in claim 14, and is rejected for the same reasons set forth in the analysis of claim 14. Refer to “As to claim 14” presented earlier in this Office Action for details.
As to claim 3, Matsuo teaches The semiconductor memory device of claim 1 wherein the second memory cell array is closer than the first memory cell array to the peripheral circuit [as shown in figure 5, where the SRAM array (SA and SA0) are closer to the row decoders (20 and 21), respectively than the DRAM array (DA)], and wherein the processing unit is between the second memory cell array and the peripheral circuit [as shown in figure 17, where a data exchange circuit (16) is between the SRAM array (SA) and the DRAM array (DA) and the row decoder (1)].
As to claim 4, it recites substantially the same limitations as in claim 18, and is rejected for the same reasons set forth in the analysis of claim 18. Refer to “As to claim 18” presented earlier in this Office Action for details.
As to claim 5, Matsuo teaches The semiconductor memory device of claim 1, wherein the peripheral circuit comprises a first peripheral circuit and a second peripheral circuit, and wherein the plurality of banks are between the first peripheral circuit and the second peripheral circuit [as shown in figure 5, where the DRAM array (DA) and the SRAM array (SA) are between the row decoders (20, 21)].
As to claim 6, it recites substantially the same limitations as in claim 17, and is rejected for the same reasons set forth in the analysis of claim 17. Refer to “As to claim 17” presented earlier in this Office Action for details.
As to claim 7, it recites substantially the same limitations as in claim 14, and is rejected for the same reasons set forth in the analysis of claim 14. Refer to “As to claim 14” presented earlier in this Office Action for details.
As to claim 8, it recites substantially the same limitations as in claim 18, and is rejected for the same reasons set forth in the analysis of claim 18. Refer to “As to claim 18” presented earlier in this Office Action for details.
As to claim 10, Matsuo teaches The semiconductor memory device of claim 1, wherein a DRAM cell of the DRAM cells comprises: a DRAM cell transistor; and a capacitor connected to the DRAM cell transistor, wherein the DRAM cell transistor comprises a metal oxide field effect transistor [The DRAM will be first schematically explained hereunder. In the DRAM developed after the generation of 4K bits, a memory cell having the structure utilizing one N-channel MOS transistor and one capacitor is mainly introduced. Such a memory cell is also employed in the current 1M bits, 4M bits and 16M bits DRAMs … (c1 L23-52)], wherein a SRAM cell of the SRAM cells comprises: a first inverter and a second inverter coupled in parallel between a power terminal and a ground terminal [Next, the refresh operation of this SRAM memory cell SMC will be explained. FIG. 12 is a circuit diagram illustrating only the access transistor T2 and driver transistor T4 in the SRAM memory cell SMC shown in FIG. 11. In FIG. 12, since the potential of the word line WL is H level, the power source voltage Vcc is applied to the gate electrode of the access transistor T2. Therefore, the access transistor T2 and driver transistor T4 form an enhancement load type inverter … Meanwhile, the access transistor T3 and driver transistor T5 also form an enhancement load type inverter. Since these inverters are cross-coupled, an output potential Vout of one inverter is supplied as an input potential Vin of the other inverter and an output potential Vout of the other inverter is supplied as an input potential Vin of one inverter … (c18 L33-50)]; and a first pass gate transistor and a second pass gate transistor connected to respective output terminals of the first inverter and the second inverter, wherein the first inverter comprises a first pull-up transistor and a first pull-down transistor coupled in series, and wherein the second inverter comprises a second pull-up transistor and a second pull-down transistor coupled in series [FIG. 29 is a block diagram illustrating a structure of a selector 61 and a signal generating circuit 8 shown in FIG. 21. With reference to FIG. 29, the selector 61 comprises transfer gates 611 and 612 consisting of P and N channel MOS transistors and an inverter 610 for inverting the mode switching signal MS and applying respectively the inverted signal to the P channel MOS transistor of the transfer gate 611 and the N channel MOS transistor of the transfer gate 612 … (c31 L19-27); FIG. 1 is a circuit diagram illustrating in detail one SRAM memory cell SMC and one DRAM memory cell DMC in the semiconductor memory device shown in FIG. 2. With reference to FIG. 1, the SRAM memory cell SMC is composed of a pair of resistances R1, R2 having high resistance values and four N channel MOS transistors T2-T5 … The resistance R1 pulls up the potential of the memory node M2 up to the power source voltage Vcc, while the resistance R2 pulls up the potential of the memory node M3 up to the power source voltage Vcc … (c9 L19-64)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo et al. (US Patent 5,663,905, hereinafter Matsuo), and in view of Park et al. (US Patent Application Publication 2014/0146589, hereinafter Park).
As to claim 19, Matsuo teaches The semiconductor memory device of claim 17, wherein the semiconductor memory device comprises a plurality of second memory cell arrays including the second memory cell array [as shown in figures 5 and 19, where there are a plurality of SRAM arrays (SA)] and a plurality of processing units [this limitation is taught by Park – as shown in figure 6, where there are two processors, P1 and P2; Referring to FIG. 6, a semiconductor memory device may include four memory banks 100-1, 100-2, 100-3, and 110-1, two ports 132 and 134, and an arbitration circuit 122 … The first port 132 may be connected with a first processor P1, and the second port 134 may be connected with a second processor P2. The first processor P1 may access the first memory bank 100-1 via a first line FL in a dedicated manner … (¶ 0099-0109)] including the processing unit [as shown in figure 17, where a data exchange circuit (16), which represents the corresponding “processing unit,” is adjacent to the SRAM array (SA); FIG. 15 is a block diagram illustrating a total structure of the semiconductor memory device depending on an embodiment 9 of the present invention. Referring to FIG. 15, this semiconductor memory device further comprises a data exchange circuit 16. The data exchange circuit 16 mutually exchanges the data of SRAM circuit and the data of DRAM circuit … In this embodiment, when the SRAM memory cell SMC is first accessed and subsequently the DRAM memory cell DMC is then accessed, total access rate becomes fast, but when the DRAM memory cell is first accessed, the access rate almost does not change from the existing one. The data exchange circuit 16 exchanges data when the data of low access frequency is stored in the SRAM memory cell array SA and the data of high access frequency is stored in the DRAM memory cell array DA … The data exchange circuit 16 performs data exchange between the SRAM memory cell SMC and the DRAM memory cell DMC conforming to the LRU system … (c19 L31 to c20 L28)]], wherein the plurality of second memory cell arrays are on the substrate in an array comprising a plurality of rows [as shown in figure 5], and wherein each of the plurality of processing units is in the second bank and adjacent to a respective one of the plurality of rows [as shown in figure 17, where a data exchange circuit (16), which represents the corresponding “processing unit,” is adjacent to the SRAM array (SA); FIG. 15 is a block diagram illustrating a total structure of the semiconductor memory device depending on an embodiment 9 of the present invention. Referring to FIG. 15, this semiconductor memory device further comprises a data exchange circuit 16. The data exchange circuit 16 mutually exchanges the data of SRAM circuit and the data of DRAM circuit … In this embodiment, when the SRAM memory cell SMC is first accessed and subsequently the DRAM memory cell DMC is then accessed, total access rate becomes fast, but when the DRAM memory cell is first accessed, the access rate almost does not change from the existing one. The data exchange circuit 16 exchanges data when the data of low access frequency is stored in the SRAM memory cell array SA and the data of high access frequency is stored in the DRAM memory cell array DA … The data exchange circuit 16 performs data exchange between the SRAM memory cell SMC and the DRAM memory cell DMC conforming to the LRU system … (c19 L31 to c20 L28)].
Regarding claim 19, Matsuo does not teach a plurality of processing units.
However, a system with a plurality of processing units, such as a multiprocessor system, is well known and commonly deployed in the art to facilitate parallel processing for enhanced throughput.
For example, Park specifically teaches a plurality of processing units associated with a plurality of SRAM and DRAM banks [as shown in figure 6, where there are two processors, P1 and P2; Referring to FIG. 6, a semiconductor memory device may include four memory banks 100-1, 100-2, 100-3, and 110-1, two ports 132 and 134, and an arbitration circuit 122 … The first port 132 may be connected with a first processor P1, and the second port 134 may be connected with a second processor P2. The first processor P1 may access the first memory bank 100-1 via a first line FL in a dedicated manner … (¶ 0099-0109)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to have a plurality of processing units associated with a plurality of SRAM and DRAM banks, as specifically demonstrated by Park, and to incorporate it into the existing scheme disclosed by Matsuo, in order to facilitate, and take advantage of the benefits offered by, a multiprocessor system.
As to claim 9, it recites substantially the same limitations as in claim 19, and is rejected for the same reasons set forth in the analysis of claim 19. Refer to “As to claim 19” presented earlier in this Office Action for details.
11. Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo et al. (US Patent 5,663,905, hereinafter Matsuo), and in view of Koldiaev et al. (US Patent Application Publication 2014/0106523, hereinafter Koldiaev).
As to claim 11, it recites substantially the same limitations as in claim 10, and is rejected for the same reasons set forth in the analysis of claim 10. Refer to “As to claim 10” presented earlier in this Office Action for details.
Further regarding claim 11, Matsuo does not expressively teach the DRAM cell comprises a ferroelectrics field effect transistor.
However, a ferroelectrics field effect transistor is well known and has been commonly and extensively used in the art.
For example, Koldiaev specifically teaches a DRAM cell implemented using a ferroelectrics field effect transistor [… Many memory devices such as DRAM, NOR and NAND Flash (floating gate, trap-based, and ferroelectric based) … (¶ 0030); FIG. 26a is a layout view of a NOR 1T Flash cell with 1 transistor and 2 bits per cell fabricated using VSTB-FET design where a ferroelectric dielectric stack (such as SiO2-SrTiO3, Pb(TiZr)O3, Sr2(TaNb)2O7 and the like) or SONOS (TANOS and the like) stack is formed as the gate stack. By repeating this column of cells to the left and to the right a NOR Flash array can be formed with 2 bits per cell … (¶ 0066-0071); FIG. 30a is a layout view of a DRAM cell group to illustrate the location of BL's, WL, iso-plugs, Drain connected to the Capacitor (not shown), Source connected to the BL … (¶ 0077-0082); If necessarily, System-on-Chip, ASIC, and other products, or stand alone memory can be fabricated using the VSTB-FET's. The VSTB-FET device concept and fabrication method of therein are very flexible and allows to design and to fabricate many types of embedded and stand alone memories such as DRAM (access and periphery transistors), SRAM, and Flash NOR and NAND non-volatile memory … A slight modification of 2T NOR cell can be used for fabricating a DRAM with a MOSFET having a gate dielectric stack made of a ferroelectric material (FeFET) and a non-ferroelectric gate dielectric access transistor comprises the memory cell where both FET are made in a form of VSTB-FET devices (¶ 0118)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to have a DRAM cell implemented using a ferroelectrics field effect transistor, as specifically demonstrated by Koldiaev, and to incorporate it into the existing scheme disclosed by Matsuo, because Koldiaev teaches it offers flexibility and allows integration of different type of components [If necessarily, System-on-Chip, ASIC, and other products, or stand alone memory can be fabricated using the VSTB-FET's. The VSTB-FET device concept and fabrication method of therein are very flexible and allows to design and to fabricate many types of embedded and stand alone memories such as DRAM (access and periphery transistors), SRAM, and Flash NOR and NAND non-volatile memory (NVM): trap-based such as TANOS and the like, polarization based such as SrTiO2 ferroelectric and the like, and floating gate based NVM as well as PCM-based NVM … (¶ 0118)].
As to claim 12, Matsuo in view of Koldiaev teaches The semiconductor memory device of claim 11, wherein the DRAM cell transistor comprises: a first active pattern having a first fin [Koldiaev -- The device 2000 essentially has two gates, one on either side of the channel of the device. Because the double gate device 2000 has a gate on each side of the channel, thickness (Tsi) of the silicon body can be double that of a single gate device and still obtain a fully depleted transistor operation. That is, with a double gate device 2000 a fully depleted transistor can be formed where Tsi=(2*Lg)/3. The most manufacturable form of the double gate (DG) device 2000, however, requires that the body 2020 patterning be done with photolithography that is 0.7.times. smaller than that used to pattern the gate length (Lg) of the device … A bit of improvement of the DG SOI FinFET is made as illustrated in FIG. 3a and FIG. 3b where the thick dielectric on the top of the FinFET was made as thin as the gate dielectric and the FinFET called as tri-gate since it has 3 active sides of the Fin as the channel. This innovation makes the effective channel width more beneficial. And it does make it more manufacturable for a practically achievable modest aspect ratio of the Fin to be about 1 to 3 … (¶ 0010-0011)]; a first gate electrode on the first active pattern [Koldiaev -- The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices (abstract)]; a ferroelectrics layer between the first active pattern and the first gate electrode [Koldiaev -- [… Many memory devices such as DRAM, NOR and NAND Flash (floating gate, trap-based, and ferroelectric based) … (¶ 0030); FIG. 26a is a layout view of a NOR 1T Flash cell with 1 transistor and 2 bits per cell fabricated using VSTB-FET design where a ferroelectric dielectric stack (such as SiO2-SrTiO3, Pb(TiZr)O3, Sr2(TaNb)2O7 and the like) or SONOS (TANOS and the like) stack is formed as the gate stack. By repeating this column of cells to the left and to the right a NOR Flash array can be formed with 2 bits per cell … (¶ 0066-0071); and first source/drain patterns on opposing sides of the first active pattern [Koldiaev -- The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices (abstract)]; wherein at least one of the first pass gate transistor, the second pass gate transistor, the first pull-up transistor, the first pull-down transistor, the second pull-up transistor, and the second pull-down transistor comprises: a second active pattern having a second fin; a second gate electrode on the second active pattern [Koldiaev -- Fabrication of the super-thin body on SOI with a required uniformity across a 300 mm (or 450 mm in future) wafer is not possible. FinFET on SOI is proven to be not manufacturable for a number of reasons observed as many unsuccessful efforts to implement it in the mass production. Bulk-FinFET (a.k.a. tri-gate) with a modest aspect ratio of the Fin width to height is implemented into the mass production at about 24 nm and now has become the main stream in R&D activity across the industry. Scaling of the latter concept is under scrupulous attention. For the technology nodes at and below 10 nm it seems to be rather difficult to scale the bulk FinFET as a tri-gate structure to a highly manufacturable device. A very thin Fin below 6 nm keeping a practical aspect ratio is difficult to fabricate due Fin's mechanical fragility. For a tri-gate MOSFET structure with less than 20 nm channel length, a thin Fin of 9 nm or less is needed. For such a thin Fin the quantum confinement effects of the inversion layer formation suggest little merits in having double gate not even talking about the third gate … (¶ 0027); 6T SRAM array is a very frequently used embedded memory in many ULSI products. SRAM typical design consists of 6 transistors where 2 pull-down nMOSFET transistors are 2.times. to 3.times. more powerful versus 2 pull-up pMOSFET transistors and Word-line access nMOSFET transistors … (¶ 0127)]; and second source/drain patterns on opposing sides of the second active pattern, and wherein a height of the first fin of the first active pattern is equal to a height of the second fin of the second active pattern, relative to the substrate [Koldiaev -- FIG. 30a is a layout view of a DRAM cell group to illustrate the location of BL's, WL, iso-plugs, Drain connected to the Capacitor (not shown), Source connected to the BL … (¶ 0077-0082); 1. Scaling of such a sloppy Fin goes to its limit when thinning at the bottom results in over-etching the tip and the Fin-height/Fin-thickness aspect ratio is self-limited … (¶ 0020-0027); … The distance between the top surface 107 and the bottom surface 106 defines the height of the semiconductor body 100. In the embodiment of the present invention the body height is approximately equal to the channel width W.sub.g. Actually the channel width is equal to semiconductor body 100 height minus the gate-to-substrate isolation 400 with a thickness T.sub.gs (¶ 0096)].
12. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuo et al. (US Patent 5,663,905, hereinafter Matsuo), and in view of Shu et al. (US Patent Application Publication 2016/0005458, hereinafter Shu).
As to claim 13, Matsuo teaches The semiconductor memory device of claim 1, further comprising: a plurality of first bit lines intersecting the first memory cell array in a first direction parallel to an upper surface of the substrate; and a plurality of second bit lines and a plurality of dummy lines intersecting the second memory cell array in the first direction, wherein first ones of the plurality of first bit lines are aligned with the plurality of second bit lines along the first direction, wherein second ones of the plurality of first bit lines are aligned with the plurality of dummy lines along the first direction, and wherein the plurality of first bit lines are electrically connected to the first memory cell array, the plurality of second bit lines are electrically connected to the second memory cell array, and the plurality of dummy lines are electrically isolated from the second memory cell array [A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns (abstract); FIG. 2 is a block diagram illustrating a total structure of a semiconductor memory device depending on an embodiment 1 of the present invention. With reference to FIG. 2, the semiconductor memory device comprises n word lines WL1-WLn arranged in the n rows, (k+m) pairs of bit lines SBL1, /SBL1-SBLk, /SBLk and DBL1, /DBL1-DBLm, /DBLm arranged crossing the word lines WL1-WLn, a row decoder 1 for selecting one word line among WL1-WLn and a column decoder 2 for selecting a pair of the bit lines from the bit lines SBL1, /SBL1-SBLk, /SBLk and DBL1, /DBL1-DBLm, /DBLm … (c7 L65 to c8 L27)].
Regarding claim 13, Matsuo does not teach dummy lines.
However, dummy lines are well known and commonly used in semiconductor memory devices to ensure manufacturing uniformity, improve pattern fidelity, control electrical timing, and Preventing Proximity Effects.
For example, Shu specifically teaches using dummy lines in a memory device [An SRAM memory device comprising: a local section bit line including: a plurality of sectioned bit lines (SBLs), each comprising: a local bit line; one or more memory cells connected to the local bit line; a local complement bit line connected to the memory cell; & a pass gate coupled to the local bit line; a local shared sense amplifier; a local shared data driver; a global bit line; and a dummy global bit line that is arranged along or in a comparable path of the global bit line; wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line (claim 21); The invention of claim 21 further comprising circuitry configured to: access a plurality of sectioned bit lines, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line, wherein a dummy global bit line is arranged along or in a comparable path of the global bit line; pass data/signals to or from memory cells within the sectioned bit line via the pass gates, wherein the pass gates are configured to connect and isolate the sectioned bit lines and the global bit line; determine an estimated delay on the global bit line via measurement of emulated delay information on the dummy global bit line; and utilize the estimated delay and/or the emulated delay information to improve timing tracking (claim 25)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to have a plurality of dummy lines, as specifically demonstrated by Shu, and to incorporate it into the existing scheme disclosed by Matsuo, in order to ensure manufacturing uniformity, improve pattern fidelity, control electrical timing, and Preventing Proximity Effects.
13. Claims 1-7, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ayukawa et al. (US Patent Application Publication 2001/0014052, hereinafter Ayukawa), and in view of Peled et al. (US Patent Application Publication 2015/0215226, hereinafter Peled).
As to claim 1, Ayukawa teaches A semiconductor memory device [examples of semiconductor memories as shown in figure 1; Peled also teaches this limitation – semiconductor memory device as shown in figure 4, comprising a first memory (110) and a second memory (112)] comprising:
a substrate [FIG. 1 shows a configuration of the memory macro of the present invention and how to compose the memory macro. A central processing unit CPU, which is an example of a large scaled logic circuit and a memory macro MM, which is an example of a large capacity memory, are integrated on a semiconductor integrated circuit device CHIP formed on a semiconductor substrate (on a chip) … (¶ 0055); A semiconductor integrated circuit device having a memory on a semiconductor substrate, said memory comprising: … (claim 1)];
a plurality of banks comprising a first bank comprising a first memory cell array comprising DRAM cells [a plurality of DRAM banks as shown in figure 1, MM1, 10; Peled also teaches this limitation – as shown in figure 4, where the second memory (112) is a DRAM; … In an embodiment, the low latency first memory 110 and the high latency second memory 112 are disposed on separate physical devices and/or are constructed using different microarchitectural design (e.g., the low latency first memory 110 comprises SRAM and the high latency second memory 112 comprises DRAM … (¶ 0020)], and a second bank comprising a second memory cell array comprising SRAM cells [a plurality of SRAM banks as shown in figure 1, MM2, 12; the cache banks (MM3, 11) are also made of SRAM cells -- Since the operation of the SRAM bank module 12 is fast, it is possible to compose a large capacity memory provided with a cache function using the SRAM bank module 12. Since the SRAM portion to be accessed fast comparatively and the DRAM portion to be accessed rather slowly are integrated in different address ranges, the SRAM portion is composed so as to function as a so-called cache, which i s to be accessed fast … (¶ 0069); Peled also teaches this limitation – as shown in figure 4, where the first memory (110) is a SRAM; … In an embodiment, the low latency first memory 110 and the high latency second memory 112 are disposed on separate physical devices and/or are constructed using different microarchitectural design (e.g., the low latency first memory 110 comprises SRAM and the high latency second memory 112 comprises DRAM … (¶ 0020)], on the substrate [A semiconductor integrated circuit device having a memory on a semiconductor substrate, said memory comprising: … (claim 1)];
a peripheral circuit between the plurality of banks [as shown in figure 6, where the peripheral circuits include controller, X decoder, Y decoder, and sense amplifier; also see figure 13]; and
a processing unit adjacent to the second memory cell array [Ayukawa teaches a processing unit associated with the memory banks -- as shown in figure 1, where a CPU is associated with the memory element, and each of the MM1, MM2, MM3, and MM4 includes a cache controller (16)/bank controller (15) associated with the memory banks; Peled more expressively teaches a processing unit adjacent to the second memory cell array -- … Some memory space that is located in relative close proximity to a packet processing core of the packet processing system, is limited in size, is relatively low latency and is comparatively expensive. Conversely, other memory space that is located relatively far away from the packet processing core typically has the potential of being significantly larger than memory space that is located in close proximity to the packet processing system. However, while the other memory space is comparatively less expensive it also exhibits relatively high latency (¶ 0003); … The first memory 110 comprises static random-access memory (SRAM), in an embodiment, or other suitable internal memory configurations. In an example, the first memory 110 is in relative close proximity to processor components of the one or more processors of the packet processing system 100 … (¶ 0016); FIG. 6 is a flow diagram 600 depicting steps of an example method for establishing and managing a queue in the packet processing system 100 of FIGS. 1-4. As described in detail below, when the queue is initially established, space for N data units of the queue is allocated in the first memory 110, which comprises low latency memory (e.g., SRAM) that is disposed in relative close proximity to a processing unit, in an embodiment. When additional space is required for the queue, the additional space is allocated in the first memory 110 on an as-available basis or in the second memory 112. The second memory 112 comprises high latency memory (e.g., DRAM) that is disposed a relatively large distance from the processing unit, in an embodiment (¶ 0052)].
Regarding claim 1, Ayukawa teaches a processing unit associated with the memory banks [as shown in figure 1, where a CPU is associated with the memory element, and each of the MM1, MM2, MM3, and MM4 includes a cache controller (16)/bank controller (15) associated with the memory banks], but does not expressively teach the processing unit is adjacent to the second memory cell array.
However, Peled specifically teaches a semiconductor memory device includes both a SRAM bank and a DRAM bank, wherein a processing unit is adjacent to the SRAM memory cell array [… Some memory space that is located in relative close proximity to a packet processing core of the packet processing system, is limited in size, is relatively low latency and is comparatively expensive. Conversely, other memory space that is located relatively far away from the packet processing core typically has the potential of being significantly larger than memory space that is located in close proximity to the packet processing system. However, while the other memory space is comparatively less expensive it also exhibits relatively high latency (¶ 0003); … The first memory 110 comprises static random-access memory (SRAM), in an embodiment, or other suitable internal memory configurations. In an example, the first memory 110 is in relative close proximity to processor components of the one or more processors of the packet processing system 100 … (¶ 0016); FIG. 6 is a flow diagram 600 depicting steps of an example method for establishing and managing a queue in the packet processing system 100 of FIGS. 1-4. As described in detail below, when the queue is initially established, space for N data units of the queue is allocated in the first memory 110, which comprises low latency memory (e.g., SRAM) that is disposed in relative close proximity to a processing unit, in an embodiment. When additional space is required for the queue, the additional space is allocated in the first memory 110 on an as-available basis or in the second memory 112. The second memory 112 comprises high latency memory (e.g., DRAM) that is disposed a relatively large distance from the processing unit, in an embodiment (¶ 0052)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to have a processing unit is adjacent to the SRAM memory cell array in a memory device including both SRAM and DRAM, as specifically demonstrated by Peled, and to incorporate it into the existing scheme disclosed by Ayukawa, because Peled teaches doing so allows memory access latency for the processing unit be reduced due to the low latency of SRAM, which in turn increases the throughput of the processing unit [FIG. 6 is a flow diagram 600 depicting steps of an example method for establishing and managing a queue in the packet processing system 100 of FIGS. 1-4. As described in detail below, when the queue is initially established, space for N data units of the queue is allocated in the first memory 110, which comprises low latency memory (e.g., SRAM) that is disposed in relative close proximity to a processing unit, in an embodiment. When additional space is required for the queue, the additional space is allocated in the first memory 110 on an as-available basis or in the second memory 112. The second memory 112 comprises high latency memory (e.g., DRAM) that is disposed a relatively large distance from the processing unit, in an embodiment (¶ 0052)].
As to claim 2, Ayukawa in view of Peled teaches The semiconductor memory device of claim 1 wherein the semiconductor memory device comprises a plurality of processing units [Ayukawa -- The method that uses ID numbers as described above can also apply to a multiprocessor system. FIG. 31 shows a block diagram of such a multiprocessor system. In this example, two processors (CPU#1 and CPU#2) share one memory macro MM. This multiprocessor also includes an address bus ABUS, a data bus DBUS, an address ID signal, line, a data ID signal line DID, and a processor ID signal line PID that indicates a processor number. Each processor outputs the processor ID signal PID, which notifies the memory macro M of which of the processors has issued an address when the address is issued. The memory macro MM manages the value of the processor ID signal PID together with the address value, so that the processor ID signal PID is output again when data is output, thereby identifying the object processor to which the data is to be transmitted (¶ 0222)], wherein each of the plurality of banks comprises the first memory cell array and the second memory cell array [Ayukawa – as shown in figure 1, MM2, which includes both DRAM banks (10) and SRAM banks (12)], and wherein respective ones of the plurality of processing units including the processing unit are closer to the second memory cell array of a respective one of the plurality of banks than to the first memory cell array of a respective one of the plurality of banks [Peled -- FIG. 6 is a flow diagram 600 depicting steps of an example method for establishing and managing a queue in the packet processing system 100 of FIGS. 1-4. As described in detail below, when the queue is initially established, space for N data units of the queue is allocated in the first memory 110, which comprises low latency memory (e.g., SRAM) that is disposed in relative close proximity to a processing unit, in an embodiment. When additional space is required for the queue, the additional space is allocated in the first memory 110 on an as-available basis or in the second memory 112. The second memory 112 comprises high latency memory (e.g., DRAM) that is disposed a relatively large distance from the processing unit, in an embodiment (¶ 0052)].
As to claim 3, Ayukawa in view of Peled teaches The semiconductor memory device of claim 1 wherein the second memory cell array is closer than the first memory cell array to the peripheral circuit, and wherein the processing unit is between the second memory cell array and the peripheral circuit [Ayukawa – as shown in figures 1, 6, and 13; Peled – as shown in figure 4].
As to claim 4, Ayukawa in view of Peled teaches The semiconductor memory device of claim 1, wherein some of the plurality of banks are at a first side of the peripheral circuit and some of the plurality of banks are at a second side of the peripheral circuit which is opposite of the first side [Ayukawa – as shown in figures 1, 6, and 13; Peled – as shown in figure 4].
As to claim 5, Ayukawa in view of Peled teaches The semiconductor memory device of claim 1, wherein the peripheral circuit comprises a first peripheral circuit and a second peripheral circuit, and wherein the plurality of banks are between the first peripheral circuit and the second peripheral circuit [Ayukawa -- as shown in figure 6, where the peripheral circuits include controller, X decoder, Y decoder, and sense amplifier; also see figure 13].
As to claim 6, Ayukawa in view of Peled teaches The semiconductor memory device of claim 1, wherein the first bank comprises the first memory cell array and is free of SRAM cells [Ayukawa – as shown in figure 1, MM1, which includes DRAM banks (10), which contains only DRAM cells.], and wherein the second bank comprises the second memory cell array, and is free of DRAM cells [Ayukawa – as shown in figure 1, MM2, which includes SRAM banks (12), which contains only SRAM cells].
As to claim 7, Ayukawa in view of Peled teaches The semiconductor memory device of claim 6, wherein the peripheral circuit is between the first bank and the second bank [Peled – as shown in figure 4; Ayukawa – as shown in figures 1, 6, and 13].
As to claim 20, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
Conclusion
14. Claims 1-20 are rejected as explained above.
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG JEN TSAI/Primary Examiner, Art Unit 2139
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